2822 #define X0000  BITS4(0,0,0,0)  macro
2920       instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000);  in imm32_to_ireg()
3096             case ARMalu_AND:  subopc = X0000; break;  in emit_ARMInstr()
3118             case ARMsh_SHL: subopc = X0000; break;  in emit_ARMInstr()
3124          instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM);  in emit_ARMInstr()
3704                insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM);  in emit_ARMInstr()
3707                insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X1100,dM);  in emit_ARMInstr()
3727                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000,  in emit_ARMInstr()
3732                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000,  in emit_ARMInstr()
3765          UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);  in emit_ARMInstr()
3775                               X0000,(fD >> 1),X1010,  in emit_ARMInstr()
4092                      opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2);  in emit_ARMInstr()
4101                                BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000);  in emit_ARMInstr()
4142                                BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);  in emit_ARMInstr()
4181                      opc = X0000 | (i->ARMin.NUnaryS.src->index << 2);  in emit_ARMInstr()
4190                                BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);  in emit_ARMInstr()
4258                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,  in emit_ARMInstr()
4266                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,  in emit_ARMInstr()
4286                                X1011, BITS4(D,0,sz2,1), X0000);  in emit_ARMInstr()
4431                                regD, X0000, BITS4(1,Q,M,0), regM);  in emit_ARMInstr()
4514                                X0000, BITS4(N,Q,M,1), regM);  in emit_ARMInstr()
4518                                X0000, BITS4(N,Q,M,1), regM);  in emit_ARMInstr()
5069 #undef X0000