Lines Matching refs:X0100
2826 #define X0100 BITS4(0,1,0,0) macro
3091 case ARMalu_ADD: subopc = X0100; break; in emit_ARMInstr()
3658 case ARMvfp_MUL: pqrs = X0100; break; in emit_ARMInstr()
3683 case ARMvfp_MUL: pqrs = X0100; break; in emit_ARMInstr()
3704 insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM); in emit_ARMInstr()
3710 insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM); in emit_ARMInstr()
3755 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM); in emit_ARMInstr()
3765 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM); in emit_ARMInstr()
3899 X1011, X0100, regD); in emit_ARMInstr()
3909 X1011, X0100, regD); in emit_ARMInstr()
3936 isF64 ? X1011 : X1010, X0100 | (M << 1), Vm); in emit_ARMInstr()
4013 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), in emit_ARMInstr()
4033 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), in emit_ARMInstr()
4271 regD, X0100, BITS4(1,Q,M,0), regM); in emit_ARMInstr()
4275 regD, X0100, BITS4(0,Q,M,0), regM); in emit_ARMInstr()
4383 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, in emit_ARMInstr()
4399 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, in emit_ARMInstr()
4696 X0100, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4700 X0100, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4704 X0100, BITS4(N,Q,M,1), regM); in emit_ARMInstr()
4708 X0100, BITS4(N,Q,M,1), regM); in emit_ARMInstr()
5073 #undef X0100