Lines Matching refs:X1000
2830 #define X1000 BITS4(1,0,0,0) macro
2959 op = X1000; in imm32_to_ireg()
2967 op = X1000; in imm32_to_ireg()
2975 op = X1000; in imm32_to_ireg()
2983 op = X1000; in imm32_to_ireg()
3158 UInt subopc = i->ARMin.CmpOrTst.isCmp ? X1010 : X1000; in emit_ARMInstr()
3659 case ARMvfp_DIV: pqrs = X1000; break; in emit_ARMInstr()
3684 case ARMvfp_DIV: pqrs = X1000; break; in emit_ARMInstr()
3877 UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, in emit_ARMInstr()
3887 UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, in emit_ARMInstr()
3965 *p++ = XXXXXXXX(X1111,X1110, X1000 | (D << 2), Vn, Vd, in emit_ARMInstr()
4014 regN, regD, X1010, X1000, regM); in emit_ARMInstr()
4034 regN, regD, X0111, X1000, regM); in emit_ARMInstr()
4082 opc = X1000 | i->ARMin.NUnaryS.dst->index; in emit_ARMInstr()
4122 opc = X1000 | i->ARMin.NUnaryS.src->index; in emit_ARMInstr()
4163 opc = X1000 | i->ARMin.NUnaryS.src->index; in emit_ARMInstr()
4482 X1000, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4486 X1000, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4546 X1000, BITS4(N,Q,M,1), regM); in emit_ARMInstr()
4593 X1000, BITS4(N,0,M,0), regM); in emit_ARMInstr()
4810 UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD); in emit_ARMInstr()
5077 #undef X1000