Lines Matching refs:instr_addr
145 Addr instr_addr; member
210 static void get_debug_info(Addr instr_addr, const HChar **dir, in get_debug_info() argument
214 instr_addr, in get_debug_info()
218 Bool found_fn = VG_(get_fnname)(instr_addr, fn); in get_debug_info()
334 cachesim_I1_doref_Gen(n->instr_addr, n->instr_len, in log_1IrGen_0D_cache_access()
344 cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, in log_1IrNoX_0D_cache_access()
356 cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, in log_2IrNoX_0D_cache_access()
359 cachesim_I1_doref_NoX(n2->instr_addr, n2->instr_len, in log_2IrNoX_0D_cache_access()
373 cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, in log_3IrNoX_0D_cache_access()
376 cachesim_I1_doref_NoX(n2->instr_addr, n2->instr_len, in log_3IrNoX_0D_cache_access()
379 cachesim_I1_doref_NoX(n3->instr_addr, n3->instr_len, in log_3IrNoX_0D_cache_access()
390 cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, in log_1IrNoX_1Dr_cache_access()
405 cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, in log_1IrNoX_1Dw_cache_access()
450 += (1 & do_cond_branch_predict(n->instr_addr, taken)); in log_cond_branch()
460 += (1 & do_ind_branch_predict(n->instr_addr, actual_dst)); in log_ind_branch()
675 InstrInfo* setup_InstrInfo ( CgState* cgs, Addr instr_addr, UInt instr_len ) in setup_InstrInfo() argument
681 i_node->instr_addr = instr_addr; in setup_InstrInfo()
683 i_node->parent = get_lineCC(instr_addr); in setup_InstrInfo()
884 if (cachesim_is_IrNoX(inode->instr_addr, inode->instr_len)) { in addEvent_Ir()