Lines Matching refs:CLG_
113 Addr CLG_(bb_base);
114 ULong* CLG_(cost_base);
859 idx, CLG_(bb_base) + current_ii->instr_offset, memline); in update_LL_use()
864 CLG_(current_state).collect, loaded->use_base); in update_LL_use()
866 if (CLG_(current_state).collect && loaded->use_base) { in update_LL_use()
876 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; in update_LL_use()
877 loaded->use_base = (CLG_(current_state).nonskipped) ? in update_LL_use()
878 CLG_(current_state).nonskipped->skipped : in update_LL_use()
879 CLG_(cost_base) + current_ii->cost_offset; in update_LL_use()
947 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
952 CLG_(current_state).collect, loaded->use_base); \
954 if (CLG_(current_state).collect && loaded->use_base) { \
967 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
968 loaded->use_base = (CLG_(current_state).nonskipped) ? \
969 CLG_(current_state).nonskipped->skipped : \
970 CLG_(cost_base) + current_ii->cost_offset; \
989 if (!CLG_(current_state).collect) return; in cacheuse_finish()
991 CLG_(bb_base) = 0; in cacheuse_finish()
993 CLG_(cost_base) = 0; in cacheuse_finish()
1068 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I0D()
1071 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes)); in log_1I0D()
1073 if (CLG_(current_state).collect) { in log_1I0D()
1076 if (CLG_(current_state).nonskipped) in log_1I0D()
1077 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I0D()
1079 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I0D()
1082 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I0D()
1093 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_2I0D()
1095 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_2I0D()
1098 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_2I0D()
1099 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) ); in log_2I0D()
1101 if (!CLG_(current_state).collect) return; in log_2I0D()
1103 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_2I0D()
1104 if (CLG_(current_state).nonskipped) { in log_2I0D()
1106 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_2I0D()
1114 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_2I0D()
1116 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_2I0D()
1126 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_3I0D()
1128 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_3I0D()
1130 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size); in log_3I0D()
1133 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_3I0D()
1134 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res), in log_3I0D()
1135 CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) ); in log_3I0D()
1137 if (!CLG_(current_state).collect) return; in log_3I0D()
1139 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_3I0D()
1140 if (CLG_(current_state).nonskipped) { in log_3I0D()
1142 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_3I0D()
1150 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_3I0D()
1152 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_3I0D()
1154 CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]); in log_3I0D()
1165 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dr()
1169 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dr()
1172 if (CLG_(current_state).collect) { in log_1I1Dr()
1175 if (CLG_(current_state).nonskipped) { in log_1I1Dr()
1176 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dr()
1177 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_1I1Dr()
1180 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dr()
1181 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_1I1Dr()
1185 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dr()
1187 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_1I1Dr()
1206 if (CLG_(current_state).collect) { in log_0I1Dr()
1209 if (CLG_(current_state).nonskipped) in log_0I1Dr()
1210 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_0I1Dr()
1212 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_0I1Dr()
1215 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_0I1Dr()
1228 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dw()
1232 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dw()
1235 if (CLG_(current_state).collect) { in log_1I1Dw()
1238 if (CLG_(current_state).nonskipped) { in log_1I1Dw()
1239 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dw()
1240 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_1I1Dw()
1243 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dw()
1244 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_1I1Dw()
1248 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dw()
1250 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_1I1Dw()
1266 if (CLG_(current_state).collect) { in log_0I1Dw()
1269 if (CLG_(current_state).nonskipped) in log_0I1Dw()
1270 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_0I1Dw()
1272 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_0I1Dw()
1275 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_0I1Dw()
1296 if (!CLG_(clo).simulate_cache) { in cachesim_post_clo_init()
1297 CLG_(cachesim).log_1I0D = 0; in cachesim_post_clo_init()
1298 CLG_(cachesim).log_1I0D_name = "(no function)"; in cachesim_post_clo_init()
1299 CLG_(cachesim).log_2I0D = 0; in cachesim_post_clo_init()
1300 CLG_(cachesim).log_2I0D_name = "(no function)"; in cachesim_post_clo_init()
1301 CLG_(cachesim).log_3I0D = 0; in cachesim_post_clo_init()
1302 CLG_(cachesim).log_3I0D_name = "(no function)"; in cachesim_post_clo_init()
1304 CLG_(cachesim).log_1I1Dr = 0; in cachesim_post_clo_init()
1305 CLG_(cachesim).log_1I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1306 CLG_(cachesim).log_1I1Dw = 0; in cachesim_post_clo_init()
1307 CLG_(cachesim).log_1I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1309 CLG_(cachesim).log_0I1Dr = 0; in cachesim_post_clo_init()
1310 CLG_(cachesim).log_0I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1311 CLG_(cachesim).log_0I1Dw = 0; in cachesim_post_clo_init()
1312 CLG_(cachesim).log_0I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1329 CLG_(min_line_size) = (I1c.line_size < D1c.line_size) in cachesim_post_clo_init()
1331 CLG_(min_line_size) = (LLc.line_size < CLG_(min_line_size)) in cachesim_post_clo_init()
1332 ? LLc.line_size : CLG_(min_line_size); in cachesim_post_clo_init()
1336 if (CLG_(min_line_size) < largest_load_or_store_size) { in cachesim_post_clo_init()
1341 (Int)CLG_(min_line_size)); in cachesim_post_clo_init()
1355 CLG_(cachesim).log_1I0D = log_1I0D; in cachesim_post_clo_init()
1356 CLG_(cachesim).log_1I0D_name = "log_1I0D"; in cachesim_post_clo_init()
1357 CLG_(cachesim).log_2I0D = log_2I0D; in cachesim_post_clo_init()
1358 CLG_(cachesim).log_2I0D_name = "log_2I0D"; in cachesim_post_clo_init()
1359 CLG_(cachesim).log_3I0D = log_3I0D; in cachesim_post_clo_init()
1360 CLG_(cachesim).log_3I0D_name = "log_3I0D"; in cachesim_post_clo_init()
1362 CLG_(cachesim).log_1I1Dr = log_1I1Dr; in cachesim_post_clo_init()
1363 CLG_(cachesim).log_1I1Dw = log_1I1Dw; in cachesim_post_clo_init()
1364 CLG_(cachesim).log_1I1Dr_name = "log_1I1Dr"; in cachesim_post_clo_init()
1365 CLG_(cachesim).log_1I1Dw_name = "log_1I1Dw"; in cachesim_post_clo_init()
1367 CLG_(cachesim).log_0I1Dr = log_0I1Dr; in cachesim_post_clo_init()
1368 CLG_(cachesim).log_0I1Dw = log_0I1Dw; in cachesim_post_clo_init()
1369 CLG_(cachesim).log_0I1Dr_name = "log_0I1Dr"; in cachesim_post_clo_init()
1370 CLG_(cachesim).log_0I1Dw_name = "log_0I1Dw"; in cachesim_post_clo_init()
1472 CLG_(clo).dump_instr = True; in cachesim_parse_opt()
1490 FullCost total = CLG_(total_cost), D_total = 0; in cachesim_printstat()
1523 D_total = CLG_(get_eventset_cost)( CLG_(sets).full ); in cachesim_printstat()
1524 CLG_(init_cost)( CLG_(sets).full, D_total); in cachesim_printstat()
1526 CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) ); in cachesim_printstat()
1527 CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) ); in cachesim_printstat()
1596 struct event_sets CLG_(sets);
1598 void CLG_(init_eventsets)() in CLG_() function
1603 CLG_(register_event_group4)(EG_USE, in CLG_()
1606 if (!CLG_(clo).simulate_cache) in CLG_()
1607 CLG_(register_event_group)(EG_IR, "Ir"); in CLG_()
1609 CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "ILmr"); in CLG_()
1610 CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "DLmr"); in CLG_()
1611 CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "DLmw"); in CLG_()
1614 CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "ILmr", "ILdmr"); in CLG_()
1615 CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "DLmr", "DLdmr"); in CLG_()
1616 CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "DLmw", "DLdmw"); in CLG_()
1619 if (CLG_(clo).simulate_branch) { in CLG_()
1620 CLG_(register_event_group2)(EG_BC, "Bc", "Bcm"); in CLG_()
1621 CLG_(register_event_group2)(EG_BI, "Bi", "Bim"); in CLG_()
1624 if (CLG_(clo).collect_bus) in CLG_()
1625 CLG_(register_event_group)(EG_BUS, "Ge"); in CLG_()
1627 if (CLG_(clo).collect_alloc) in CLG_()
1628 CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize"); in CLG_()
1630 if (CLG_(clo).collect_systime) in CLG_()
1631 CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime"); in CLG_()
1634 CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR); in CLG_()
1637 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW); in CLG_()
1638 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_BC, EG_BI); in CLG_()
1639 CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS); in CLG_()
1640 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS); in CLG_()
1644 CLG_(print_eventset)(-2, CLG_(sets).base); in CLG_()
1645 CLG_(print_eventset)(-2, CLG_(sets).full); in CLG_()
1649 CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full); in CLG_()
1650 CLG_(append_event)(CLG_(dumpmap), "Ir"); in CLG_()
1651 CLG_(append_event)(CLG_(dumpmap), "Dr"); in CLG_()
1652 CLG_(append_event)(CLG_(dumpmap), "Dw"); in CLG_()
1653 CLG_(append_event)(CLG_(dumpmap), "I1mr"); in CLG_()
1654 CLG_(append_event)(CLG_(dumpmap), "D1mr"); in CLG_()
1655 CLG_(append_event)(CLG_(dumpmap), "D1mw"); in CLG_()
1656 CLG_(append_event)(CLG_(dumpmap), "ILmr"); in CLG_()
1657 CLG_(append_event)(CLG_(dumpmap), "DLmr"); in CLG_()
1658 CLG_(append_event)(CLG_(dumpmap), "DLmw"); in CLG_()
1659 CLG_(append_event)(CLG_(dumpmap), "ILdmr"); in CLG_()
1660 CLG_(append_event)(CLG_(dumpmap), "DLdmr"); in CLG_()
1661 CLG_(append_event)(CLG_(dumpmap), "DLdmw"); in CLG_()
1662 CLG_(append_event)(CLG_(dumpmap), "Bc"); in CLG_()
1663 CLG_(append_event)(CLG_(dumpmap), "Bcm"); in CLG_()
1664 CLG_(append_event)(CLG_(dumpmap), "Bi"); in CLG_()
1665 CLG_(append_event)(CLG_(dumpmap), "Bim"); in CLG_()
1666 CLG_(append_event)(CLG_(dumpmap), "AcCost1"); in CLG_()
1667 CLG_(append_event)(CLG_(dumpmap), "SpLoss1"); in CLG_()
1668 CLG_(append_event)(CLG_(dumpmap), "AcCost2"); in CLG_()
1669 CLG_(append_event)(CLG_(dumpmap), "SpLoss2"); in CLG_()
1670 CLG_(append_event)(CLG_(dumpmap), "Ge"); in CLG_()
1671 CLG_(append_event)(CLG_(dumpmap), "allocCount"); in CLG_()
1672 CLG_(append_event)(CLG_(dumpmap), "allocSize"); in CLG_()
1673 CLG_(append_event)(CLG_(dumpmap), "sysCount"); in CLG_()
1674 CLG_(append_event)(CLG_(dumpmap), "sysTime"); in CLG_()
1682 if (!CLG_(clo).simulate_cache) in cachesim_add_icost()
1686 CLG_(add_and_zero_cost2)( CLG_(sets).full, cost, in cachesim_add_icost()
1701 struct cachesim_if CLG_(cachesim) = {