859            idx, CLG_(bb_base) + current_ii->instr_offset, memline);  in update_LL_use()
876   loaded->iaddr   = CLG_(bb_base) + current_ii->instr_offset;  in update_LL_use()
947            cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
967   loaded->iaddr   = CLG_(bb_base) + current_ii->instr_offset;        \
1068     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I0D()
1071               CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes));  in log_1I0D()
1093     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);  in log_2I0D()
1095     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);  in log_2I0D()
1098               CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),  in log_2I0D()
1099               CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) );  in log_2I0D()
1126     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);  in log_3I0D()
1128     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);  in log_3I0D()
1130     Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);  in log_3I0D()
1133               CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),  in log_3I0D()
1134               CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res),  in log_3I0D()
1135               CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) );  in log_3I0D()
1165     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I1Dr()
1169               CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),  in log_1I1Dr()
1228     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I1Dw()
1232               CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),  in log_1I1Dw()