65 #define add_icache(level, size, assoc, linesize) \  argument
68                 VEX_CACHE_INIT(INSN_CACHE, level, size, linesize, assoc)); \
71 #define add_dcache(level, size, assoc, linesize) \  argument
74                 VEX_CACHE_INIT(DATA_CACHE, level, size, linesize, assoc)); \
77 #define add_ucache(level, size, assoc, linesize) \  argument
80                 VEX_CACHE_INIT(UNIFIED_CACHE, level, size, linesize, assoc)); \
83 #define add_itcache(level, size, assoc) \  argument
86           VEX_CACHE_INIT(INSN_CACHE, level, size, 0, assoc); \
91 #define add_I1(size, assoc, linesize) add_icache(1, size, assoc, linesize)  argument
92 #define add_D1(size, assoc, linesize) add_dcache(1, size, assoc, linesize)  argument
93 #define add_U1(size, assoc, linesize) add_ucache(1, size, assoc, linesize)  argument
94 #define add_I2(size, assoc, linesize) add_icache(2, size, assoc, linesize)  argument
95 #define add_D2(size, assoc, linesize) add_dcache(2, size, assoc, linesize)  argument
96 #define add_U2(size, assoc, linesize) add_ucache(2, size, assoc, linesize)  argument
97 #define add_I3(size, assoc, linesize) add_icache(3, size, assoc, linesize)  argument
98 #define add_D3(size, assoc, linesize) add_dcache(3, size, assoc, linesize)  argument
99 #define add_U3(size, assoc, linesize) add_ucache(3, size, assoc, linesize)  argument
101 #define add_I1T(size, assoc) \  argument
102    add_itcache(1, size, assoc)
295             UInt assoc = ((*(UInt *)&info[4] >> 22) & 0x3ff) + 1;  in Intel_cache_info()  local
300             UInt size = assoc * parts * line_size * sets / 1024;  in Intel_cache_info()
307                case 1: add_D1(size, assoc, line_size); break;  in Intel_cache_info()
308                case 2: add_I1(size, assoc, line_size); break;  in Intel_cache_info()
309                case 3: add_U1(size, assoc, line_size); break;  in Intel_cache_info()
319                case 1: add_D2(size, assoc, line_size); break;  in Intel_cache_info()
320                case 2: add_I2(size, assoc, line_size); break;  in Intel_cache_info()
321                case 3: add_U2(size, assoc, line_size); break;  in Intel_cache_info()
331                case 1: add_D3(size, assoc, line_size); break;  in Intel_cache_info()
332                case 2: add_I3(size, assoc, line_size); break;  in Intel_cache_info()
333                case 3: add_U3(size, assoc, line_size); break;  in Intel_cache_info()
416    UInt size, line_size, assoc;  in AMD_cache_info()  local
452    assoc     = (D1i >> 16) & 0xff;  in AMD_cache_info()
454    ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE, 1, size, line_size, assoc);  in AMD_cache_info()
458    assoc     = (I1i >> 16) & 0xff;  in AMD_cache_info()
460    ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE, 1, size, line_size, assoc);  in AMD_cache_info()
464    assoc     = decode_AMD_cache_L2_L3_assoc((L2i >> 12) & 0xf);  in AMD_cache_info()
466    ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, size, line_size, assoc);  in AMD_cache_info()
475       assoc     = decode_AMD_cache_L2_L3_assoc((L3i >> 12) & 0xf);  in AMD_cache_info()
477       ci->caches[3] = VEX_CACHE_INIT(UNIFIED_CACHE, 3, size, line_size, assoc);  in AMD_cache_info()
597    UInt assoc = get_associativity(level, is_insn_cache);  in get_cache()  local
599    return VEX_CACHE_INIT(kind, level + 1, size, line_size, assoc);  in get_cache()
693       VG_(debugLog)(1, "cache", "        assoc = %u\n", c->assoc);  in write_cache_info()