Lines Matching refs:i32
10 declare <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
11 declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
12 declare <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
13 declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
19 declare <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
20 declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
21 declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
22 declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
27 declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
28 declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
31 declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
32 declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
51 %1 = insertelement <4 x float> undef, float %in, i32 0
52 %2 = insertelement <4 x float> %1, float %in, i32 1
53 %3 = insertelement <4 x float> %2, float %in, i32 2
54 %4 = insertelement <4 x float> %3, float %in, i32 3
58 define internal <4 x i32> @smear_4i(i32 %in) nounwind readnone alwaysinline {
59 %1 = insertelement <4 x i32> undef, i32 %in, i32 0
60 %2 = insertelement <4 x i32> %1, i32 %in, i32 1
61 %3 = insertelement <4 x i32> %2, i32 %in, i32 2
62 %4 = insertelement <4 x i32> %3, i32 %in, i32 3
63 ret <4 x i32> %4
67 %1 = insertelement <4 x i16> undef, i16 %in, i32 0
68 %2 = insertelement <4 x i16> %1, i16 %in, i32 1
69 %3 = insertelement <4 x i16> %2, i16 %in, i32 2
70 %4 = insertelement <4 x i16> %3, i16 %in, i32 3
77 %1 = insertelement <2 x float> undef, float %in, i32 0
78 %2 = insertelement <2 x float> %1, float %in, i32 1
82 define internal <2 x i32> @smear_2i(i32 %in) nounwind readnone alwaysinline {
83 %1 = insertelement <2 x i32> undef, i32 %in, i32 0
84 %2 = insertelement <2 x i32> %1, i32 %in, i32 1
85 ret <2 x i32> %2
89 %1 = insertelement <2 x i16> undef, i16 %in, i32 0
90 %2 = insertelement <2 x i16> %1, i16 %in, i32 1
95 define internal <4 x i32> @smear_4i32(i32 %in) nounwind readnone alwaysinline {
96 %1 = insertelement <4 x i32> undef, i32 %in, i32 0
97 %2 = insertelement <4 x i32> %1, i32 %in, i32 1
98 %3 = insertelement <4 x i32> %2, i32 %in, i32 2
99 %4 = insertelement <4 x i32> %3, i32 %in, i32 3
100 ret <4 x i32> %4
122 …value = shufflevector <3 x float> %value, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
123 %_low = shufflevector <3 x float> %low, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
124 …%_high = shufflevector <3 x float> %high, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
127 %c = shufflevector <4 x float> %b, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
132 …value = shufflevector <3 x float> %value, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
137 %c = shufflevector <4 x float> %b, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
165 define <4 x i32> @_Z5clampDv4_iS_S_(<4 x i32> %value, <4 x i32> %low, <4 x i32> %high) nounwind rea…
166 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %value, <4 x i32> %high) nounwind…
167 …%2 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %1, <4 x i32> %low) nounwind read…
168 ret <4 x i32> %2
171 define <4 x i32> @_Z5clampDv4_iii(<4 x i32> %value, i32 %low, i32 %high) nounwind readonly {
172 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
173 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
174 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %value, <4 x i32> %_high) nounwin…
175 …%2 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %1, <4 x i32> %_low) nounwind rea…
176 ret <4 x i32> %2
179 define <3 x i32> @_Z5clampDv3_iS_S_(<3 x i32> %value, <3 x i32> %low, <3 x i32> %high) nounwind rea…
180 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
181 %_low = shufflevector <3 x i32> %low, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
182 %_high = shufflevector <3 x i32> %high, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
183 …%a = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwi…
184 …%b = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind rea…
185 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
186 ret <3 x i32> %c
189 define <3 x i32> @_Z5clampDv3_iii(<3 x i32> %value, i32 %low, i32 %high) nounwind readonly {
190 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
191 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
192 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
193 …%a = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwi…
194 …%b = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind rea…
195 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
196 ret <3 x i32> %c
199 define <2 x i32> @_Z5clampDv2_iS_S_(<2 x i32> %value, <2 x i32> %low, <2 x i32> %high) nounwind rea…
200 …%1 = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %value, <2 x i32> %high) nounwind…
201 …%2 = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %1, <2 x i32> %low) nounwind read…
202 ret <2 x i32> %2
205 define <2 x i32> @_Z5clampDv2_iii(<2 x i32> %value, i32 %low, i32 %high) nounwind readonly {
206 %_high = tail call <2 x i32> @smear_2i(i32 %high) nounwind readnone
207 %_low = tail call <2 x i32> @smear_2i(i32 %low) nounwind readnone
208 …%a = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %value, <2 x i32> %_high) nounwin…
209 …%b = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %a, <2 x i32> %_low) nounwind rea…
210 ret <2 x i32> %b
215 define <4 x i32> @_Z5clampDv4_jS_S_(<4 x i32> %value, <4 x i32> %low, <4 x i32> %high) nounwind rea…
216 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %value, <4 x i32> %high) nounwind…
217 …%2 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %1, <4 x i32> %low) nounwind read…
218 ret <4 x i32> %2
221 define <4 x i32> @_Z5clampDv4_jjj(<4 x i32> %value, i32 %low, i32 %high) nounwind readonly {
222 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
223 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
224 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %value, <4 x i32> %_high) nounwin…
225 …%2 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %1, <4 x i32> %_low) nounwind rea…
226 ret <4 x i32> %2
229 define <3 x i32> @_Z5clampDv3_jS_S_(<3 x i32> %value, <3 x i32> %low, <3 x i32> %high) nounwind rea…
230 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
231 %_low = shufflevector <3 x i32> %low, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
232 %_high = shufflevector <3 x i32> %high, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
233 …%a = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwi…
234 …%b = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind rea…
235 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
236 ret <3 x i32> %c
239 define <3 x i32> @_Z5clampDv3_jjj(<3 x i32> %value, i32 %low, i32 %high) nounwind readonly {
240 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
241 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
242 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
243 …%a = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwi…
244 …%b = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind rea…
245 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
246 ret <3 x i32> %c
249 define <2 x i32> @_Z5clampDv2_jS_S_(<2 x i32> %value, <2 x i32> %low, <2 x i32> %high) nounwind rea…
250 …%1 = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %value, <2 x i32> %high) nounwind…
251 …%2 = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %1, <2 x i32> %low) nounwind read…
252 ret <2 x i32> %2
255 define <2 x i32> @_Z5clampDv2_jjj(<2 x i32> %value, i32 %low, i32 %high) nounwind readonly {
256 %_high = tail call <2 x i32> @smear_2i(i32 %high) nounwind readnone
257 %_low = tail call <2 x i32> @smear_2i(i32 %low) nounwind readnone
258 …%a = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %value, <2 x i32> %_high) nounwin…
259 …%b = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %a, <2 x i32> %_low) nounwind rea…
260 ret <2 x i32> %b
280 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
281 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
283 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
288 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
291 %c = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
329 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
330 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
332 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
337 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
340 %c = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
373 %1 = sext <2 x i8> %v1 to <2 x i32>
374 %2 = sext <2 x i8> %v2 to <2 x i32>
375 …%3 = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
376 %4 = trunc <2 x i32> %3 to <2 x i8>
380 define <3 x i8> @_Z3maxDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
381 %1 = bitcast i32 %v1 to <4 x i8>
382 %2 = bitcast i32 %v2 to <4 x i8>
383 %3 = sext <4 x i8> %1 to <4 x i32>
384 %4 = sext <4 x i8> %2 to <4 x i32>
385 …%5 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
386 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
387 %7 = trunc <3 x i32> %6 to <3 x i8>
392 %1 = sext <4 x i8> %v1 to <4 x i32>
393 %2 = sext <4 x i8> %v2 to <4 x i32>
394 …%3 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
395 %4 = trunc <4 x i32> %3 to <4 x i8>
406 %1 = sext <2 x i16> %v1 to <2 x i32>
407 %2 = sext <2 x i16> %v2 to <2 x i32>
408 …%3 = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
409 %4 = trunc <2 x i32> %3 to <2 x i16>
414 %1 = sext <3 x i16> %v1 to <3 x i32>
415 %2 = sext <3 x i16> %v2 to <3 x i32>
416 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
417 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
418 …%5 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
419 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
420 %7 = trunc <3 x i32> %6 to <3 x i16>
425 %1 = sext <4 x i16> %v1 to <4 x i32>
426 %2 = sext <4 x i16> %v2 to <4 x i32>
427 …%3 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
428 %4 = trunc <4 x i32> %3 to <4 x i16>
432 define i32 @_Z3maxii(i32 %v1, i32 %v2) nounwind readnone {
433 %1 = icmp sgt i32 %v1, %v2
434 %2 = select i1 %1, i32 %v1, i32 %v2
435 ret i32 %2
438 define <2 x i32> @_Z3maxDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
439 …%1 = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
440 ret <2 x i32> %1
443 define <3 x i32> @_Z3maxDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
444 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
445 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
446 …%3 = tail call <4 x i32 > @llvm.aarch64.neon.smax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind rea…
447 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
448 ret <3 x i32> %4
451 define <4 x i32> @_Z3maxDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
452 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
453 ret <4 x i32> %1
471 %1 = zext <2 x i8> %v1 to <2 x i32>
472 %2 = zext <2 x i8> %v2 to <2 x i32>
473 …%3 = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
474 %4 = trunc <2 x i32> %3 to <2 x i8>
478 define <3 x i8> @_Z3maxDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
479 %1 = bitcast i32 %v1 to <4 x i8>
480 %2 = bitcast i32 %v2 to <4 x i8>
481 %3 = zext <4 x i8> %1 to <4 x i32>
482 %4 = zext <4 x i8> %2 to <4 x i32>
483 …%5 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
484 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
485 %7 = trunc <3 x i32> %6 to <3 x i8>
490 %1 = zext <4 x i8> %v1 to <4 x i32>
491 %2 = zext <4 x i8> %v2 to <4 x i32>
492 …%3 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
493 %4 = trunc <4 x i32> %3 to <4 x i8>
504 %1 = zext <2 x i16> %v1 to <2 x i32>
505 %2 = zext <2 x i16> %v2 to <2 x i32>
506 …%3 = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
507 %4 = trunc <2 x i32> %3 to <2 x i16>
512 %1 = zext <3 x i16> %v1 to <3 x i32>
513 %2 = zext <3 x i16> %v2 to <3 x i32>
514 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
515 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
516 …%5 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
517 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
518 %7 = trunc <3 x i32> %6 to <3 x i16>
523 %1 = zext <4 x i16> %v1 to <4 x i32>
524 %2 = zext <4 x i16> %v2 to <4 x i32>
525 …%3 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
526 %4 = trunc <4 x i32> %3 to <4 x i16>
530 define i32 @_Z3maxjj(i32 %v1, i32 %v2) nounwind readnone {
531 %1 = icmp ugt i32 %v1, %v2
532 %2 = select i1 %1, i32 %v1, i32 %v2
533 ret i32 %2
536 define <2 x i32> @_Z3maxDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
537 …%1 = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
538 ret <2 x i32> %1
541 define <3 x i32> @_Z3maxDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
542 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
543 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
544 …%3 = tail call <4 x i32 > @llvm.aarch64.neon.umax.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind rea…
545 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
546 ret <3 x i32> %4
549 define <4 x i32> @_Z3maxDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
550 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
551 ret <4 x i32> %1
604 %1 = sext <2 x i8> %v1 to <2 x i32>
605 %2 = sext <2 x i8> %v2 to <2 x i32>
606 …%3 = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
607 %4 = trunc <2 x i32> %3 to <2 x i8>
611 define <3 x i8> @_Z3minDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
612 %1 = bitcast i32 %v1 to <4 x i8>
613 %2 = bitcast i32 %v2 to <4 x i8>
614 %3 = sext <4 x i8> %1 to <4 x i32>
615 %4 = sext <4 x i8> %2 to <4 x i32>
616 …%5 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
617 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
618 %7 = trunc <3 x i32> %6 to <3 x i8>
623 %1 = sext <4 x i8> %v1 to <4 x i32>
624 %2 = sext <4 x i8> %v2 to <4 x i32>
625 …%3 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
626 %4 = trunc <4 x i32> %3 to <4 x i8>
637 %1 = sext <2 x i16> %v1 to <2 x i32>
638 %2 = sext <2 x i16> %v2 to <2 x i32>
639 …%3 = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
640 %4 = trunc <2 x i32> %3 to <2 x i16>
645 %1 = sext <3 x i16> %v1 to <3 x i32>
646 %2 = sext <3 x i16> %v2 to <3 x i32>
647 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
648 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
649 …%5 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
650 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
651 %7 = trunc <3 x i32> %6 to <3 x i16>
656 %1 = sext <4 x i16> %v1 to <4 x i32>
657 %2 = sext <4 x i16> %v2 to <4 x i32>
658 …%3 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
659 %4 = trunc <4 x i32> %3 to <4 x i16>
663 define i32 @_Z3minii(i32 %v1, i32 %v2) nounwind readnone {
664 %1 = icmp slt i32 %v1, %v2
665 %2 = select i1 %1, i32 %v1, i32 %v2
666 ret i32 %2
669 define <2 x i32> @_Z3minDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
670 …%1 = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
671 ret <2 x i32> %1
674 define <3 x i32> @_Z3minDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
675 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
676 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
677 …%3 = tail call <4 x i32 > @llvm.aarch64.neon.smin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind rea…
678 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
679 ret <3 x i32> %4
682 define <4 x i32> @_Z3minDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
683 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
684 ret <4 x i32> %1
702 %1 = zext <2 x i8> %v1 to <2 x i32>
703 %2 = zext <2 x i8> %v2 to <2 x i32>
704 …%3 = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
705 %4 = trunc <2 x i32> %3 to <2 x i8>
709 define <3 x i8> @_Z3minDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
710 %1 = bitcast i32 %v1 to <4 x i8>
711 %2 = bitcast i32 %v2 to <4 x i8>
712 %3 = zext <4 x i8> %1 to <4 x i32>
713 %4 = zext <4 x i8> %2 to <4 x i32>
714 …%5 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
715 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
716 %7 = trunc <3 x i32> %6 to <3 x i8>
721 %1 = zext <4 x i8> %v1 to <4 x i32>
722 %2 = zext <4 x i8> %v2 to <4 x i32>
723 …%3 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
724 %4 = trunc <4 x i32> %3 to <4 x i8>
735 %1 = zext <2 x i16> %v1 to <2 x i32>
736 %2 = zext <2 x i16> %v2 to <2 x i32>
737 …%3 = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readno…
738 %4 = trunc <2 x i32> %3 to <2 x i16>
743 %1 = zext <3 x i16> %v1 to <3 x i32>
744 %2 = zext <3 x i16> %v2 to <3 x i32>
745 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
746 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
747 …%5 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readno…
748 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
749 %7 = trunc <3 x i32> %6 to <3 x i16>
754 %1 = zext <4 x i16> %v1 to <4 x i32>
755 %2 = zext <4 x i16> %v2 to <4 x i32>
756 …%3 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
757 %4 = trunc <4 x i32> %3 to <4 x i16>
761 define i32 @_Z3minjj(i32 %v1, i32 %v2) nounwind readnone {
762 %1 = icmp ult i32 %v1, %v2
763 %2 = select i1 %1, i32 %v1, i32 %v2
764 ret i32 %2
767 define <2 x i32> @_Z3minDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
768 …%1 = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
769 ret <2 x i32> %1
772 define <3 x i32> @_Z3minDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
773 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
774 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
775 …%3 = tail call <4 x i32 > @llvm.aarch64.neon.umin.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind rea…
776 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
777 ret <3 x i32> %4
780 define <4 x i32> @_Z3minDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
781 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
782 ret <4 x i32> %1
828 @yuv_U = internal constant <4 x i32> <i32 0, i32 -100, i32 516, i32 0>, align 16
829 @yuv_V = internal constant <4 x i32> <i32 409, i32 -208, i32 0, i32 0>, align 16
830 @yuv_0 = internal constant <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
831 @yuv_255 = internal constant <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, align 16
835 %_sy = zext i8 %pY to i32
836 %_su = zext i8 %pU to i32
837 %_sv = zext i8 %pV to i32
839 %_sy2 = add i32 -16, %_sy
840 %_sy3 = mul i32 298, %_sy2
841 %_su2 = add i32 -128, %_su
842 %_sv2 = add i32 -128, %_sv
843 %_y = tail call <4 x i32> @smear_4i32(i32 %_sy3) nounwind readnone
844 %_u = tail call <4 x i32> @smear_4i32(i32 %_su2) nounwind readnone
845 %_v = tail call <4 x i32> @smear_4i32(i32 %_sv2) nounwind readnone
847 %mu = load <4 x i32>, <4 x i32>* @yuv_U, align 8
848 %mv = load <4 x i32>, <4 x i32>* @yuv_V, align 8
849 %_u2 = mul <4 x i32> %_u, %mu
850 %_v2 = mul <4 x i32> %_v, %mv
851 %_y2 = add <4 x i32> %_y, %_u2
852 %_y3 = add <4 x i32> %_y2, %_v2
854 …call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %_y3, <4 x i32> <i32 8, i32 8, i32 8, i3…
858 %c0 = load <4 x i32>, <4 x i32>* @yuv_0, align 8
859 %c255 = load <4 x i32>, <4 x i32>* @yuv_255, align 8
860 …%r1 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %_y3, <4 x i32> %c0) nounwind re…
861 …%r2 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %r1, <4 x i32> %c255) nounwind r…
862 %r3 = lshr <4 x i32> %r2, <i32 8, i32 8, i32 8, i32 8>
863 %r4 = trunc <4 x i32> %r3 to <4 x i8>
890 %1 = shufflevector <3 x float> %v, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
892 %3 = shufflevector <4 x float> %2, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
902 %1 = insertelement <2 x float> undef, float %v, i32 0
907 %6 = extractelement <2 x float> %5, i32 0
920 %1 = shufflevector <3 x float> %v, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
925 %6 = shufflevector <4 x float> %5, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
946 %1 = insertelement <4 x float> undef, float %in, i32 0
947 %2 = insertelement <4 x float> %1, float %in, i32 1
948 %3 = insertelement <4 x float> %2, float %in, i32 2
949 %4 = insertelement <4 x float> %3, float %in, i32 3
955 %x0 = extractelement <3 x float> %in, i32 0
957 %y0 = extractelement <3 x float> %in, i32 1
959 %z0 = extractelement <3 x float> %in, i32 2
962 %px = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 0
966 %py = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 3
968 ; %ym = call <4 x float> @llvm.aarch64.neon.ld4.v4f32(i8* %py2, i32 4) nounwind
971 %pz = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 5
973 ; %zm2 = call <4 x float> @llvm.aarch64.neon.ld4.v4f32(i8* %pz2, i32 4) nounwind
975 %zm = shufflevector <4 x float> %zm2, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
982 %a6 = shufflevector <4 x float> %a5, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
987 %x0 = extractelement <2 x float> %in, i32 0
989 %y0 = extractelement <2 x float> %in, i32 1
992 %px = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 0
995 %py = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 3
1002 %a4 = shufflevector <4 x float> %a3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
1007 %x0 = extractelement <4 x float> %in, i32 0
1009 %y0 = extractelement <4 x float> %in, i32 1
1011 %z0 = extractelement <4 x float> %in, i32 2
1013 %w0 = extractelement <4 x float> %in, i32 3
1016 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1019 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1022 %pz = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 8
1025 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1040 %x0 = extractelement <3 x float> %in, i32 0
1042 %y0 = extractelement <3 x float> %in, i32 1
1044 %z0 = extractelement <3 x float> %in, i32 2
1047 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1050 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1053 %pz = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 8
1056 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1070 %x0 = extractelement <2 x float> %in, i32 0
1072 %y0 = extractelement <2 x float> %in, i32 1
1075 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1078 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1081 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1119 define <4 x i8> @_Z17rsPackColorTo8888Dv3_f(<4 x i32> %color) nounwind readnone {
1120 %1 = bitcast <4 x i32> %color to <4 x float>
1121 %2 = insertelement <4 x float> %1, float 1.0, i32 3
1128 %1 = insertelement <4 x float> undef, float %r, i32 0
1129 %2 = insertelement <4 x float> %1, float %g, i32 1
1130 %3 = insertelement <4 x float> %2, float %b, i32 2
1131 %4 = insertelement <4 x float> %3, float 1.0, i32 3
1138 %1 = insertelement <4 x float> undef, float %r, i32 0
1139 %2 = insertelement <4 x float> %1, float %g, i32 1
1140 %3 = insertelement <4 x float> %2, float %b, i32 2
1141 %4 = insertelement <4 x float> %3, float %a, i32 3