// Copyright (c) 1994-2006 Sun Microsystems Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistribution in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // - Neither the name of Sun Microsystems or the names of contributors may // be used to endorse or promote products derived from this software without // specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // The original source code covered by the above license above has been // modified significantly by Google Inc. // Copyright 2012 the V8 project authors. All rights reserved. // A lightweight X64 Assembler. #ifndef V8_X64_ASSEMBLER_X64_H_ #define V8_X64_ASSEMBLER_X64_H_ #include #include "src/assembler.h" #include "src/x64/sse-instr.h" namespace v8 { namespace internal { // Utility functions #define GENERAL_REGISTERS(V) \ V(rax) \ V(rcx) \ V(rdx) \ V(rbx) \ V(rsp) \ V(rbp) \ V(rsi) \ V(rdi) \ V(r8) \ V(r9) \ V(r10) \ V(r11) \ V(r12) \ V(r13) \ V(r14) \ V(r15) #define ALLOCATABLE_GENERAL_REGISTERS(V) \ V(rax) \ V(rbx) \ V(rdx) \ V(rcx) \ V(rsi) \ V(rdi) \ V(r8) \ V(r9) \ V(r11) \ V(r12) \ V(r14) \ V(r15) // The length of pushq(rbp), movp(rbp, rsp), Push(rsi) and Push(rdi). static const int kNoCodeAgeSequenceLength = kPointerSize == kInt64Size ? 6 : 17; // CPU Registers. // // 1) We would prefer to use an enum, but enum values are assignment- // compatible with int, which has caused code-generation bugs. // // 2) We would prefer to use a class instead of a struct but we don't like // the register initialization to depend on the particular initialization // order (which appears to be different on OS X, Linux, and Windows for the // installed versions of C++ we tried). Using a struct permits C-style // "initialization". Also, the Register objects cannot be const as this // forces initialization stubs in MSVC, making us dependent on initialization // order. // // 3) By not using an enum, we are possibly preventing the compiler from // doing certain constant folds, which may significantly reduce the // code generated for some assembly instructions (because they boil down // to a few constants). If this is a problem, we could change the code // such that we use an enum in optimized mode, and the struct in debug // mode. This way we get the compile-time error checking in debug mode // and best performance in optimized code. // struct Register { enum Code { #define REGISTER_CODE(R) kCode_##R, GENERAL_REGISTERS(REGISTER_CODE) #undef REGISTER_CODE kAfterLast, kCode_no_reg = -1 }; static const int kNumRegisters = Code::kAfterLast; static Register from_code(int code) { DCHECK(code >= 0); DCHECK(code < kNumRegisters); Register r = {code}; return r; } bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; } bool is(Register reg) const { return reg_code == reg.reg_code; } int code() const { DCHECK(is_valid()); return reg_code; } int bit() const { DCHECK(is_valid()); return 1 << reg_code; } bool is_byte_register() const { return reg_code <= 3; } // Return the high bit of the register code as a 0 or 1. Used often // when constructing the REX prefix byte. int high_bit() const { return reg_code >> 3; } // Return the 3 low bits of the register code. Used when encoding registers // in modR/M, SIB, and opcode bytes. int low_bits() const { return reg_code & 0x7; } // Unfortunately we can't make this private in a struct when initializing // by assignment. int reg_code; }; #define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R}; GENERAL_REGISTERS(DECLARE_REGISTER) #undef DECLARE_REGISTER const Register no_reg = {Register::kCode_no_reg}; #ifdef _WIN64 // Windows calling convention const Register arg_reg_1 = {Register::kCode_rcx}; const Register arg_reg_2 = {Register::kCode_rdx}; const Register arg_reg_3 = {Register::kCode_r8}; const Register arg_reg_4 = {Register::kCode_r9}; #else // AMD64 calling convention const Register arg_reg_1 = {Register::kCode_rdi}; const Register arg_reg_2 = {Register::kCode_rsi}; const Register arg_reg_3 = {Register::kCode_rdx}; const Register arg_reg_4 = {Register::kCode_rcx}; #endif // _WIN64 #define DOUBLE_REGISTERS(V) \ V(xmm0) \ V(xmm1) \ V(xmm2) \ V(xmm3) \ V(xmm4) \ V(xmm5) \ V(xmm6) \ V(xmm7) \ V(xmm8) \ V(xmm9) \ V(xmm10) \ V(xmm11) \ V(xmm12) \ V(xmm13) \ V(xmm14) \ V(xmm15) #define FLOAT_REGISTERS DOUBLE_REGISTERS #define SIMD128_REGISTERS DOUBLE_REGISTERS #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ V(xmm0) \ V(xmm1) \ V(xmm2) \ V(xmm3) \ V(xmm4) \ V(xmm5) \ V(xmm6) \ V(xmm7) \ V(xmm8) \ V(xmm9) \ V(xmm10) \ V(xmm11) \ V(xmm12) \ V(xmm13) \ V(xmm14) static const bool kSimpleFPAliasing = true; static const bool kSimdMaskRegisters = false; struct XMMRegister { enum Code { #define REGISTER_CODE(R) kCode_##R, DOUBLE_REGISTERS(REGISTER_CODE) #undef REGISTER_CODE kAfterLast, kCode_no_reg = -1 }; static const int kMaxNumRegisters = Code::kAfterLast; static XMMRegister from_code(int code) { XMMRegister result = {code}; return result; } bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } bool is(XMMRegister reg) const { return reg_code == reg.reg_code; } int code() const { DCHECK(is_valid()); return reg_code; } // Return the high bit of the register code as a 0 or 1. Used often // when constructing the REX prefix byte. int high_bit() const { return reg_code >> 3; } // Return the 3 low bits of the register code. Used when encoding registers // in modR/M, SIB, and opcode bytes. int low_bits() const { return reg_code & 0x7; } // Unfortunately we can't make this private in a struct when initializing // by assignment. int reg_code; }; typedef XMMRegister FloatRegister; typedef XMMRegister DoubleRegister; typedef XMMRegister Simd128Register; #define DECLARE_REGISTER(R) \ const DoubleRegister R = {DoubleRegister::kCode_##R}; DOUBLE_REGISTERS(DECLARE_REGISTER) #undef DECLARE_REGISTER const DoubleRegister no_double_reg = {DoubleRegister::kCode_no_reg}; enum Condition { // any value < 0 is considered no_condition no_condition = -1, overflow = 0, no_overflow = 1, below = 2, above_equal = 3, equal = 4, not_equal = 5, below_equal = 6, above = 7, negative = 8, positive = 9, parity_even = 10, parity_odd = 11, less = 12, greater_equal = 13, less_equal = 14, greater = 15, // Fake conditions that are handled by the // opcodes using them. always = 16, never = 17, // aliases carry = below, not_carry = above_equal, zero = equal, not_zero = not_equal, sign = negative, not_sign = positive, last_condition = greater }; // Returns the equivalent of !cc. // Negation of the default no_condition (-1) results in a non-default // no_condition value (-2). As long as tests for no_condition check // for condition < 0, this will work as expected. inline Condition NegateCondition(Condition cc) { return static_cast(cc ^ 1); } // Commute a condition such that {a cond b == b cond' a}. inline Condition CommuteCondition(Condition cc) { switch (cc) { case below: return above; case above: return below; case above_equal: return below_equal; case below_equal: return above_equal; case less: return greater; case greater: return less; case greater_equal: return less_equal; case less_equal: return greater_equal; default: return cc; } } enum RoundingMode { kRoundToNearest = 0x0, kRoundDown = 0x1, kRoundUp = 0x2, kRoundToZero = 0x3 }; // ----------------------------------------------------------------------------- // Machine instruction Immediates class Immediate BASE_EMBEDDED { public: explicit Immediate(int32_t value) : value_(value) {} explicit Immediate(int32_t value, RelocInfo::Mode rmode) : value_(value), rmode_(rmode) {} explicit Immediate(Smi* value) { DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI. value_ = static_cast(reinterpret_cast(value)); } private: int32_t value_; RelocInfo::Mode rmode_ = RelocInfo::NONE32; friend class Assembler; }; // ----------------------------------------------------------------------------- // Machine instruction Operands enum ScaleFactor { times_1 = 0, times_2 = 1, times_4 = 2, times_8 = 3, times_int_size = times_4, times_pointer_size = (kPointerSize == 8) ? times_8 : times_4 }; class Operand BASE_EMBEDDED { public: // [base + disp/r] Operand(Register base, int32_t disp); // [base + index*scale + disp/r] Operand(Register base, Register index, ScaleFactor scale, int32_t disp); // [index*scale + disp/r] Operand(Register index, ScaleFactor scale, int32_t disp); // Offset from existing memory operand. // Offset is added to existing displacement as 32-bit signed values and // this must not overflow. Operand(const Operand& base, int32_t offset); // [rip + disp/r] explicit Operand(Label* label); // Checks whether either base or index register is the given register. // Does not check the "reg" part of the Operand. bool AddressUsesRegister(Register reg) const; // Queries related to the size of the generated instruction. // Whether the generated instruction will have a REX prefix. bool requires_rex() const { return rex_ != 0; } // Size of the ModR/M, SIB and displacement parts of the generated // instruction. int operand_size() const { return len_; } private: byte rex_; byte buf_[9]; // The number of bytes of buf_ in use. byte len_; // Set the ModR/M byte without an encoded 'reg' register. The // register is encoded later as part of the emit_operand operation. // set_modrm can be called before or after set_sib and set_disp*. inline void set_modrm(int mod, Register rm); // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. inline void set_sib(ScaleFactor scale, Register index, Register base); // Adds operand displacement fields (offsets added to the memory address). // Needs to be called after set_sib, not before it. inline void set_disp8(int disp); inline void set_disp32(int disp); inline void set_disp64(int64_t disp); // for labels. friend class Assembler; }; #define ASSEMBLER_INSTRUCTION_LIST(V) \ V(add) \ V(and) \ V(cmp) \ V(cmpxchg) \ V(dec) \ V(idiv) \ V(div) \ V(imul) \ V(inc) \ V(lea) \ V(mov) \ V(movzxb) \ V(movzxw) \ V(neg) \ V(not) \ V(or) \ V(repmovs) \ V(sbb) \ V(sub) \ V(test) \ V(xchg) \ V(xor) // Shift instructions on operands/registers with kPointerSize, kInt32Size and // kInt64Size. #define SHIFT_INSTRUCTION_LIST(V) \ V(rol, 0x0) \ V(ror, 0x1) \ V(rcl, 0x2) \ V(rcr, 0x3) \ V(shl, 0x4) \ V(shr, 0x5) \ V(sar, 0x7) \ class Assembler : public AssemblerBase { private: // We check before assembling an instruction that there is sufficient // space to write an instruction and its relocation information. // The relocation writer's position must be kGap bytes above the end of // the generated instructions. This leaves enough space for the // longest possible x64 instruction, 15 bytes, and the longest possible // relocation information encoding, RelocInfoWriter::kMaxLength == 16. // (There is a 15 byte limit on x64 instruction length that rules out some // otherwise valid instructions.) // This allows for a single, fast space check per instruction. static const int kGap = 32; public: // Create an assembler. Instructions and relocation information are emitted // into a buffer, with the instructions starting from the beginning and the // relocation information starting from the end of the buffer. See CodeDesc // for a detailed comment on the layout (globals.h). // // If the provided buffer is NULL, the assembler allocates and grows its own // buffer, and buffer_size determines the initial buffer size. The buffer is // owned by the assembler and deallocated upon destruction of the assembler. // // If the provided buffer is not NULL, the assembler uses the provided buffer // for code generation and assumes its size to be buffer_size. If the buffer // is too small, a fatal error occurs. No deallocation of the buffer is done // upon destruction of the assembler. Assembler(Isolate* isolate, void* buffer, int buffer_size); virtual ~Assembler() { } // GetCode emits any pending (non-emitted) code and fills the descriptor // desc. GetCode() is idempotent; it returns the same result if no other // Assembler functions are invoked in between GetCode() calls. void GetCode(CodeDesc* desc); // Read/Modify the code target in the relative branch/call instruction at pc. // On the x64 architecture, we use relative jumps with a 32-bit displacement // to jump to other Code objects in the Code space in the heap. // Jumps to C functions are done indirectly through a 64-bit register holding // the absolute address of the target. // These functions convert between absolute Addresses of Code objects and // the relative displacements stored in the code. static inline Address target_address_at(Address pc, Address constant_pool); static inline void set_target_address_at( Isolate* isolate, Address pc, Address constant_pool, Address target, ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); static inline Address target_address_at(Address pc, Code* code); static inline void set_target_address_at( Isolate* isolate, Address pc, Code* code, Address target, ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); // Return the code target address at a call site from the return address // of that call in the instruction stream. static inline Address target_address_from_return_address(Address pc); // This sets the branch destination (which is in the instruction on x64). // This is for calls and branches within generated code. inline static void deserialization_set_special_target_at( Isolate* isolate, Address instruction_payload, Code* code, Address target); // This sets the internal reference at the pc. inline static void deserialization_set_target_internal_reference_at( Isolate* isolate, Address pc, Address target, RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); static inline RelocInfo::Mode RelocInfoNone() { if (kPointerSize == kInt64Size) { return RelocInfo::NONE64; } else { DCHECK(kPointerSize == kInt32Size); return RelocInfo::NONE32; } } inline Handle