1 //===-- MipsOptionRecord.h - Abstraction for storing information ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // MipsOptionRecord - Abstraction for storing arbitrary information in 11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips 12 // specific ELF sections like .Mips.options. Specific records should subclass 13 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which 14 // basically just dumps the information into an ELF section. More information 15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object 16 // specification. 17 // 18 //===----------------------------------------------------------------------===// 19 20 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H 21 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H 22 23 #include "MCTargetDesc/MipsMCTargetDesc.h" 24 #include "llvm/MC/MCContext.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 27 namespace llvm { 28 class MipsELFStreamer; 29 class MCSubtargetInfo; 30 31 class MipsOptionRecord { 32 public: ~MipsOptionRecord()33 virtual ~MipsOptionRecord(){}; 34 virtual void EmitMipsOptionRecord() = 0; 35 }; 36 37 class MipsRegInfoRecord : public MipsOptionRecord { 38 public: MipsRegInfoRecord(MipsELFStreamer * S,MCContext & Context)39 MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context) 40 : Streamer(S), Context(Context) { 41 ri_gprmask = 0; 42 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0; 43 ri_gp_value = 0; 44 45 const MCRegisterInfo *TRI = Context.getRegisterInfo(); 46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); 47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); 48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); 49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); 50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); 51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); 52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); 53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); 54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); 55 } ~MipsRegInfoRecord()56 ~MipsRegInfoRecord() override {} 57 58 void EmitMipsOptionRecord() override; 59 void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo); 60 61 private: 62 MipsELFStreamer *Streamer; 63 MCContext &Context; 64 const MCRegisterClass *GPR32RegClass; 65 const MCRegisterClass *GPR64RegClass; 66 const MCRegisterClass *FGR32RegClass; 67 const MCRegisterClass *FGR64RegClass; 68 const MCRegisterClass *AFGR64RegClass; 69 const MCRegisterClass *MSA128BRegClass; 70 const MCRegisterClass *COP0RegClass; 71 const MCRegisterClass *COP2RegClass; 72 const MCRegisterClass *COP3RegClass; 73 uint32_t ri_gprmask; 74 uint32_t ri_cprmask[4]; 75 int64_t ri_gp_value; 76 }; 77 } // namespace llvm 78 #endif 79