1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 23277 bytes, from 2016-12-24 05:01:47)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2016-12-26 17:51:07)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 100594 bytes, from 2017-01-20 23:03:30)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
20
21 Copyright (C) 2013-2016 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum vgt_event_type {
48 VS_DEALLOC = 0,
49 PS_DEALLOC = 1,
50 VS_DONE_TS = 2,
51 PS_DONE_TS = 3,
52 CACHE_FLUSH_TS = 4,
53 CONTEXT_DONE = 5,
54 CACHE_FLUSH = 6,
55 HLSQ_FLUSH = 7,
56 VIZQUERY_START = 7,
57 VIZQUERY_END = 8,
58 SC_WAIT_WC = 9,
59 RST_PIX_CNT = 13,
60 RST_VTX_CNT = 14,
61 TILE_FLUSH = 15,
62 STAT_EVENT = 16,
63 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
64 ZPASS_DONE = 21,
65 CACHE_FLUSH_AND_INV_EVENT = 22,
66 PERFCOUNTER_START = 23,
67 PERFCOUNTER_STOP = 24,
68 VS_FETCH_DONE = 27,
69 FACENESS_FLUSH = 28,
70 FLUSH_SO_0 = 17,
71 FLUSH_SO_1 = 18,
72 FLUSH_SO_2 = 19,
73 FLUSH_SO_3 = 20,
74 UNK_19 = 25,
75 UNK_1C = 28,
76 UNK_1D = 29,
77 BLIT = 30,
78 UNK_25 = 37,
79 UNK_26 = 38,
80 UNK_2C = 44,
81 UNK_2D = 45,
82 };
83
84 enum pc_di_primtype {
85 DI_PT_NONE = 0,
86 DI_PT_POINTLIST_PSIZE = 1,
87 DI_PT_LINELIST = 2,
88 DI_PT_LINESTRIP = 3,
89 DI_PT_TRILIST = 4,
90 DI_PT_TRIFAN = 5,
91 DI_PT_TRISTRIP = 6,
92 DI_PT_LINELOOP = 7,
93 DI_PT_RECTLIST = 8,
94 DI_PT_POINTLIST = 9,
95 DI_PT_LINE_ADJ = 10,
96 DI_PT_LINESTRIP_ADJ = 11,
97 DI_PT_TRI_ADJ = 12,
98 DI_PT_TRISTRIP_ADJ = 13,
99 };
100
101 enum pc_di_src_sel {
102 DI_SRC_SEL_DMA = 0,
103 DI_SRC_SEL_IMMEDIATE = 1,
104 DI_SRC_SEL_AUTO_INDEX = 2,
105 DI_SRC_SEL_RESERVED = 3,
106 };
107
108 enum pc_di_index_size {
109 INDEX_SIZE_IGN = 0,
110 INDEX_SIZE_16_BIT = 0,
111 INDEX_SIZE_32_BIT = 1,
112 INDEX_SIZE_8_BIT = 2,
113 INDEX_SIZE_INVALID = 0,
114 };
115
116 enum pc_di_vis_cull_mode {
117 IGNORE_VISIBILITY = 0,
118 USE_VISIBILITY = 1,
119 };
120
121 enum adreno_pm4_packet_type {
122 CP_TYPE0_PKT = 0,
123 CP_TYPE1_PKT = 0x40000000,
124 CP_TYPE2_PKT = 0x80000000,
125 CP_TYPE3_PKT = 0xc0000000,
126 CP_TYPE4_PKT = 0x40000000,
127 CP_TYPE7_PKT = 0x70000000,
128 };
129
130 enum adreno_pm4_type3_packets {
131 CP_ME_INIT = 72,
132 CP_NOP = 16,
133 CP_PREEMPT_ENABLE = 28,
134 CP_PREEMPT_TOKEN = 30,
135 CP_INDIRECT_BUFFER = 63,
136 CP_INDIRECT_BUFFER_PFD = 55,
137 CP_WAIT_FOR_IDLE = 38,
138 CP_WAIT_REG_MEM = 60,
139 CP_WAIT_REG_EQ = 82,
140 CP_WAIT_REG_GTE = 83,
141 CP_WAIT_UNTIL_READ = 92,
142 CP_WAIT_IB_PFD_COMPLETE = 93,
143 CP_REG_RMW = 33,
144 CP_SET_BIN_DATA = 47,
145 CP_REG_TO_MEM = 62,
146 CP_MEM_WRITE = 61,
147 CP_MEM_WRITE_CNTR = 79,
148 CP_COND_EXEC = 68,
149 CP_COND_WRITE = 69,
150 CP_EVENT_WRITE = 70,
151 CP_EVENT_WRITE_SHD = 88,
152 CP_EVENT_WRITE_CFL = 89,
153 CP_EVENT_WRITE_ZPD = 91,
154 CP_RUN_OPENCL = 49,
155 CP_DRAW_INDX = 34,
156 CP_DRAW_INDX_2 = 54,
157 CP_DRAW_INDX_BIN = 52,
158 CP_DRAW_INDX_2_BIN = 53,
159 CP_VIZ_QUERY = 35,
160 CP_SET_STATE = 37,
161 CP_SET_CONSTANT = 45,
162 CP_IM_LOAD = 39,
163 CP_IM_LOAD_IMMEDIATE = 43,
164 CP_LOAD_CONSTANT_CONTEXT = 46,
165 CP_INVALIDATE_STATE = 59,
166 CP_SET_SHADER_BASES = 74,
167 CP_SET_BIN_MASK = 80,
168 CP_SET_BIN_SELECT = 81,
169 CP_CONTEXT_UPDATE = 94,
170 CP_INTERRUPT = 64,
171 CP_IM_STORE = 44,
172 CP_SET_DRAW_INIT_FLAGS = 75,
173 CP_SET_PROTECTED_MODE = 95,
174 CP_BOOTSTRAP_UCODE = 111,
175 CP_LOAD_STATE = 48,
176 CP_COND_INDIRECT_BUFFER_PFE = 58,
177 CP_COND_INDIRECT_BUFFER_PFD = 50,
178 CP_INDIRECT_BUFFER_PFE = 63,
179 CP_SET_BIN = 76,
180 CP_TEST_TWO_MEMS = 113,
181 CP_REG_WR_NO_CTXT = 120,
182 CP_RECORD_PFP_TIMESTAMP = 17,
183 CP_SET_SECURE_MODE = 102,
184 CP_WAIT_FOR_ME = 19,
185 CP_SET_DRAW_STATE = 67,
186 CP_DRAW_INDX_OFFSET = 56,
187 CP_DRAW_INDIRECT = 40,
188 CP_DRAW_INDX_INDIRECT = 41,
189 CP_DRAW_AUTO = 36,
190 CP_UNKNOWN_19 = 25,
191 CP_UNKNOWN_1A = 26,
192 CP_UNKNOWN_4E = 78,
193 CP_WIDE_REG_WRITE = 116,
194 CP_SCRATCH_TO_REG = 77,
195 CP_REG_TO_SCRATCH = 74,
196 CP_WAIT_MEM_WRITES = 18,
197 CP_COND_REG_EXEC = 71,
198 CP_MEM_TO_REG = 66,
199 CP_EXEC_CS = 51,
200 CP_PERFCOUNTER_ACTION = 80,
201 CP_SMMU_TABLE_UPDATE = 83,
202 CP_CONTEXT_REG_BUNCH = 92,
203 CP_YIELD_ENABLE = 28,
204 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
205 CP_SKIP_IB2_ENABLE_LOCAL = 35,
206 CP_SET_SUBDRAW_SIZE = 53,
207 CP_SET_VISIBILITY_OVERRIDE = 100,
208 CP_PREEMPT_ENABLE_GLOBAL = 105,
209 CP_PREEMPT_ENABLE_LOCAL = 106,
210 CP_CONTEXT_SWITCH_YIELD = 107,
211 CP_SET_RENDER_MODE = 108,
212 CP_COMPUTE_CHECKPOINT = 110,
213 CP_MEM_TO_MEM = 115,
214 CP_BLIT = 44,
215 CP_UNK_39 = 57,
216 IN_IB_PREFETCH_END = 23,
217 IN_SUBBLK_PREFETCH = 31,
218 IN_INSTR_PREFETCH = 32,
219 IN_INSTR_MATCH = 71,
220 IN_CONST_PREFETCH = 73,
221 IN_INCR_UPDT_STATE = 85,
222 IN_INCR_UPDT_CONST = 86,
223 IN_INCR_UPDT_INSTR = 87,
224 };
225
226 enum adreno_state_block {
227 SB_VERT_TEX = 0,
228 SB_VERT_MIPADDR = 1,
229 SB_FRAG_TEX = 2,
230 SB_FRAG_MIPADDR = 3,
231 SB_VERT_SHADER = 4,
232 SB_GEOM_SHADER = 5,
233 SB_FRAG_SHADER = 6,
234 SB_COMPUTE_SHADER = 7,
235 };
236
237 enum adreno_state_type {
238 ST_SHADER = 0,
239 ST_CONSTANTS = 1,
240 };
241
242 enum adreno_state_src {
243 SS_DIRECT = 0,
244 SS_INVALID_ALL_IC = 2,
245 SS_INVALID_PART_IC = 3,
246 SS_INDIRECT = 4,
247 SS_INDIRECT_TCM = 5,
248 SS_INDIRECT_STM = 6,
249 };
250
251 enum a4xx_index_size {
252 INDEX4_SIZE_8_BIT = 0,
253 INDEX4_SIZE_16_BIT = 1,
254 INDEX4_SIZE_32_BIT = 2,
255 };
256
257 enum render_mode_cmd {
258 BYPASS = 1,
259 BINNING = 2,
260 GMEM = 3,
261 BLIT2D = 5,
262 };
263
264 enum cp_blit_cmd {
265 BLIT_OP_FILL = 0,
266 BLIT_OP_COPY = 1,
267 };
268
269 #define REG_CP_LOAD_STATE_0 0x00000000
270 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
271 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)272 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
273 {
274 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
275 }
276 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
277 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)278 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
279 {
280 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
281 }
282 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
283 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)284 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
285 {
286 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
287 }
288 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
289 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)290 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
291 {
292 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
293 }
294
295 #define REG_CP_LOAD_STATE_1 0x00000001
296 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
297 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)298 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
299 {
300 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
301 }
302 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
303 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)304 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
305 {
306 assert(!(val & 0x3));
307 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
308 }
309
310 #define REG_CP_LOAD_STATE_2 0x00000002
311 #define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
312 #define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)313 static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
314 {
315 return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
316 }
317
318 #define REG_CP_DRAW_INDX_0 0x00000000
319 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
320 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)321 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
322 {
323 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
324 }
325
326 #define REG_CP_DRAW_INDX_1 0x00000001
327 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
328 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)329 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
330 {
331 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
332 }
333 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
334 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)335 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
336 {
337 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
338 }
339 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
340 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)341 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
342 {
343 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
344 }
345 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
346 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)347 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
348 {
349 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
350 }
351 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
352 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
353 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
354 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
355 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)356 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
357 {
358 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
359 }
360
361 #define REG_CP_DRAW_INDX_2 0x00000002
362 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
363 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)364 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
365 {
366 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
367 }
368
369 #define REG_CP_DRAW_INDX_3 0x00000003
370 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
371 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
CP_DRAW_INDX_3_INDX_BASE(uint32_t val)372 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
373 {
374 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
375 }
376
377 #define REG_CP_DRAW_INDX_4 0x00000004
378 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
379 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)380 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
381 {
382 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
383 }
384
385 #define REG_CP_DRAW_INDX_2_0 0x00000000
386 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
387 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)388 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
389 {
390 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
391 }
392
393 #define REG_CP_DRAW_INDX_2_1 0x00000001
394 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
395 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)396 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
397 {
398 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
399 }
400 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
401 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)402 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
403 {
404 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
405 }
406 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
407 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)408 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
409 {
410 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
411 }
412 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
413 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)414 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
415 {
416 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
417 }
418 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
419 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
420 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
421 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
422 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)423 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
424 {
425 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
426 }
427
428 #define REG_CP_DRAW_INDX_2_2 0x00000002
429 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
430 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)431 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
432 {
433 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
434 }
435
436 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
437 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
438 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)439 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
440 {
441 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
442 }
443 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
444 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)445 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
446 {
447 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
448 }
449 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
450 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)451 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
452 {
453 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
454 }
455 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
456 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)457 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
458 {
459 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
460 }
461 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
462 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)463 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
464 {
465 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
466 }
467
468 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
469 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
470 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)471 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
472 {
473 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
474 }
475
476 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
477 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
478 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)479 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
480 {
481 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
482 }
483
484 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
485
486 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
487 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
488 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)489 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
490 {
491 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
492 }
493
494 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
495 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
496 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)497 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
498 {
499 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
500 }
501
REG_CP_SET_DRAW_STATE_(uint32_t i0)502 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
503
REG_CP_SET_DRAW_STATE__0(uint32_t i0)504 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
505 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
506 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
CP_SET_DRAW_STATE__0_COUNT(uint32_t val)507 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
508 {
509 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
510 }
511 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
512 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
513 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
514 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
515 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
516 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)517 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
518 {
519 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
520 }
521
REG_CP_SET_DRAW_STATE__1(uint32_t i0)522 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
523 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
524 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)525 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
526 {
527 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
528 }
529
REG_CP_SET_DRAW_STATE__2(uint32_t i0)530 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
531 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
532 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)533 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
534 {
535 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
536 }
537
538 #define REG_CP_SET_BIN_0 0x00000000
539
540 #define REG_CP_SET_BIN_1 0x00000001
541 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
542 #define CP_SET_BIN_1_X1__SHIFT 0
CP_SET_BIN_1_X1(uint32_t val)543 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
544 {
545 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
546 }
547 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
548 #define CP_SET_BIN_1_Y1__SHIFT 16
CP_SET_BIN_1_Y1(uint32_t val)549 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
550 {
551 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
552 }
553
554 #define REG_CP_SET_BIN_2 0x00000002
555 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
556 #define CP_SET_BIN_2_X2__SHIFT 0
CP_SET_BIN_2_X2(uint32_t val)557 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
558 {
559 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
560 }
561 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
562 #define CP_SET_BIN_2_Y2__SHIFT 16
CP_SET_BIN_2_Y2(uint32_t val)563 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
564 {
565 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
566 }
567
568 #define REG_CP_SET_BIN_DATA_0 0x00000000
569 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
570 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)571 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
572 {
573 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
574 }
575
576 #define REG_CP_SET_BIN_DATA_1 0x00000001
577 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
578 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)579 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
580 {
581 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
582 }
583
584 #define REG_CP_REG_TO_MEM_0 0x00000000
585 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
586 #define CP_REG_TO_MEM_0_REG__SHIFT 0
CP_REG_TO_MEM_0_REG(uint32_t val)587 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
588 {
589 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
590 }
591 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
592 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
CP_REG_TO_MEM_0_CNT(uint32_t val)593 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
594 {
595 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
596 }
597 #define CP_REG_TO_MEM_0_64B 0x40000000
598 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
599
600 #define REG_CP_REG_TO_MEM_1 0x00000001
601 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
602 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
CP_REG_TO_MEM_1_DEST(uint32_t val)603 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
604 {
605 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
606 }
607
608 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
609
610 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
611 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
612 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
CP_DISPATCH_COMPUTE_1_X(uint32_t val)613 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
614 {
615 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
616 }
617
618 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
619 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
620 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
CP_DISPATCH_COMPUTE_2_Y(uint32_t val)621 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
622 {
623 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
624 }
625
626 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
627 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
628 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
CP_DISPATCH_COMPUTE_3_Z(uint32_t val)629 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
630 {
631 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
632 }
633
634 #define REG_CP_SET_RENDER_MODE_0 0x00000000
635 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
636 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)637 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
638 {
639 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
640 }
641
642 #define REG_CP_SET_RENDER_MODE_1 0x00000001
643 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
644 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)645 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
646 {
647 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
648 }
649
650 #define REG_CP_SET_RENDER_MODE_2 0x00000002
651 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
652 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)653 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
654 {
655 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
656 }
657
658 #define REG_CP_SET_RENDER_MODE_3 0x00000003
659 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
660
661 #define REG_CP_SET_RENDER_MODE_4 0x00000004
662
663 #define REG_CP_SET_RENDER_MODE_5 0x00000005
664 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
665 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)666 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
667 {
668 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
669 }
670
671 #define REG_CP_SET_RENDER_MODE_6 0x00000006
672 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
673 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)674 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
675 {
676 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
677 }
678
679 #define REG_CP_SET_RENDER_MODE_7 0x00000007
680 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
681 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)682 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
683 {
684 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
685 }
686
687 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
688
689 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
690 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
691 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)692 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
693 {
694 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
695 }
696
697 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
698 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
699 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)700 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
701 {
702 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
703 }
704
705 #define REG_CP_EVENT_WRITE_0 0x00000000
706 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
707 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)708 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
709 {
710 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
711 }
712
713 #define REG_CP_EVENT_WRITE_1 0x00000001
714 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
715 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)716 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
717 {
718 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
719 }
720
721 #define REG_CP_EVENT_WRITE_2 0x00000002
722 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
723 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)724 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
725 {
726 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
727 }
728
729 #define REG_CP_EVENT_WRITE_3 0x00000003
730
731 #define REG_CP_BLIT_0 0x00000000
732 #define CP_BLIT_0_OP__MASK 0x0000000f
733 #define CP_BLIT_0_OP__SHIFT 0
CP_BLIT_0_OP(enum cp_blit_cmd val)734 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
735 {
736 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
737 }
738
739 #define REG_CP_BLIT_1 0x00000001
740 #define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
741 #define CP_BLIT_1_SRC_X1__SHIFT 0
CP_BLIT_1_SRC_X1(uint32_t val)742 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
743 {
744 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
745 }
746 #define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
747 #define CP_BLIT_1_SRC_Y1__SHIFT 16
CP_BLIT_1_SRC_Y1(uint32_t val)748 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
749 {
750 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
751 }
752
753 #define REG_CP_BLIT_2 0x00000002
754 #define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
755 #define CP_BLIT_2_SRC_X2__SHIFT 0
CP_BLIT_2_SRC_X2(uint32_t val)756 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
757 {
758 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
759 }
760 #define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
761 #define CP_BLIT_2_SRC_Y2__SHIFT 16
CP_BLIT_2_SRC_Y2(uint32_t val)762 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
763 {
764 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
765 }
766
767 #define REG_CP_BLIT_3 0x00000003
768 #define CP_BLIT_3_DST_X1__MASK 0x0000ffff
769 #define CP_BLIT_3_DST_X1__SHIFT 0
CP_BLIT_3_DST_X1(uint32_t val)770 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
771 {
772 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
773 }
774 #define CP_BLIT_3_DST_Y1__MASK 0xffff0000
775 #define CP_BLIT_3_DST_Y1__SHIFT 16
CP_BLIT_3_DST_Y1(uint32_t val)776 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
777 {
778 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
779 }
780
781 #define REG_CP_BLIT_4 0x00000004
782 #define CP_BLIT_4_DST_X2__MASK 0x0000ffff
783 #define CP_BLIT_4_DST_X2__SHIFT 0
CP_BLIT_4_DST_X2(uint32_t val)784 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
785 {
786 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
787 }
788 #define CP_BLIT_4_DST_Y2__MASK 0xffff0000
789 #define CP_BLIT_4_DST_Y2__SHIFT 16
CP_BLIT_4_DST_Y2(uint32_t val)790 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
791 {
792 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
793 }
794
795
796 #endif /* ADRENO_PM4_XML */
797