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1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "processimplicitdefs"
11 
12 #include "llvm/CodeGen/ProcessImplicitDefs.h"
13 
14 #include "llvm/ADT/DepthFirstIterator.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 
25 
26 using namespace llvm;
27 
28 char ProcessImplicitDefs::ID = 0;
29 INITIALIZE_PASS_BEGIN(ProcessImplicitDefs, "processimpdefs",
30                 "Process Implicit Definitions", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveVariables)31 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
32 INITIALIZE_PASS_END(ProcessImplicitDefs, "processimpdefs",
33                 "Process Implicit Definitions", false, false)
34 
35 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
36   AU.setPreservesCFG();
37   AU.addPreserved<AliasAnalysis>();
38   AU.addPreserved<LiveVariables>();
39   AU.addRequired<LiveVariables>();
40   AU.addPreservedID(MachineLoopInfoID);
41   AU.addPreservedID(MachineDominatorsID);
42   AU.addPreservedID(TwoAddressInstructionPassID);
43   AU.addPreservedID(PHIEliminationID);
44   MachineFunctionPass::getAnalysisUsage(AU);
45 }
46 
47 bool
CanTurnIntoImplicitDef(MachineInstr * MI,unsigned Reg,unsigned OpIdx,SmallSet<unsigned,8> & ImpDefRegs)48 ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
49                                             unsigned Reg, unsigned OpIdx,
50                                             SmallSet<unsigned, 8> &ImpDefRegs) {
51   switch(OpIdx) {
52   case 1:
53     return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
54                             ImpDefRegs.count(MI->getOperand(0).getReg()));
55   case 2:
56     return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
57                                   ImpDefRegs.count(MI->getOperand(0).getReg()));
58   default: return false;
59   }
60 }
61 
isUndefCopy(MachineInstr * MI,unsigned Reg,SmallSet<unsigned,8> & ImpDefRegs)62 static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
63                         SmallSet<unsigned, 8> &ImpDefRegs) {
64   if (MI->isCopy()) {
65     MachineOperand &MO0 = MI->getOperand(0);
66     MachineOperand &MO1 = MI->getOperand(1);
67     if (MO1.getReg() != Reg)
68       return false;
69     if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
70       return true;
71     return false;
72   }
73   return false;
74 }
75 
76 /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
77 /// there is one implicit_def for each use. Add isUndef marker to
78 /// implicit_def defs and their uses.
runOnMachineFunction(MachineFunction & fn)79 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
80 
81   DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
82                << "********** Function: "
83                << ((Value*)fn.getFunction())->getName() << '\n');
84 
85   bool Changed = false;
86 
87   TII = fn.getTarget().getInstrInfo();
88   TRI = fn.getTarget().getRegisterInfo();
89   MRI = &fn.getRegInfo();
90   LV = &getAnalysis<LiveVariables>();
91 
92   SmallSet<unsigned, 8> ImpDefRegs;
93   SmallVector<MachineInstr*, 8> ImpDefMIs;
94   SmallVector<MachineInstr*, 4> RUses;
95   SmallPtrSet<MachineBasicBlock*,16> Visited;
96   SmallPtrSet<MachineInstr*, 8> ModInsts;
97 
98   MachineBasicBlock *Entry = fn.begin();
99   for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
100          DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
101        DFI != E; ++DFI) {
102     MachineBasicBlock *MBB = *DFI;
103     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
104          I != E; ) {
105       MachineInstr *MI = &*I;
106       ++I;
107       if (MI->isImplicitDef()) {
108         if (MI->getOperand(0).getSubReg())
109           continue;
110         unsigned Reg = MI->getOperand(0).getReg();
111         ImpDefRegs.insert(Reg);
112         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
113           for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
114             ImpDefRegs.insert(*SS);
115         }
116         ImpDefMIs.push_back(MI);
117         continue;
118       }
119 
120       // Eliminate %reg1032:sub<def> = COPY undef.
121       if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
122         MachineOperand &MO = MI->getOperand(1);
123         if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
124           if (MO.isKill()) {
125             LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg());
126             vi.removeKill(MI);
127           }
128           unsigned Reg = MI->getOperand(0).getReg();
129           MI->eraseFromParent();
130           Changed = true;
131 
132           // A REG_SEQUENCE may have been expanded into partial definitions.
133           // If this was the last one, mark Reg as implicitly defined.
134           if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg))
135             ImpDefRegs.insert(Reg);
136           continue;
137         }
138       }
139 
140       bool ChangedToImpDef = false;
141       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
142         MachineOperand& MO = MI->getOperand(i);
143         if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
144           continue;
145         unsigned Reg = MO.getReg();
146         if (!Reg)
147           continue;
148         if (!ImpDefRegs.count(Reg))
149           continue;
150         // Use is a copy, just turn it into an implicit_def.
151         if (CanTurnIntoImplicitDef(MI, Reg, i, ImpDefRegs)) {
152           bool isKill = MO.isKill();
153           MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
154           for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
155             MI->RemoveOperand(j);
156           if (isKill) {
157             ImpDefRegs.erase(Reg);
158             LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
159             vi.removeKill(MI);
160           }
161           ChangedToImpDef = true;
162           Changed = true;
163           break;
164         }
165 
166         Changed = true;
167         MO.setIsUndef();
168         // This is a partial register redef of an implicit def.
169         // Make sure the whole register is defined by the instruction.
170         if (MO.isDef()) {
171           MI->addRegisterDefined(Reg);
172           continue;
173         }
174         if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
175           // Make sure other uses of
176           for (unsigned j = i+1; j != e; ++j) {
177             MachineOperand &MOJ = MI->getOperand(j);
178             if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
179               MOJ.setIsUndef();
180           }
181           ImpDefRegs.erase(Reg);
182         }
183       }
184 
185       if (ChangedToImpDef) {
186         // Backtrack to process this new implicit_def.
187         --I;
188       } else {
189         for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
190           MachineOperand& MO = MI->getOperand(i);
191           if (!MO.isReg() || !MO.isDef())
192             continue;
193           ImpDefRegs.erase(MO.getReg());
194         }
195       }
196     }
197 
198     // Any outstanding liveout implicit_def's?
199     for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
200       MachineInstr *MI = ImpDefMIs[i];
201       unsigned Reg = MI->getOperand(0).getReg();
202       if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
203           !ImpDefRegs.count(Reg)) {
204         // Delete all "local" implicit_def's. That include those which define
205         // physical registers since they cannot be liveout.
206         MI->eraseFromParent();
207         Changed = true;
208         continue;
209       }
210 
211       // If there are multiple defs of the same register and at least one
212       // is not an implicit_def, do not insert implicit_def's before the
213       // uses.
214       bool Skip = false;
215       SmallVector<MachineInstr*, 4> DeadImpDefs;
216       for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
217              DE = MRI->def_end(); DI != DE; ++DI) {
218         MachineInstr *DeadImpDef = &*DI;
219         if (!DeadImpDef->isImplicitDef()) {
220           Skip = true;
221           break;
222         }
223         DeadImpDefs.push_back(DeadImpDef);
224       }
225       if (Skip)
226         continue;
227 
228       // The only implicit_def which we want to keep are those that are live
229       // out of its block.
230       for (unsigned j = 0, ee = DeadImpDefs.size(); j != ee; ++j)
231         DeadImpDefs[j]->eraseFromParent();
232       Changed = true;
233 
234       // Process each use instruction once.
235       for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
236              UE = MRI->use_end(); UI != UE; ++UI) {
237         if (UI.getOperand().isUndef())
238           continue;
239         MachineInstr *RMI = &*UI;
240         if (ModInsts.insert(RMI))
241           RUses.push_back(RMI);
242       }
243 
244       for (unsigned i = 0, e = RUses.size(); i != e; ++i) {
245         MachineInstr *RMI = RUses[i];
246 
247         // Turn a copy use into an implicit_def.
248         if (isUndefCopy(RMI, Reg, ImpDefRegs)) {
249           RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
250 
251           bool isKill = false;
252           SmallVector<unsigned, 4> Ops;
253           for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
254             MachineOperand &RRMO = RMI->getOperand(j);
255             if (RRMO.isReg() && RRMO.getReg() == Reg) {
256               Ops.push_back(j);
257               if (RRMO.isKill())
258                 isKill = true;
259             }
260           }
261           // Leave the other operands along.
262           for (unsigned j = 0, ee = Ops.size(); j != ee; ++j) {
263             unsigned OpIdx = Ops[j];
264             RMI->RemoveOperand(OpIdx-j);
265           }
266 
267           // Update LiveVariables varinfo if the instruction is a kill.
268           if (isKill) {
269             LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
270             vi.removeKill(RMI);
271           }
272           continue;
273         }
274 
275         // Replace Reg with a new vreg that's marked implicit.
276         const TargetRegisterClass* RC = MRI->getRegClass(Reg);
277         unsigned NewVReg = MRI->createVirtualRegister(RC);
278         bool isKill = true;
279         for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
280           MachineOperand &RRMO = RMI->getOperand(j);
281           if (RRMO.isReg() && RRMO.getReg() == Reg) {
282             RRMO.setReg(NewVReg);
283             RRMO.setIsUndef();
284             if (isKill) {
285               // Only the first operand of NewVReg is marked kill.
286               RRMO.setIsKill();
287               isKill = false;
288             }
289           }
290         }
291       }
292       RUses.clear();
293       ModInsts.clear();
294     }
295     ImpDefRegs.clear();
296     ImpDefMIs.clear();
297   }
298 
299   return Changed;
300 }
301 
302