| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | OpenCL.std.h | 201 Clz = 151, enumerator
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1257 __ Clz(i.OutputRegister64(), i.InputRegister64(0)); in AssembleArchInstruction() local
1260 __ Clz(i.OutputRegister32(), i.InputRegister32(0)); in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.h | 214 Clz, enumerator
|
| D | IceInstARM32.h | 388 Clz, enumerator
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 438 void MacroAssembler::Clz(const Register& rd, const Register& rn) { in Clz() function
|
| /external/v8/src/compiler/mips/ |
| D | code-generator-mips.cc | 913 __ Clz(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 1654 __ Clz(w0, w24); in TEST() local
1655 __ Clz(x1, x24); in TEST() local
1656 __ Clz(w2, w25); in TEST() local
1657 __ Clz(x3, x25); in TEST() local
1658 __ Clz(w4, w26); in TEST() local
1659 __ Clz(x5, x26); in TEST() local
19387 __ Clz(v22.V8B(), v0.V8B()); in TEST() local
19388 __ Clz(v23.V16B(), v0.V16B()); in TEST() local
19389 __ Clz(v24.V4H(), v0.V4H()); in TEST() local
19390 __ Clz(v25.V8H(), v0.V8H()); in TEST() local
[all …]
|
| /external/v8/src/compiler/mips64/ |
| D | code-generator-mips64.cc | 1034 __ Clz(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1062 void Clz(const Register& rd, const Register& rn) { in Clz() function
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC() local
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 2371 void MacroAssembler::Clz(Register rd, Register rs) { in Clz() function in v8::internal::MacroAssembler
|
| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 2558 void MacroAssembler::Clz(Register rd, Register rs) { in Clz() function in v8::internal::MacroAssembler
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 2672 __ Clz(r0, r0); in TEST_T32() local
|
| /external/v8/src/crankshaft/mips/ |
| D | lithium-codegen-mips.cc | 3453 __ Clz(result, input); in DoMathClz32() local
|
| /external/v8/src/crankshaft/arm64/ |
| D | lithium-codegen-arm64.cc | 3645 __ Clz(result, input); in DoMathClz32() local
|
| /external/v8/src/crankshaft/mips64/ |
| D | lithium-codegen-mips64.cc | 3659 __ Clz(result, input); in DoMathClz32() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2375 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC() local
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1605 void Clz(Condition cond, Register rd, Register rm) { in Clz() function
1614 void Clz(Register rd, Register rm) { Clz(al, rd, rm); } in Clz() function
|