• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes an abstract interface used to get information about a
11 // target machines register file.  This information is used for a variety of
12 // purposed, especially register allocation.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
18 
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <cassert>
22 
23 namespace llvm {
24 
25 /// An unsigned integer type large enough to represent all physical registers,
26 /// but not necessarily virtual registers.
27 typedef uint16_t MCPhysReg;
28 
29 /// MCRegisterClass - Base class of TargetRegisterClass.
30 class MCRegisterClass {
31 public:
32   typedef const MCPhysReg* iterator;
33   typedef const MCPhysReg* const_iterator;
34 
35   const iterator RegsBegin;
36   const uint8_t *const RegSet;
37   const uint32_t NameIdx;
38   const uint16_t RegsSize;
39   const uint16_t RegSetSize;
40   const uint16_t ID;
41   const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
42   const int8_t CopyCost;
43   const bool Allocatable;
44 
45   /// getID() - Return the register class ID number.
46   ///
getID()47   unsigned getID() const { return ID; }
48 
49   /// begin/end - Return all of the registers in this class.
50   ///
begin()51   iterator       begin() const { return RegsBegin; }
end()52   iterator         end() const { return RegsBegin + RegsSize; }
53 
54   /// getNumRegs - Return the number of registers in this class.
55   ///
getNumRegs()56   unsigned getNumRegs() const { return RegsSize; }
57 
58   /// getRegister - Return the specified register in the class.
59   ///
getRegister(unsigned i)60   unsigned getRegister(unsigned i) const {
61     assert(i < getNumRegs() && "Register number out of range!");
62     return RegsBegin[i];
63   }
64 
65   /// contains - Return true if the specified register is included in this
66   /// register class.  This does not include virtual registers.
contains(unsigned Reg)67   bool contains(unsigned Reg) const {
68     unsigned InByte = Reg % 8;
69     unsigned Byte = Reg / 8;
70     if (Byte >= RegSetSize)
71       return false;
72     return (RegSet[Byte] & (1 << InByte)) != 0;
73   }
74 
75   /// contains - Return true if both registers are in this class.
contains(unsigned Reg1,unsigned Reg2)76   bool contains(unsigned Reg1, unsigned Reg2) const {
77     return contains(Reg1) && contains(Reg2);
78   }
79 
80   /// getSize - Return the size of the register in bytes, which is also the size
81   /// of a stack slot allocated to hold a spilled copy of this register.
getSize()82   unsigned getSize() const { return RegSize; }
83 
84   /// getAlignment - Return the minimum required alignment for a register of
85   /// this class.
getAlignment()86   unsigned getAlignment() const { return Alignment; }
87 
88   /// getCopyCost - Return the cost of copying a value between two registers in
89   /// this class. A negative number means the register class is very expensive
90   /// to copy e.g. status flag register classes.
getCopyCost()91   int getCopyCost() const { return CopyCost; }
92 
93   /// isAllocatable - Return true if this register class may be used to create
94   /// virtual registers.
isAllocatable()95   bool isAllocatable() const { return Allocatable; }
96 };
97 
98 /// MCRegisterDesc - This record contains information about a particular
99 /// register.  The SubRegs field is a zero terminated array of registers that
100 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101 /// of AX. The SuperRegs field is a zero terminated array of registers that are
102 /// super-registers of the specific register, e.g. RAX, EAX, are
103 /// super-registers of AX.
104 ///
105 struct MCRegisterDesc {
106   uint32_t Name;      // Printable name for the reg (for debugging)
107   uint32_t SubRegs;   // Sub-register set, described above
108   uint32_t SuperRegs; // Super-register set, described above
109 
110   // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111   // sub-register in SubRegs.
112   uint32_t SubRegIndices;
113 
114   // RegUnits - Points to the list of register units. The low 4 bits holds the
115   // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
116   uint32_t RegUnits;
117 
118   /// Index into list with lane mask sequences. The sequence contains a lanemask
119   /// for every register unit.
120   uint16_t RegUnitLaneMasks;
121 };
122 
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has.  As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
127 /// descriptor.
128 ///
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
133 /// virtual methods.
134 ///
135 class MCRegisterInfo {
136 public:
137   typedef const MCRegisterClass *regclass_iterator;
138 
139   /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140   /// performed with a binary search.
141   struct DwarfLLVMRegPair {
142     unsigned FromReg;
143     unsigned ToReg;
144 
145     bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
146   };
147 
148   /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149   /// index, -1 in any being invalid.
150   struct SubRegCoveredBits {
151     uint16_t Offset;
152     uint16_t Size;
153   };
154 private:
155   const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
156   unsigned NumRegs;                           // Number of entries in the array
157   unsigned RAReg;                             // Return address register
158   unsigned PCReg;                             // Program counter register
159   const MCRegisterClass *Classes;             // Pointer to the regclass array
160   unsigned NumClasses;                        // Number of entries in the array
161   unsigned NumRegUnits;                       // Number of regunits.
162   const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
163   const MCPhysReg *DiffLists;                 // Pointer to the difflists array
164   const unsigned *RegUnitMaskSequences;       // Pointer to lane mask sequences
165                                               // for register units.
166   const char *RegStrings;                     // Pointer to the string table.
167   const char *RegClassStrings;                // Pointer to the class strings.
168   const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
169                                               // array.
170   const SubRegCoveredBits *SubRegIdxRanges;   // Pointer to the subreg covered
171                                               // bit ranges array.
172   unsigned NumSubRegIndices;                  // Number of subreg indices.
173   const uint16_t *RegEncodingTable;           // Pointer to array of register
174                                               // encodings.
175 
176   unsigned L2DwarfRegsSize;
177   unsigned EHL2DwarfRegsSize;
178   unsigned Dwarf2LRegsSize;
179   unsigned EHDwarf2LRegsSize;
180   const DwarfLLVMRegPair *L2DwarfRegs;        // LLVM to Dwarf regs mapping
181   const DwarfLLVMRegPair *EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
182   const DwarfLLVMRegPair *Dwarf2LRegs;        // Dwarf to LLVM regs mapping
183   const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
184   DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
185   DenseMap<unsigned, int> L2CVRegs;           // LLVM to CV regs mapping
186 
187 public:
188   /// DiffListIterator - Base iterator class that can traverse the
189   /// differentially encoded register and regunit lists in DiffLists.
190   /// Don't use this class directly, use one of the specialized sub-classes
191   /// defined below.
192   class DiffListIterator {
193     uint16_t Val;
194     const MCPhysReg *List;
195 
196   protected:
197     /// Create an invalid iterator. Call init() to point to something useful.
DiffListIterator()198     DiffListIterator() : Val(0), List(nullptr) {}
199 
200     /// init - Point the iterator to InitVal, decoding subsequent values from
201     /// DiffList. The iterator will initially point to InitVal, sub-classes are
202     /// responsible for skipping the seed value if it is not part of the list.
init(MCPhysReg InitVal,const MCPhysReg * DiffList)203     void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
204       Val = InitVal;
205       List = DiffList;
206     }
207 
208     /// advance - Move to the next list position, return the applied
209     /// differential. This function does not detect the end of the list, that
210     /// is the caller's responsibility (by checking for a 0 return value).
advance()211     unsigned advance() {
212       assert(isValid() && "Cannot move off the end of the list.");
213       MCPhysReg D = *List++;
214       Val += D;
215       return D;
216     }
217 
218   public:
219 
220     /// isValid - returns true if this iterator is not yet at the end.
isValid()221     bool isValid() const { return List; }
222 
223     /// Dereference the iterator to get the value at the current position.
224     unsigned operator*() const { return Val; }
225 
226     /// Pre-increment to move to the next position.
227     void operator++() {
228       // The end of the list is encoded as a 0 differential.
229       if (!advance())
230         List = nullptr;
231     }
232   };
233 
234   // These iterators are allowed to sub-class DiffListIterator and access
235   // internal list pointers.
236   friend class MCSubRegIterator;
237   friend class MCSubRegIndexIterator;
238   friend class MCSuperRegIterator;
239   friend class MCRegUnitIterator;
240   friend class MCRegUnitMaskIterator;
241   friend class MCRegUnitRootIterator;
242 
243   /// \brief Initialize MCRegisterInfo, called by TableGen
244   /// auto-generated routines. *DO NOT USE*.
InitMCRegisterInfo(const MCRegisterDesc * D,unsigned NR,unsigned RA,unsigned PC,const MCRegisterClass * C,unsigned NC,const MCPhysReg (* RURoots)[2],unsigned NRU,const MCPhysReg * DL,const unsigned * RUMS,const char * Strings,const char * ClassStrings,const uint16_t * SubIndices,unsigned NumIndices,const SubRegCoveredBits * SubIdxRanges,const uint16_t * RET)245   void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
246                           unsigned PC,
247                           const MCRegisterClass *C, unsigned NC,
248                           const MCPhysReg (*RURoots)[2],
249                           unsigned NRU,
250                           const MCPhysReg *DL,
251                           const unsigned *RUMS,
252                           const char *Strings,
253                           const char *ClassStrings,
254                           const uint16_t *SubIndices,
255                           unsigned NumIndices,
256                           const SubRegCoveredBits *SubIdxRanges,
257                           const uint16_t *RET) {
258     Desc = D;
259     NumRegs = NR;
260     RAReg = RA;
261     PCReg = PC;
262     Classes = C;
263     DiffLists = DL;
264     RegUnitMaskSequences = RUMS;
265     RegStrings = Strings;
266     RegClassStrings = ClassStrings;
267     NumClasses = NC;
268     RegUnitRoots = RURoots;
269     NumRegUnits = NRU;
270     SubRegIndices = SubIndices;
271     NumSubRegIndices = NumIndices;
272     SubRegIdxRanges = SubIdxRanges;
273     RegEncodingTable = RET;
274   }
275 
276   /// \brief Used to initialize LLVM register to Dwarf
277   /// register number mapping. Called by TableGen auto-generated routines.
278   /// *DO NOT USE*.
mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair * Map,unsigned Size,bool isEH)279   void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
280                               bool isEH) {
281     if (isEH) {
282       EHL2DwarfRegs = Map;
283       EHL2DwarfRegsSize = Size;
284     } else {
285       L2DwarfRegs = Map;
286       L2DwarfRegsSize = Size;
287     }
288   }
289 
290   /// \brief Used to initialize Dwarf register to LLVM
291   /// register number mapping. Called by TableGen auto-generated routines.
292   /// *DO NOT USE*.
mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair * Map,unsigned Size,bool isEH)293   void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
294                               bool isEH) {
295     if (isEH) {
296       EHDwarf2LRegs = Map;
297       EHDwarf2LRegsSize = Size;
298     } else {
299       Dwarf2LRegs = Map;
300       Dwarf2LRegsSize = Size;
301     }
302   }
303 
304   /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
305   /// number mapping. By default the SEH register number is just the same
306   /// as the LLVM register number.
307   /// FIXME: TableGen these numbers. Currently this requires target specific
308   /// initialization code.
mapLLVMRegToSEHReg(unsigned LLVMReg,int SEHReg)309   void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
310     L2SEHRegs[LLVMReg] = SEHReg;
311   }
312 
mapLLVMRegToCVReg(unsigned LLVMReg,int CVReg)313   void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
314     L2CVRegs[LLVMReg] = CVReg;
315   }
316 
317   /// \brief This method should return the register where the return
318   /// address can be found.
getRARegister()319   unsigned getRARegister() const {
320     return RAReg;
321   }
322 
323   /// Return the register which is the program counter.
getProgramCounter()324   unsigned getProgramCounter() const {
325     return PCReg;
326   }
327 
328   const MCRegisterDesc &operator[](unsigned RegNo) const {
329     assert(RegNo < NumRegs &&
330            "Attempting to access record for invalid register number!");
331     return Desc[RegNo];
332   }
333 
334   /// \brief Provide a get method, equivalent to [], but more useful with a
335   /// pointer to this object.
get(unsigned RegNo)336   const MCRegisterDesc &get(unsigned RegNo) const {
337     return operator[](RegNo);
338   }
339 
340   /// \brief Returns the physical register number of sub-register "Index"
341   /// for physical register RegNo. Return zero if the sub-register does not
342   /// exist.
343   unsigned getSubReg(unsigned Reg, unsigned Idx) const;
344 
345   /// \brief Return a super-register of the specified register
346   /// Reg so its sub-register of index SubIdx is Reg.
347   unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
348                                const MCRegisterClass *RC) const;
349 
350   /// \brief For a given register pair, return the sub-register index
351   /// if the second register is a sub-register of the first. Return zero
352   /// otherwise.
353   unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
354 
355   /// \brief Get the size of the bit range covered by a sub-register index.
356   /// If the index isn't continuous, return the sum of the sizes of its parts.
357   /// If the index is used to access subregisters of different sizes, return -1.
358   unsigned getSubRegIdxSize(unsigned Idx) const;
359 
360   /// \brief Get the offset of the bit range covered by a sub-register index.
361   /// If an Offset doesn't make sense (the index isn't continuous, or is used to
362   /// access sub-registers at different offsets), return -1.
363   unsigned getSubRegIdxOffset(unsigned Idx) const;
364 
365   /// \brief Return the human-readable symbolic target-specific name for the
366   /// specified physical register.
getName(unsigned RegNo)367   const char *getName(unsigned RegNo) const {
368     return RegStrings + get(RegNo).Name;
369   }
370 
371   /// \brief Return the number of registers this target has (useful for
372   /// sizing arrays holding per register information)
getNumRegs()373   unsigned getNumRegs() const {
374     return NumRegs;
375   }
376 
377   /// \brief Return the number of sub-register indices
378   /// understood by the target. Index 0 is reserved for the no-op sub-register,
379   /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
getNumSubRegIndices()380   unsigned getNumSubRegIndices() const {
381     return NumSubRegIndices;
382   }
383 
384   /// \brief Return the number of (native) register units in the
385   /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
386   /// can be accessed through MCRegUnitIterator defined below.
getNumRegUnits()387   unsigned getNumRegUnits() const {
388     return NumRegUnits;
389   }
390 
391   /// \brief Map a target register to an equivalent dwarf register
392   /// number.  Returns -1 if there is no equivalent value.  The second
393   /// parameter allows targets to use different numberings for EH info and
394   /// debugging info.
395   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
396 
397   /// \brief Map a dwarf register back to a target register.
398   int getLLVMRegNum(unsigned RegNum, bool isEH) const;
399 
400   /// \brief Map a target register to an equivalent SEH register
401   /// number.  Returns LLVM register number if there is no equivalent value.
402   int getSEHRegNum(unsigned RegNum) const;
403 
404   /// \brief Map a target register to an equivalent CodeView register
405   /// number.
406   int getCodeViewRegNum(unsigned RegNum) const;
407 
regclass_begin()408   regclass_iterator regclass_begin() const { return Classes; }
regclass_end()409   regclass_iterator regclass_end() const { return Classes+NumClasses; }
410 
getNumRegClasses()411   unsigned getNumRegClasses() const {
412     return (unsigned)(regclass_end()-regclass_begin());
413   }
414 
415   /// \brief Returns the register class associated with the enumeration
416   /// value.  See class MCOperandInfo.
getRegClass(unsigned i)417   const MCRegisterClass& getRegClass(unsigned i) const {
418     assert(i < getNumRegClasses() && "Register Class ID out of range");
419     return Classes[i];
420   }
421 
getRegClassName(const MCRegisterClass * Class)422   const char *getRegClassName(const MCRegisterClass *Class) const {
423     return RegClassStrings + Class->NameIdx;
424   }
425 
426    /// \brief Returns the encoding for RegNo
getEncodingValue(unsigned RegNo)427   uint16_t getEncodingValue(unsigned RegNo) const {
428     assert(RegNo < NumRegs &&
429            "Attempting to get encoding for invalid register number!");
430     return RegEncodingTable[RegNo];
431   }
432 
433   /// \brief Returns true if RegB is a sub-register of RegA.
isSubRegister(unsigned RegA,unsigned RegB)434   bool isSubRegister(unsigned RegA, unsigned RegB) const {
435     return isSuperRegister(RegB, RegA);
436   }
437 
438   /// \brief Returns true if RegB is a super-register of RegA.
439   bool isSuperRegister(unsigned RegA, unsigned RegB) const;
440 
441   /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
isSubRegisterEq(unsigned RegA,unsigned RegB)442   bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
443     return isSuperRegisterEq(RegB, RegA);
444   }
445 
446   /// \brief Returns true if RegB is a super-register of RegA or if
447   /// RegB == RegA.
isSuperRegisterEq(unsigned RegA,unsigned RegB)448   bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
449     return RegA == RegB || isSuperRegister(RegA, RegB);
450   }
451 
452   /// \brief Returns true if RegB is a super-register or sub-register of RegA
453   /// or if RegB == RegA.
isSuperOrSubRegisterEq(unsigned RegA,unsigned RegB)454   bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
455     return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
456   }
457 };
458 
459 //===----------------------------------------------------------------------===//
460 //                          Register List Iterators
461 //===----------------------------------------------------------------------===//
462 
463 // MCRegisterInfo provides lists of super-registers, sub-registers, and
464 // aliasing registers. Use these iterator classes to traverse the lists.
465 
466 /// MCSubRegIterator enumerates all sub-registers of Reg.
467 /// If IncludeSelf is set, Reg itself is included in the list.
468 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
469 public:
470   MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
471                      bool IncludeSelf = false) {
472     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
473     // Initially, the iterator points to Reg itself.
474     if (!IncludeSelf)
475       ++*this;
476   }
477 };
478 
479 /// Iterator that enumerates the sub-registers of a Reg and the associated
480 /// sub-register indices.
481 class MCSubRegIndexIterator {
482   MCSubRegIterator SRIter;
483   const uint16_t *SRIndex;
484 public:
485   /// Constructs an iterator that traverses subregisters and their
486   /// associated subregister indices.
MCSubRegIndexIterator(unsigned Reg,const MCRegisterInfo * MCRI)487   MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
488     : SRIter(Reg, MCRI) {
489     SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
490   }
491 
492   /// Returns current sub-register.
getSubReg()493   unsigned getSubReg() const {
494     return *SRIter;
495   }
496   /// Returns sub-register index of the current sub-register.
getSubRegIndex()497   unsigned getSubRegIndex() const {
498     return *SRIndex;
499   }
500 
501   /// Returns true if this iterator is not yet at the end.
isValid()502   bool isValid() const { return SRIter.isValid(); }
503 
504   /// Moves to the next position.
505   void operator++() {
506     ++SRIter;
507     ++SRIndex;
508   }
509 };
510 
511 /// MCSuperRegIterator enumerates all super-registers of Reg.
512 /// If IncludeSelf is set, Reg itself is included in the list.
513 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
514 public:
MCSuperRegIterator()515   MCSuperRegIterator() {}
516   MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
517                      bool IncludeSelf = false) {
518     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
519     // Initially, the iterator points to Reg itself.
520     if (!IncludeSelf)
521       ++*this;
522   }
523 };
524 
525 // Definition for isSuperRegister. Put it down here since it needs the
526 // iterator defined above in addition to the MCRegisterInfo class itself.
isSuperRegister(unsigned RegA,unsigned RegB)527 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
528   for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
529     if (*I == RegB)
530       return true;
531   return false;
532 }
533 
534 //===----------------------------------------------------------------------===//
535 //                               Register Units
536 //===----------------------------------------------------------------------===//
537 
538 // Register units are used to compute register aliasing. Every register has at
539 // least one register unit, but it can have more. Two registers overlap if and
540 // only if they have a common register unit.
541 //
542 // A target with a complicated sub-register structure will typically have many
543 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
544 // the number of register units in the target.
545 
546 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
547 // in ascending numerical order.
548 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
549 public:
550   /// MCRegUnitIterator - Create an iterator that traverses the register units
551   /// in Reg.
MCRegUnitIterator()552   MCRegUnitIterator() {}
MCRegUnitIterator(unsigned Reg,const MCRegisterInfo * MCRI)553   MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
554     assert(Reg && "Null register has no regunits");
555     // Decode the RegUnits MCRegisterDesc field.
556     unsigned RU = MCRI->get(Reg).RegUnits;
557     unsigned Scale = RU & 15;
558     unsigned Offset = RU >> 4;
559 
560     // Initialize the iterator to Reg * Scale, and the List pointer to
561     // DiffLists + Offset.
562     init(Reg * Scale, MCRI->DiffLists + Offset);
563 
564     // That may not be a valid unit, we need to advance by one to get the real
565     // unit number. The first differential can be 0 which would normally
566     // terminate the list, but since we know every register has at least one
567     // unit, we can allow a 0 differential here.
568     advance();
569   }
570 };
571 
572 /// MCRegUnitIterator enumerates a list of register units and their associated
573 /// lane masks for Reg. The register units are in ascending numerical order.
574 class MCRegUnitMaskIterator {
575   MCRegUnitIterator RUIter;
576   const unsigned *MaskListIter;
577 public:
MCRegUnitMaskIterator()578   MCRegUnitMaskIterator() {}
579   /// Constructs an iterator that traverses the register units and their
580   /// associated LaneMasks in Reg.
MCRegUnitMaskIterator(unsigned Reg,const MCRegisterInfo * MCRI)581   MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
582     : RUIter(Reg, MCRI) {
583       uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
584       MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
585   }
586 
587   /// Returns a (RegUnit, LaneMask) pair.
588   std::pair<unsigned,unsigned> operator*() const {
589     return std::make_pair(*RUIter, *MaskListIter);
590   }
591 
592   /// Returns true if this iterator is not yet at the end.
isValid()593   bool isValid() const { return RUIter.isValid(); }
594 
595   /// Moves to the next position.
596   void operator++() {
597     ++MaskListIter;
598     ++RUIter;
599   }
600 };
601 
602 // Each register unit has one or two root registers. The complete set of
603 // registers containing a register unit is the union of the roots and their
604 // super-registers. All registers aliasing Unit can be visited like this:
605 //
606 //   for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
607 //     for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
608 //       visit(*SI);
609 //    }
610 
611 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
612 class MCRegUnitRootIterator {
613   uint16_t Reg0;
614   uint16_t Reg1;
615 public:
MCRegUnitRootIterator()616   MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
MCRegUnitRootIterator(unsigned RegUnit,const MCRegisterInfo * MCRI)617   MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
618     assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
619     Reg0 = MCRI->RegUnitRoots[RegUnit][0];
620     Reg1 = MCRI->RegUnitRoots[RegUnit][1];
621   }
622 
623   /// \brief Dereference to get the current root register.
624   unsigned operator*() const {
625     return Reg0;
626   }
627 
628   /// \brief Check if the iterator is at the end of the list.
isValid()629   bool isValid() const {
630     return Reg0;
631   }
632 
633   /// \brief Preincrement to move to the next root register.
634   void operator++() {
635     assert(isValid() && "Cannot move off the end of the list.");
636     Reg0 = Reg1;
637     Reg1 = 0;
638   }
639 };
640 
641 /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
642 /// set, Reg itself is included in the list.  This iterator does not guarantee
643 /// any ordering or that entries are unique.
644 class MCRegAliasIterator {
645 private:
646   unsigned Reg;
647   const MCRegisterInfo *MCRI;
648   bool IncludeSelf;
649 
650   MCRegUnitIterator RI;
651   MCRegUnitRootIterator RRI;
652   MCSuperRegIterator SI;
653 public:
MCRegAliasIterator(unsigned Reg,const MCRegisterInfo * MCRI,bool IncludeSelf)654   MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
655                      bool IncludeSelf)
656     : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
657 
658     // Initialize the iterators.
659     for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
660       for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
661         for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
662           if (!(!IncludeSelf && Reg == *SI))
663             return;
664         }
665       }
666     }
667   }
668 
isValid()669   bool isValid() const { return RI.isValid(); }
670 
671   unsigned operator*() const {
672     assert (SI.isValid() && "Cannot dereference an invalid iterator.");
673     return *SI;
674   }
675 
advance()676   void advance() {
677     // Assuming SI is valid.
678     ++SI;
679     if (SI.isValid()) return;
680 
681     ++RRI;
682     if (RRI.isValid()) {
683       SI = MCSuperRegIterator(*RRI, MCRI, true);
684       return;
685     }
686 
687     ++RI;
688     if (RI.isValid()) {
689       RRI = MCRegUnitRootIterator(*RI, MCRI);
690       SI = MCSuperRegIterator(*RRI, MCRI, true);
691     }
692   }
693 
694   void operator++() {
695     assert(isValid() && "Cannot move off the end of the list.");
696     do advance();
697     while (!IncludeSelf && isValid() && *SI == Reg);
698   }
699 };
700 
701 } // End llvm namespace
702 
703 #endif
704