1 #ifndef GEN_RENDER_DYNAMIC_XML 2 #define GEN_RENDER_DYNAMIC_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 https://github.com/olvaffe/envytools/ 8 git clone https://github.com/olvaffe/envytools.git 9 10 Copyright (C) 2014-2015 by the following authors: 11 - Chia-I Wu <olvaffe@gmail.com> (olv) 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice (including the 22 next paragraph) shall be included in all copies or substantial 23 portions of the Software. 24 25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 enum gen_compare_function { 36 GEN6_COMPAREFUNCTION_ALWAYS = 0x0, 37 GEN6_COMPAREFUNCTION_NEVER = 0x1, 38 GEN6_COMPAREFUNCTION_LESS = 0x2, 39 GEN6_COMPAREFUNCTION_EQUAL = 0x3, 40 GEN6_COMPAREFUNCTION_LEQUAL = 0x4, 41 GEN6_COMPAREFUNCTION_GREATER = 0x5, 42 GEN6_COMPAREFUNCTION_NOTEQUAL = 0x6, 43 GEN6_COMPAREFUNCTION_GEQUAL = 0x7, 44 }; 45 46 enum gen_stencil_op { 47 GEN6_STENCILOP_KEEP = 0x0, 48 GEN6_STENCILOP_ZERO = 0x1, 49 GEN6_STENCILOP_REPLACE = 0x2, 50 GEN6_STENCILOP_INCRSAT = 0x3, 51 GEN6_STENCILOP_DECRSAT = 0x4, 52 GEN6_STENCILOP_INCR = 0x5, 53 GEN6_STENCILOP_DECR = 0x6, 54 GEN6_STENCILOP_INVERT = 0x7, 55 }; 56 57 enum gen_blend_factor { 58 GEN6_BLENDFACTOR_ONE = 0x1, 59 GEN6_BLENDFACTOR_SRC_COLOR = 0x2, 60 GEN6_BLENDFACTOR_SRC_ALPHA = 0x3, 61 GEN6_BLENDFACTOR_DST_ALPHA = 0x4, 62 GEN6_BLENDFACTOR_DST_COLOR = 0x5, 63 GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE = 0x6, 64 GEN6_BLENDFACTOR_CONST_COLOR = 0x7, 65 GEN6_BLENDFACTOR_CONST_ALPHA = 0x8, 66 GEN6_BLENDFACTOR_SRC1_COLOR = 0x9, 67 GEN6_BLENDFACTOR_SRC1_ALPHA = 0xa, 68 GEN6_BLENDFACTOR_ZERO = 0x11, 69 GEN6_BLENDFACTOR_INV_SRC_COLOR = 0x12, 70 GEN6_BLENDFACTOR_INV_SRC_ALPHA = 0x13, 71 GEN6_BLENDFACTOR_INV_DST_ALPHA = 0x14, 72 GEN6_BLENDFACTOR_INV_DST_COLOR = 0x15, 73 GEN6_BLENDFACTOR_INV_CONST_COLOR = 0x17, 74 GEN6_BLENDFACTOR_INV_CONST_ALPHA = 0x18, 75 GEN6_BLENDFACTOR_INV_SRC1_COLOR = 0x19, 76 GEN6_BLENDFACTOR_INV_SRC1_ALPHA = 0x1a, 77 }; 78 79 enum gen_blend_function { 80 GEN6_BLENDFUNCTION_ADD = 0x0, 81 GEN6_BLENDFUNCTION_SUBTRACT = 0x1, 82 GEN6_BLENDFUNCTION_REVERSE_SUBTRACT = 0x2, 83 GEN6_BLENDFUNCTION_MIN = 0x3, 84 GEN6_BLENDFUNCTION_MAX = 0x4, 85 }; 86 87 enum gen_logic_op { 88 GEN6_LOGICOP_CLEAR = 0x0, 89 GEN6_LOGICOP_NOR = 0x1, 90 GEN6_LOGICOP_AND_INVERTED = 0x2, 91 GEN6_LOGICOP_COPY_INVERTED = 0x3, 92 GEN6_LOGICOP_AND_REVERSE = 0x4, 93 GEN6_LOGICOP_INVERT = 0x5, 94 GEN6_LOGICOP_XOR = 0x6, 95 GEN6_LOGICOP_NAND = 0x7, 96 GEN6_LOGICOP_AND = 0x8, 97 GEN6_LOGICOP_EQUIV = 0x9, 98 GEN6_LOGICOP_NOOP = 0xa, 99 GEN6_LOGICOP_OR_INVERTED = 0xb, 100 GEN6_LOGICOP_COPY = 0xc, 101 GEN6_LOGICOP_OR_REVERSE = 0xd, 102 GEN6_LOGICOP_OR = 0xe, 103 GEN6_LOGICOP_SET = 0xf, 104 }; 105 106 enum gen_mip_filter { 107 GEN6_MIPFILTER_NONE = 0x0, 108 GEN6_MIPFILTER_NEAREST = 0x1, 109 GEN6_MIPFILTER_LINEAR = 0x3, 110 }; 111 112 enum gen_map_filter { 113 GEN6_MAPFILTER_NEAREST = 0x0, 114 GEN6_MAPFILTER_LINEAR = 0x1, 115 GEN6_MAPFILTER_ANISOTROPIC = 0x2, 116 GEN6_MAPFILTER_MONO = 0x6, 117 }; 118 119 enum gen_prefilter_op { 120 GEN6_PREFILTEROP_ALWAYS = 0x0, 121 GEN6_PREFILTEROP_NEVER = 0x1, 122 GEN6_PREFILTEROP_LESS = 0x2, 123 GEN6_PREFILTEROP_EQUAL = 0x3, 124 GEN6_PREFILTEROP_LEQUAL = 0x4, 125 GEN6_PREFILTEROP_GREATER = 0x5, 126 GEN6_PREFILTEROP_NOTEQUAL = 0x6, 127 GEN6_PREFILTEROP_GEQUAL = 0x7, 128 }; 129 130 enum gen_aniso_ratio { 131 GEN6_ANISORATIO_2 = 0x0, 132 GEN6_ANISORATIO_4 = 0x1, 133 GEN6_ANISORATIO_6 = 0x2, 134 GEN6_ANISORATIO_8 = 0x3, 135 GEN6_ANISORATIO_10 = 0x4, 136 GEN6_ANISORATIO_12 = 0x5, 137 GEN6_ANISORATIO_14 = 0x6, 138 GEN6_ANISORATIO_16 = 0x7, 139 }; 140 141 enum gen_texcoord_mode { 142 GEN6_TEXCOORDMODE_WRAP = 0x0, 143 GEN6_TEXCOORDMODE_MIRROR = 0x1, 144 GEN6_TEXCOORDMODE_CLAMP = 0x2, 145 GEN6_TEXCOORDMODE_CUBE = 0x3, 146 GEN6_TEXCOORDMODE_CLAMP_BORDER = 0x4, 147 GEN6_TEXCOORDMODE_MIRROR_ONCE = 0x5, 148 GEN8_TEXCOORDMODE_HALF_BORDER = 0x6, 149 }; 150 151 enum gen_key_filter { 152 GEN6_KEYFILTER_KILL_ON_ANY_MATCH = 0x0, 153 GEN6_KEYFILTER_REPLACE_BLACK = 0x1, 154 }; 155 156 #define GEN6_COLOR_CALC_STATE__SIZE 6 157 158 #define GEN6_CC_DW0_STENCIL_REF__MASK 0xff000000 159 #define GEN6_CC_DW0_STENCIL_REF__SHIFT 24 160 #define GEN6_CC_DW0_STENCIL1_REF__MASK 0x00ff0000 161 #define GEN6_CC_DW0_STENCIL1_REF__SHIFT 16 162 #define GEN6_CC_DW0_ROUND_DISABLE_DISABLE (0x1 << 15) 163 #define GEN6_CC_DW0_ALPHATEST__MASK 0x00000001 164 #define GEN6_CC_DW0_ALPHATEST__SHIFT 0 165 #define GEN6_CC_DW0_ALPHATEST_UNORM8 0x0 166 #define GEN6_CC_DW0_ALPHATEST_FLOAT32 0x1 167 168 169 170 171 172 173 #define GEN6_DEPTH_STENCIL_STATE__SIZE 3 174 175 #define GEN6_ZS_DW0_STENCIL_TEST_ENABLE (0x1 << 31) 176 #define GEN6_ZS_DW0_STENCIL_FUNC__MASK 0x70000000 177 #define GEN6_ZS_DW0_STENCIL_FUNC__SHIFT 28 178 #define GEN6_ZS_DW0_STENCIL_FAIL_OP__MASK 0x0e000000 179 #define GEN6_ZS_DW0_STENCIL_FAIL_OP__SHIFT 25 180 #define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__MASK 0x01c00000 181 #define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__SHIFT 22 182 #define GEN6_ZS_DW0_STENCIL_ZPASS_OP__MASK 0x00380000 183 #define GEN6_ZS_DW0_STENCIL_ZPASS_OP__SHIFT 19 184 #define GEN6_ZS_DW0_STENCIL_WRITE_ENABLE (0x1 << 18) 185 #define GEN6_ZS_DW0_STENCIL1_ENABLE (0x1 << 15) 186 #define GEN6_ZS_DW0_STENCIL1_FUNC__MASK 0x00007000 187 #define GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT 12 188 #define GEN6_ZS_DW0_STENCIL1_FAIL_OP__MASK 0x00000e00 189 #define GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT 9 190 #define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__MASK 0x000001c0 191 #define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT 6 192 #define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__MASK 0x00000038 193 #define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT 3 194 195 #define GEN6_ZS_DW1_STENCIL_TEST_MASK__MASK 0xff000000 196 #define GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT 24 197 #define GEN6_ZS_DW1_STENCIL_WRITE_MASK__MASK 0x00ff0000 198 #define GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT 16 199 #define GEN6_ZS_DW1_STENCIL1_TEST_MASK__MASK 0x0000ff00 200 #define GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT 8 201 #define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__MASK 0x000000ff 202 #define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT 0 203 204 #define GEN6_ZS_DW2_DEPTH_TEST_ENABLE (0x1 << 31) 205 #define GEN6_ZS_DW2_DEPTH_FUNC__MASK 0x38000000 206 #define GEN6_ZS_DW2_DEPTH_FUNC__SHIFT 27 207 #define GEN6_ZS_DW2_DEPTH_WRITE_ENABLE (0x1 << 26) 208 209 #define GEN6_BLEND_STATE__SIZE 17 210 211 212 #define GEN6_RT_DW0_BLEND_ENABLE (0x1 << 31) 213 #define GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30) 214 #define GEN6_RT_DW0_ALPHA_FUNC__MASK 0x1c000000 215 #define GEN6_RT_DW0_ALPHA_FUNC__SHIFT 26 216 #define GEN6_RT_DW0_SRC_ALPHA_FACTOR__MASK 0x01f00000 217 #define GEN6_RT_DW0_SRC_ALPHA_FACTOR__SHIFT 20 218 #define GEN6_RT_DW0_DST_ALPHA_FACTOR__MASK 0x000f8000 219 #define GEN6_RT_DW0_DST_ALPHA_FACTOR__SHIFT 15 220 #define GEN6_RT_DW0_COLOR_FUNC__MASK 0x00003800 221 #define GEN6_RT_DW0_COLOR_FUNC__SHIFT 11 222 #define GEN6_RT_DW0_SRC_COLOR_FACTOR__MASK 0x000003e0 223 #define GEN6_RT_DW0_SRC_COLOR_FACTOR__SHIFT 5 224 #define GEN6_RT_DW0_DST_COLOR_FACTOR__MASK 0x0000001f 225 #define GEN6_RT_DW0_DST_COLOR_FACTOR__SHIFT 0 226 227 #define GEN6_RT_DW1_ALPHA_TO_COVERAGE (0x1 << 31) 228 #define GEN6_RT_DW1_ALPHA_TO_ONE (0x1 << 30) 229 #define GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER (0x1 << 29) 230 #define GEN6_RT_DW1_WRITE_DISABLES__MASK 0x0f000000 231 #define GEN6_RT_DW1_WRITE_DISABLES__SHIFT 24 232 #define GEN6_RT_DW1_WRITE_DISABLES_A (0x1 << 27) 233 #define GEN6_RT_DW1_WRITE_DISABLES_R (0x1 << 26) 234 #define GEN6_RT_DW1_WRITE_DISABLES_G (0x1 << 25) 235 #define GEN6_RT_DW1_WRITE_DISABLES_B (0x1 << 24) 236 #define GEN6_RT_DW1_LOGICOP_ENABLE (0x1 << 22) 237 #define GEN6_RT_DW1_LOGICOP_FUNC__MASK 0x003c0000 238 #define GEN6_RT_DW1_LOGICOP_FUNC__SHIFT 18 239 #define GEN6_RT_DW1_ALPHA_TEST_ENABLE (0x1 << 16) 240 #define GEN6_RT_DW1_ALPHA_TEST_FUNC__MASK 0x0000e000 241 #define GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT 13 242 #define GEN6_RT_DW1_DITHER_ENABLE (0x1 << 12) 243 #define GEN6_RT_DW1_X_DITHER_OFFSET__MASK 0x00000c00 244 #define GEN6_RT_DW1_X_DITHER_OFFSET__SHIFT 10 245 #define GEN6_RT_DW1_Y_DITHER_OFFSET__MASK 0x00000300 246 #define GEN6_RT_DW1_Y_DITHER_OFFSET__SHIFT 8 247 #define GEN6_RT_DW1_COLORCLAMP__MASK 0x0000000c 248 #define GEN6_RT_DW1_COLORCLAMP__SHIFT 2 249 #define GEN6_RT_DW1_COLORCLAMP_UNORM (0x0 << 2) 250 #define GEN6_RT_DW1_COLORCLAMP_SNORM (0x1 << 2) 251 #define GEN6_RT_DW1_COLORCLAMP_RTFORMAT (0x2 << 2) 252 #define GEN6_RT_DW1_PRE_BLEND_CLAMP (0x1 << 1) 253 #define GEN6_RT_DW1_POST_BLEND_CLAMP (0x1 << 0) 254 255 256 #define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE (0x1 << 31) 257 #define GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30) 258 #define GEN8_BLEND_DW0_ALPHA_TO_ONE (0x1 << 29) 259 #define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER (0x1 << 28) 260 #define GEN8_BLEND_DW0_ALPHA_TEST_ENABLE (0x1 << 27) 261 #define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__MASK 0x07000000 262 #define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT 24 263 #define GEN8_BLEND_DW0_DITHER_ENABLE (0x1 << 23) 264 #define GEN8_BLEND_DW0_X_DITHER_OFFSET__MASK 0x00600000 265 #define GEN8_BLEND_DW0_X_DITHER_OFFSET__SHIFT 21 266 #define GEN8_BLEND_DW0_Y_DITHER_OFFSET__MASK 0x00180000 267 #define GEN8_BLEND_DW0_Y_DITHER_OFFSET__SHIFT 19 268 269 270 #define GEN8_RT_DW0_BLEND_ENABLE (0x1 << 31) 271 #define GEN8_RT_DW0_SRC_COLOR_FACTOR__MASK 0x7c000000 272 #define GEN8_RT_DW0_SRC_COLOR_FACTOR__SHIFT 26 273 #define GEN8_RT_DW0_DST_COLOR_FACTOR__MASK 0x03e00000 274 #define GEN8_RT_DW0_DST_COLOR_FACTOR__SHIFT 21 275 #define GEN8_RT_DW0_COLOR_FUNC__MASK 0x001c0000 276 #define GEN8_RT_DW0_COLOR_FUNC__SHIFT 18 277 #define GEN8_RT_DW0_SRC_ALPHA_FACTOR__MASK 0x0003e000 278 #define GEN8_RT_DW0_SRC_ALPHA_FACTOR__SHIFT 13 279 #define GEN8_RT_DW0_DST_ALPHA_FACTOR__MASK 0x00001f00 280 #define GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT 8 281 #define GEN8_RT_DW0_ALPHA_FUNC__MASK 0x000000e0 282 #define GEN8_RT_DW0_ALPHA_FUNC__SHIFT 5 283 #define GEN8_RT_DW0_WRITE_DISABLES__MASK 0x0000000f 284 #define GEN8_RT_DW0_WRITE_DISABLES__SHIFT 0 285 #define GEN8_RT_DW0_WRITE_DISABLES_A (0x1 << 3) 286 #define GEN8_RT_DW0_WRITE_DISABLES_R (0x1 << 2) 287 #define GEN8_RT_DW0_WRITE_DISABLES_G (0x1 << 1) 288 #define GEN8_RT_DW0_WRITE_DISABLES_B (0x1 << 0) 289 290 #define GEN8_RT_DW1_LOGICOP_ENABLE (0x1 << 31) 291 #define GEN8_RT_DW1_LOGICOP_FUNC__MASK 0x78000000 292 #define GEN8_RT_DW1_LOGICOP_FUNC__SHIFT 27 293 #define GEN8_RT_DW1_PRE_BLEND_CLAMP_SRC_ONLY (0x1 << 4) 294 #define GEN8_RT_DW1_COLORCLAMP__MASK 0x0000000c 295 #define GEN8_RT_DW1_COLORCLAMP__SHIFT 2 296 #define GEN8_RT_DW1_COLORCLAMP_UNORM (0x0 << 2) 297 #define GEN8_RT_DW1_COLORCLAMP_SNORM (0x1 << 2) 298 #define GEN8_RT_DW1_COLORCLAMP_RTFORMAT (0x2 << 2) 299 #define GEN8_RT_DW1_PRE_BLEND_CLAMP (0x1 << 1) 300 #define GEN8_RT_DW1_POST_BLEND_CLAMP (0x1 << 0) 301 302 #define GEN6_CLIP_VIEWPORT__SIZE 64 303 304 305 306 307 308 309 #define GEN6_SF_VIEWPORT__SIZE 128 310 311 312 313 314 315 316 317 318 319 320 #define GEN7_SF_CLIP_VIEWPORT__SIZE 256 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 #define GEN6_CC_VIEWPORT__SIZE 32 346 347 348 349 350 #define GEN6_SCISSOR_RECT__SIZE 32 351 352 353 #define GEN6_SCISSOR_DW0_MIN_Y__MASK 0xffff0000 354 #define GEN6_SCISSOR_DW0_MIN_Y__SHIFT 16 355 #define GEN6_SCISSOR_DW0_MIN_X__MASK 0x0000ffff 356 #define GEN6_SCISSOR_DW0_MIN_X__SHIFT 0 357 358 #define GEN6_SCISSOR_DW1_MAX_Y__MASK 0xffff0000 359 #define GEN6_SCISSOR_DW1_MAX_Y__SHIFT 16 360 #define GEN6_SCISSOR_DW1_MAX_X__MASK 0x0000ffff 361 #define GEN6_SCISSOR_DW1_MAX_X__SHIFT 0 362 363 #define GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE 20 364 365 #define GEN6_BORDER_COLOR_DW0_A__MASK 0xff000000 366 #define GEN6_BORDER_COLOR_DW0_A__SHIFT 24 367 #define GEN6_BORDER_COLOR_DW0_B__MASK 0x00ff0000 368 #define GEN6_BORDER_COLOR_DW0_B__SHIFT 16 369 #define GEN6_BORDER_COLOR_DW0_G__MASK 0x0000ff00 370 #define GEN6_BORDER_COLOR_DW0_G__SHIFT 8 371 #define GEN6_BORDER_COLOR_DW0_R__MASK 0x000000ff 372 #define GEN6_BORDER_COLOR_DW0_R__SHIFT 0 373 374 375 376 377 378 #define GEN6_BORDER_COLOR_DW5_G__MASK 0xffff0000 379 #define GEN6_BORDER_COLOR_DW5_G__SHIFT 16 380 #define GEN6_BORDER_COLOR_DW5_R__MASK 0x0000ffff 381 #define GEN6_BORDER_COLOR_DW5_R__SHIFT 0 382 383 #define GEN6_BORDER_COLOR_DW6_A__MASK 0xffff0000 384 #define GEN6_BORDER_COLOR_DW6_A__SHIFT 16 385 #define GEN6_BORDER_COLOR_DW6_B__MASK 0x0000ffff 386 #define GEN6_BORDER_COLOR_DW6_B__SHIFT 0 387 388 #define GEN6_BORDER_COLOR_DW7_G__MASK 0xffff0000 389 #define GEN6_BORDER_COLOR_DW7_G__SHIFT 16 390 #define GEN6_BORDER_COLOR_DW7_R__MASK 0x0000ffff 391 #define GEN6_BORDER_COLOR_DW7_R__SHIFT 0 392 393 #define GEN6_BORDER_COLOR_DW8_A__MASK 0xffff0000 394 #define GEN6_BORDER_COLOR_DW8_A__SHIFT 16 395 #define GEN6_BORDER_COLOR_DW8_B__MASK 0x0000ffff 396 #define GEN6_BORDER_COLOR_DW8_B__SHIFT 0 397 398 #define GEN6_BORDER_COLOR_DW9_G__MASK 0xffff0000 399 #define GEN6_BORDER_COLOR_DW9_G__SHIFT 16 400 #define GEN6_BORDER_COLOR_DW9_R__MASK 0x0000ffff 401 #define GEN6_BORDER_COLOR_DW9_R__SHIFT 0 402 403 #define GEN6_BORDER_COLOR_DW10_A__MASK 0xffff0000 404 #define GEN6_BORDER_COLOR_DW10_A__SHIFT 16 405 #define GEN6_BORDER_COLOR_DW10_B__MASK 0x0000ffff 406 #define GEN6_BORDER_COLOR_DW10_B__SHIFT 0 407 408 #define GEN6_BORDER_COLOR_DW11_A__MASK 0xff000000 409 #define GEN6_BORDER_COLOR_DW11_A__SHIFT 24 410 #define GEN6_BORDER_COLOR_DW11_B__MASK 0x00ff0000 411 #define GEN6_BORDER_COLOR_DW11_B__SHIFT 16 412 #define GEN6_BORDER_COLOR_DW11_G__MASK 0x0000ff00 413 #define GEN6_BORDER_COLOR_DW11_G__SHIFT 8 414 #define GEN6_BORDER_COLOR_DW11_R__MASK 0x000000ff 415 #define GEN6_BORDER_COLOR_DW11_R__SHIFT 0 416 417 418 419 420 421 422 423 424 #define GEN6_SAMPLER_STATE__SIZE 4 425 426 #define GEN6_SAMPLER_DW0_DISABLE (0x1 << 31) 427 #define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK 0x20000000 428 #define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT 29 429 #define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL (0x0 << 29) 430 #define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9 (0x1 << 29) 431 #define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28) 432 #define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL (0x1 << 27) 433 #define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__MASK 0x18000000 434 #define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__SHIFT 27 435 #define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_NONE (0x0 << 27) 436 #define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_OGL (0x2 << 27) 437 #define GEN6_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000 438 #define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT 22 439 #define GEN6_SAMPLER_DW0_BASE_LOD__RADIX 1 440 #define GEN6_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000 441 #define GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT 20 442 #define GEN6_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000 443 #define GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT 17 444 #define GEN6_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000 445 #define GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT 14 446 #define GEN6_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ff8 447 #define GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT 3 448 #define GEN6_SAMPLER_DW0_LOD_BIAS__RADIX 6 449 #define GEN6_SAMPLER_DW0_SHADOW_FUNC__MASK 0x00000007 450 #define GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT 0 451 #define GEN7_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ffe 452 #define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT 1 453 #define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX 8 454 #define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK 0x00000001 455 #define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT 0 456 #define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY 0x0 457 #define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA 0x1 458 459 #define GEN6_SAMPLER_DW1_MIN_LOD__MASK 0xffc00000 460 #define GEN6_SAMPLER_DW1_MIN_LOD__SHIFT 22 461 #define GEN6_SAMPLER_DW1_MIN_LOD__RADIX 6 462 #define GEN6_SAMPLER_DW1_MAX_LOD__MASK 0x003ff000 463 #define GEN6_SAMPLER_DW1_MAX_LOD__SHIFT 12 464 #define GEN6_SAMPLER_DW1_MAX_LOD__RADIX 6 465 #define GEN6_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000200 466 #define GEN6_SAMPLER_DW1_CUBECTRLMODE__SHIFT 9 467 #define GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED (0x0 << 9) 468 #define GEN6_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE (0x1 << 9) 469 #define GEN6_SAMPLER_DW1_U_WRAP__MASK 0x000001c0 470 #define GEN6_SAMPLER_DW1_U_WRAP__SHIFT 6 471 #define GEN6_SAMPLER_DW1_V_WRAP__MASK 0x00000038 472 #define GEN6_SAMPLER_DW1_V_WRAP__SHIFT 3 473 #define GEN6_SAMPLER_DW1_R_WRAP__MASK 0x00000007 474 #define GEN6_SAMPLER_DW1_R_WRAP__SHIFT 0 475 476 #define GEN7_SAMPLER_DW1_MIN_LOD__MASK 0xfff00000 477 #define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT 20 478 #define GEN7_SAMPLER_DW1_MIN_LOD__RADIX 8 479 #define GEN7_SAMPLER_DW1_MAX_LOD__MASK 0x000fff00 480 #define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT 8 481 #define GEN7_SAMPLER_DW1_MAX_LOD__RADIX 8 482 #define GEN8_SAMPLER_DW1_CHROMAKEY_ENABLE (0x1 << 7) 483 #define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__MASK 0x00000060 484 #define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__SHIFT 5 485 #define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__MASK 0x00000010 486 #define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__SHIFT 4 487 #define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK 0x0000000e 488 #define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT 1 489 #define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000001 490 #define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT 0 491 #define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED 0x0 492 #define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE 0x1 493 494 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0 495 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5 496 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5 497 498 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__MASK 0x00ffffc0 499 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHIFT 6 500 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHR 6 501 #define GEN8_SAMPLER_DW2_LOD_CLAMP_MAG_MODE (0x1 << 0) 502 503 #define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25) 504 #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000 505 #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23 506 #define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000 507 #define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22 508 #define GEN6_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000 509 #define GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT 19 510 #define GEN6_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18) 511 #define GEN6_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17) 512 #define GEN6_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16) 513 #define GEN6_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15) 514 #define GEN6_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14) 515 #define GEN6_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13) 516 #define GEN7_SAMPLER_DW3_TRIQUAL__MASK 0x00001800 517 #define GEN7_SAMPLER_DW3_TRIQUAL__SHIFT 11 518 #define GEN7_SAMPLER_DW3_TRIQUAL_FULL (0x0 << 11) 519 #define GEN75_SAMPLER_DW3_TRIQUAL_HIGH (0x1 << 11) 520 #define GEN7_SAMPLER_DW3_TRIQUAL_MED (0x2 << 11) 521 #define GEN7_SAMPLER_DW3_TRIQUAL_LOW (0x3 << 11) 522 #define GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 10) 523 #define GEN7_SAMPLER_DW3_U_WRAP__MASK 0x000001c0 524 #define GEN7_SAMPLER_DW3_U_WRAP__SHIFT 6 525 #define GEN7_SAMPLER_DW3_V_WRAP__MASK 0x00000038 526 #define GEN7_SAMPLER_DW3_V_WRAP__SHIFT 3 527 #define GEN7_SAMPLER_DW3_R_WRAP__MASK 0x00000007 528 #define GEN7_SAMPLER_DW3_R_WRAP__SHIFT 0 529 #define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 0) 530 531 532 #endif /* GEN_RENDER_DYNAMIC_XML */ 533