1 #ifndef GEN_RENDER_SURFACE_XML 2 #define GEN_RENDER_SURFACE_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 https://github.com/olvaffe/envytools/ 8 git clone https://github.com/olvaffe/envytools.git 9 10 Copyright (C) 2014-2015 by the following authors: 11 - Chia-I Wu <olvaffe@gmail.com> (olv) 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice (including the 22 next paragraph) shall be included in all copies or substantial 23 portions of the Software. 24 25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 enum gen_surface_format { 36 GEN6_FORMAT_R32G32B32A32_FLOAT = 0x0, 37 GEN6_FORMAT_R32G32B32A32_SINT = 0x1, 38 GEN6_FORMAT_R32G32B32A32_UINT = 0x2, 39 GEN6_FORMAT_R32G32B32A32_UNORM = 0x3, 40 GEN6_FORMAT_R32G32B32A32_SNORM = 0x4, 41 GEN6_FORMAT_R64G64_FLOAT = 0x5, 42 GEN6_FORMAT_R32G32B32X32_FLOAT = 0x6, 43 GEN6_FORMAT_R32G32B32A32_SSCALED = 0x7, 44 GEN6_FORMAT_R32G32B32A32_USCALED = 0x8, 45 GEN6_FORMAT_R32G32B32A32_SFIXED = 0x20, 46 GEN6_FORMAT_R64G64_PASSTHRU = 0x21, 47 GEN6_FORMAT_R32G32B32_FLOAT = 0x40, 48 GEN6_FORMAT_R32G32B32_SINT = 0x41, 49 GEN6_FORMAT_R32G32B32_UINT = 0x42, 50 GEN6_FORMAT_R32G32B32_UNORM = 0x43, 51 GEN6_FORMAT_R32G32B32_SNORM = 0x44, 52 GEN6_FORMAT_R32G32B32_SSCALED = 0x45, 53 GEN6_FORMAT_R32G32B32_USCALED = 0x46, 54 GEN6_FORMAT_R32G32B32_SFIXED = 0x50, 55 GEN6_FORMAT_R16G16B16A16_UNORM = 0x80, 56 GEN6_FORMAT_R16G16B16A16_SNORM = 0x81, 57 GEN6_FORMAT_R16G16B16A16_SINT = 0x82, 58 GEN6_FORMAT_R16G16B16A16_UINT = 0x83, 59 GEN6_FORMAT_R16G16B16A16_FLOAT = 0x84, 60 GEN6_FORMAT_R32G32_FLOAT = 0x85, 61 GEN6_FORMAT_R32G32_SINT = 0x86, 62 GEN6_FORMAT_R32G32_UINT = 0x87, 63 GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS = 0x88, 64 GEN6_FORMAT_X32_TYPELESS_G8X24_UINT = 0x89, 65 GEN6_FORMAT_L32A32_FLOAT = 0x8a, 66 GEN6_FORMAT_R32G32_UNORM = 0x8b, 67 GEN6_FORMAT_R32G32_SNORM = 0x8c, 68 GEN6_FORMAT_R64_FLOAT = 0x8d, 69 GEN6_FORMAT_R16G16B16X16_UNORM = 0x8e, 70 GEN6_FORMAT_R16G16B16X16_FLOAT = 0x8f, 71 GEN6_FORMAT_A32X32_FLOAT = 0x90, 72 GEN6_FORMAT_L32X32_FLOAT = 0x91, 73 GEN6_FORMAT_I32X32_FLOAT = 0x92, 74 GEN6_FORMAT_R16G16B16A16_SSCALED = 0x93, 75 GEN6_FORMAT_R16G16B16A16_USCALED = 0x94, 76 GEN6_FORMAT_R32G32_SSCALED = 0x95, 77 GEN6_FORMAT_R32G32_USCALED = 0x96, 78 GEN6_FORMAT_R32G32_SFIXED = 0xa0, 79 GEN6_FORMAT_R64_PASSTHRU = 0xa1, 80 GEN6_FORMAT_B8G8R8A8_UNORM = 0xc0, 81 GEN6_FORMAT_B8G8R8A8_UNORM_SRGB = 0xc1, 82 GEN6_FORMAT_R10G10B10A2_UNORM = 0xc2, 83 GEN6_FORMAT_R10G10B10A2_UNORM_SRGB = 0xc3, 84 GEN6_FORMAT_R10G10B10A2_UINT = 0xc4, 85 GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM = 0xc5, 86 GEN6_FORMAT_R8G8B8A8_UNORM = 0xc7, 87 GEN6_FORMAT_R8G8B8A8_UNORM_SRGB = 0xc8, 88 GEN6_FORMAT_R8G8B8A8_SNORM = 0xc9, 89 GEN6_FORMAT_R8G8B8A8_SINT = 0xca, 90 GEN6_FORMAT_R8G8B8A8_UINT = 0xcb, 91 GEN6_FORMAT_R16G16_UNORM = 0xcc, 92 GEN6_FORMAT_R16G16_SNORM = 0xcd, 93 GEN6_FORMAT_R16G16_SINT = 0xce, 94 GEN6_FORMAT_R16G16_UINT = 0xcf, 95 GEN6_FORMAT_R16G16_FLOAT = 0xd0, 96 GEN6_FORMAT_B10G10R10A2_UNORM = 0xd1, 97 GEN6_FORMAT_B10G10R10A2_UNORM_SRGB = 0xd2, 98 GEN6_FORMAT_R11G11B10_FLOAT = 0xd3, 99 GEN6_FORMAT_R32_SINT = 0xd6, 100 GEN6_FORMAT_R32_UINT = 0xd7, 101 GEN6_FORMAT_R32_FLOAT = 0xd8, 102 GEN6_FORMAT_R24_UNORM_X8_TYPELESS = 0xd9, 103 GEN6_FORMAT_X24_TYPELESS_G8_UINT = 0xda, 104 GEN6_FORMAT_L32_UNORM = 0xdd, 105 GEN6_FORMAT_A32_UNORM = 0xde, 106 GEN6_FORMAT_L16A16_UNORM = 0xdf, 107 GEN6_FORMAT_I24X8_UNORM = 0xe0, 108 GEN6_FORMAT_L24X8_UNORM = 0xe1, 109 GEN6_FORMAT_A24X8_UNORM = 0xe2, 110 GEN6_FORMAT_I32_FLOAT = 0xe3, 111 GEN6_FORMAT_L32_FLOAT = 0xe4, 112 GEN6_FORMAT_A32_FLOAT = 0xe5, 113 GEN6_FORMAT_X8B8_UNORM_G8R8_SNORM = 0xe6, 114 GEN6_FORMAT_A8X8_UNORM_G8R8_SNORM = 0xe7, 115 GEN6_FORMAT_B8X8_UNORM_G8R8_SNORM = 0xe8, 116 GEN6_FORMAT_B8G8R8X8_UNORM = 0xe9, 117 GEN6_FORMAT_B8G8R8X8_UNORM_SRGB = 0xea, 118 GEN6_FORMAT_R8G8B8X8_UNORM = 0xeb, 119 GEN6_FORMAT_R8G8B8X8_UNORM_SRGB = 0xec, 120 GEN6_FORMAT_R9G9B9E5_SHAREDEXP = 0xed, 121 GEN6_FORMAT_B10G10R10X2_UNORM = 0xee, 122 GEN6_FORMAT_L16A16_FLOAT = 0xf0, 123 GEN6_FORMAT_R32_UNORM = 0xf1, 124 GEN6_FORMAT_R32_SNORM = 0xf2, 125 GEN6_FORMAT_R10G10B10X2_USCALED = 0xf3, 126 GEN6_FORMAT_R8G8B8A8_SSCALED = 0xf4, 127 GEN6_FORMAT_R8G8B8A8_USCALED = 0xf5, 128 GEN6_FORMAT_R16G16_SSCALED = 0xf6, 129 GEN6_FORMAT_R16G16_USCALED = 0xf7, 130 GEN6_FORMAT_R32_SSCALED = 0xf8, 131 GEN6_FORMAT_R32_USCALED = 0xf9, 132 GEN6_FORMAT_B5G6R5_UNORM = 0x100, 133 GEN6_FORMAT_B5G6R5_UNORM_SRGB = 0x101, 134 GEN6_FORMAT_B5G5R5A1_UNORM = 0x102, 135 GEN6_FORMAT_B5G5R5A1_UNORM_SRGB = 0x103, 136 GEN6_FORMAT_B4G4R4A4_UNORM = 0x104, 137 GEN6_FORMAT_B4G4R4A4_UNORM_SRGB = 0x105, 138 GEN6_FORMAT_R8G8_UNORM = 0x106, 139 GEN6_FORMAT_R8G8_SNORM = 0x107, 140 GEN6_FORMAT_R8G8_SINT = 0x108, 141 GEN6_FORMAT_R8G8_UINT = 0x109, 142 GEN6_FORMAT_R16_UNORM = 0x10a, 143 GEN6_FORMAT_R16_SNORM = 0x10b, 144 GEN6_FORMAT_R16_SINT = 0x10c, 145 GEN6_FORMAT_R16_UINT = 0x10d, 146 GEN6_FORMAT_R16_FLOAT = 0x10e, 147 GEN6_FORMAT_A8P8_UNORM_PALETTE0 = 0x10f, 148 GEN6_FORMAT_A8P8_UNORM_PALETTE1 = 0x110, 149 GEN6_FORMAT_I16_UNORM = 0x111, 150 GEN6_FORMAT_L16_UNORM = 0x112, 151 GEN6_FORMAT_A16_UNORM = 0x113, 152 GEN6_FORMAT_L8A8_UNORM = 0x114, 153 GEN6_FORMAT_I16_FLOAT = 0x115, 154 GEN6_FORMAT_L16_FLOAT = 0x116, 155 GEN6_FORMAT_A16_FLOAT = 0x117, 156 GEN6_FORMAT_L8A8_UNORM_SRGB = 0x118, 157 GEN6_FORMAT_R5G5_SNORM_B6_UNORM = 0x119, 158 GEN6_FORMAT_B5G5R5X1_UNORM = 0x11a, 159 GEN6_FORMAT_B5G5R5X1_UNORM_SRGB = 0x11b, 160 GEN6_FORMAT_R8G8_SSCALED = 0x11c, 161 GEN6_FORMAT_R8G8_USCALED = 0x11d, 162 GEN6_FORMAT_R16_SSCALED = 0x11e, 163 GEN6_FORMAT_R16_USCALED = 0x11f, 164 GEN6_FORMAT_P8A8_UNORM_PALETTE0 = 0x122, 165 GEN6_FORMAT_P8A8_UNORM_PALETTE1 = 0x123, 166 GEN6_FORMAT_A1B5G5R5_UNORM = 0x124, 167 GEN6_FORMAT_A4B4G4R4_UNORM = 0x125, 168 GEN6_FORMAT_L8A8_UINT = 0x126, 169 GEN6_FORMAT_L8A8_SINT = 0x127, 170 GEN6_FORMAT_R8_UNORM = 0x140, 171 GEN6_FORMAT_R8_SNORM = 0x141, 172 GEN6_FORMAT_R8_SINT = 0x142, 173 GEN6_FORMAT_R8_UINT = 0x143, 174 GEN6_FORMAT_A8_UNORM = 0x144, 175 GEN6_FORMAT_I8_UNORM = 0x145, 176 GEN6_FORMAT_L8_UNORM = 0x146, 177 GEN6_FORMAT_P4A4_UNORM_PALETTE0 = 0x147, 178 GEN6_FORMAT_A4P4_UNORM_PALETTE0 = 0x148, 179 GEN6_FORMAT_R8_SSCALED = 0x149, 180 GEN6_FORMAT_R8_USCALED = 0x14a, 181 GEN6_FORMAT_P8_UNORM_PALETTE0 = 0x14b, 182 GEN6_FORMAT_L8_UNORM_SRGB = 0x14c, 183 GEN6_FORMAT_P8_UNORM_PALETTE1 = 0x14d, 184 GEN6_FORMAT_P4A4_UNORM_PALETTE1 = 0x14e, 185 GEN6_FORMAT_A4P4_UNORM_PALETTE1 = 0x14f, 186 GEN6_FORMAT_Y8_UNORM = 0x150, 187 GEN6_FORMAT_L8_UINT = 0x152, 188 GEN6_FORMAT_L8_SINT = 0x153, 189 GEN6_FORMAT_I8_UINT = 0x154, 190 GEN6_FORMAT_I8_SINT = 0x155, 191 GEN6_FORMAT_DXT1_RGB_SRGB = 0x180, 192 GEN6_FORMAT_R1_UNORM = 0x181, 193 GEN6_FORMAT_YCRCB_NORMAL = 0x182, 194 GEN6_FORMAT_YCRCB_SWAPUVY = 0x183, 195 GEN6_FORMAT_P2_UNORM_PALETTE0 = 0x184, 196 GEN6_FORMAT_P2_UNORM_PALETTE1 = 0x185, 197 GEN6_FORMAT_BC1_UNORM = 0x186, 198 GEN6_FORMAT_BC2_UNORM = 0x187, 199 GEN6_FORMAT_BC3_UNORM = 0x188, 200 GEN6_FORMAT_BC4_UNORM = 0x189, 201 GEN6_FORMAT_BC5_UNORM = 0x18a, 202 GEN6_FORMAT_BC1_UNORM_SRGB = 0x18b, 203 GEN6_FORMAT_BC2_UNORM_SRGB = 0x18c, 204 GEN6_FORMAT_BC3_UNORM_SRGB = 0x18d, 205 GEN6_FORMAT_MONO8 = 0x18e, 206 GEN6_FORMAT_YCRCB_SWAPUV = 0x18f, 207 GEN6_FORMAT_YCRCB_SWAPY = 0x190, 208 GEN6_FORMAT_DXT1_RGB = 0x191, 209 GEN6_FORMAT_FXT1 = 0x192, 210 GEN6_FORMAT_R8G8B8_UNORM = 0x193, 211 GEN6_FORMAT_R8G8B8_SNORM = 0x194, 212 GEN6_FORMAT_R8G8B8_SSCALED = 0x195, 213 GEN6_FORMAT_R8G8B8_USCALED = 0x196, 214 GEN6_FORMAT_R64G64B64A64_FLOAT = 0x197, 215 GEN6_FORMAT_R64G64B64_FLOAT = 0x198, 216 GEN6_FORMAT_BC4_SNORM = 0x199, 217 GEN6_FORMAT_BC5_SNORM = 0x19a, 218 GEN6_FORMAT_R16G16B16_FLOAT = 0x19b, 219 GEN6_FORMAT_R16G16B16_UNORM = 0x19c, 220 GEN6_FORMAT_R16G16B16_SNORM = 0x19d, 221 GEN6_FORMAT_R16G16B16_SSCALED = 0x19e, 222 GEN6_FORMAT_R16G16B16_USCALED = 0x19f, 223 GEN6_FORMAT_BC6H_SF16 = 0x1a1, 224 GEN6_FORMAT_BC7_UNORM = 0x1a2, 225 GEN6_FORMAT_BC7_UNORM_SRGB = 0x1a3, 226 GEN6_FORMAT_BC6H_UF16 = 0x1a4, 227 GEN6_FORMAT_PLANAR_420_8 = 0x1a5, 228 GEN6_FORMAT_R8G8B8_UNORM_SRGB = 0x1a8, 229 GEN6_FORMAT_ETC1_RGB8 = 0x1a9, 230 GEN6_FORMAT_ETC2_RGB8 = 0x1aa, 231 GEN6_FORMAT_EAC_R11 = 0x1ab, 232 GEN6_FORMAT_EAC_RG11 = 0x1ac, 233 GEN6_FORMAT_EAC_SIGNED_R11 = 0x1ad, 234 GEN6_FORMAT_EAC_SIGNED_RG11 = 0x1ae, 235 GEN6_FORMAT_ETC2_SRGB8 = 0x1af, 236 GEN6_FORMAT_R16G16B16_UINT = 0x1b0, 237 GEN6_FORMAT_R16G16B16_SINT = 0x1b1, 238 GEN6_FORMAT_R32_SFIXED = 0x1b2, 239 GEN6_FORMAT_R10G10B10A2_SNORM = 0x1b3, 240 GEN6_FORMAT_R10G10B10A2_USCALED = 0x1b4, 241 GEN6_FORMAT_R10G10B10A2_SSCALED = 0x1b5, 242 GEN6_FORMAT_R10G10B10A2_SINT = 0x1b6, 243 GEN6_FORMAT_B10G10R10A2_SNORM = 0x1b7, 244 GEN6_FORMAT_B10G10R10A2_USCALED = 0x1b8, 245 GEN6_FORMAT_B10G10R10A2_SSCALED = 0x1b9, 246 GEN6_FORMAT_B10G10R10A2_UINT = 0x1ba, 247 GEN6_FORMAT_B10G10R10A2_SINT = 0x1bb, 248 GEN6_FORMAT_R64G64B64A64_PASSTHRU = 0x1bc, 249 GEN6_FORMAT_R64G64B64_PASSTHRU = 0x1bd, 250 GEN6_FORMAT_ETC2_RGB8_PTA = 0x1c0, 251 GEN6_FORMAT_ETC2_SRGB8_PTA = 0x1c1, 252 GEN6_FORMAT_ETC2_EAC_RGBA8 = 0x1c2, 253 GEN6_FORMAT_ETC2_EAC_SRGB8_A8 = 0x1c3, 254 GEN6_FORMAT_R8G8B8_UINT = 0x1c8, 255 GEN6_FORMAT_R8G8B8_SINT = 0x1c9, 256 GEN6_FORMAT_RAW = 0x1ff, 257 }; 258 259 enum gen_surface_type { 260 GEN6_SURFTYPE_1D = 0x0, 261 GEN6_SURFTYPE_2D = 0x1, 262 GEN6_SURFTYPE_3D = 0x2, 263 GEN6_SURFTYPE_CUBE = 0x3, 264 GEN6_SURFTYPE_BUFFER = 0x4, 265 GEN7_SURFTYPE_STRBUF = 0x5, 266 GEN6_SURFTYPE_NULL = 0x7, 267 }; 268 269 enum gen_surface_tiling { 270 GEN6_TILING_NONE = 0x0, 271 GEN8_TILING_W = 0x1, 272 GEN6_TILING_X = 0x2, 273 GEN6_TILING_Y = 0x3, 274 }; 275 276 enum gen_surface_clear_color { 277 GEN7_CLEAR_COLOR_ZERO = 0x0, 278 GEN7_CLEAR_COLOR_ONE = 0x1, 279 }; 280 281 enum gen_surface_scs { 282 GEN75_SCS_ZERO = 0x0, 283 GEN75_SCS_ONE = 0x1, 284 GEN75_SCS_RED = 0x4, 285 GEN75_SCS_GREEN = 0x5, 286 GEN75_SCS_BLUE = 0x6, 287 GEN75_SCS_ALPHA = 0x7, 288 }; 289 290 #define GEN6_SURFACE_STATE__SIZE 16 291 292 #define GEN6_SURFACE_DW0_TYPE__MASK 0xe0000000 293 #define GEN6_SURFACE_DW0_TYPE__SHIFT 29 294 #define GEN6_SURFACE_DW0_FORMAT__MASK 0x07fc0000 295 #define GEN6_SURFACE_DW0_FORMAT__SHIFT 18 296 #define GEN6_SURFACE_DW0_VSTRIDE (0x1 << 12) 297 #define GEN6_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11) 298 #define GEN6_SURFACE_DW0_MIPLAYOUT__MASK 0x00000400 299 #define GEN6_SURFACE_DW0_MIPLAYOUT__SHIFT 10 300 #define GEN6_SURFACE_DW0_MIPLAYOUT_BELOW (0x0 << 10) 301 #define GEN6_SURFACE_DW0_MIPLAYOUT_RIGHT (0x1 << 10) 302 #define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__MASK 0x00000200 303 #define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__SHIFT 9 304 #define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_REPLICATE (0x0 << 9) 305 #define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE (0x1 << 9) 306 #define GEN6_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8) 307 #define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0 308 #define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6 309 #define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f 310 #define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0 311 312 313 #define GEN6_SURFACE_DW2_HEIGHT__MASK 0xfff80000 314 #define GEN6_SURFACE_DW2_HEIGHT__SHIFT 19 315 #define GEN6_SURFACE_DW2_WIDTH__MASK 0x0007ffc0 316 #define GEN6_SURFACE_DW2_WIDTH__SHIFT 6 317 #define GEN6_SURFACE_DW2_MIP_COUNT_LOD__MASK 0x0000003c 318 #define GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT 2 319 #define GEN6_SURFACE_DW2_RTROTATE__MASK 0x00000003 320 #define GEN6_SURFACE_DW2_RTROTATE__SHIFT 0 321 #define GEN6_SURFACE_DW2_RTROTATE_0DEG 0x0 322 #define GEN6_SURFACE_DW2_RTROTATE_90DEG 0x1 323 #define GEN6_SURFACE_DW2_RTROTATE_270DEG 0x3 324 325 #define GEN6_SURFACE_DW3_DEPTH__MASK 0xffe00000 326 #define GEN6_SURFACE_DW3_DEPTH__SHIFT 21 327 #define GEN6_SURFACE_DW3_PITCH__MASK 0x000ffff8 328 #define GEN6_SURFACE_DW3_PITCH__SHIFT 3 329 #define GEN6_SURFACE_DW3_TILING__MASK 0x00000003 330 #define GEN6_SURFACE_DW3_TILING__SHIFT 0 331 332 #define GEN6_SURFACE_DW4_MIN_LOD__MASK 0xf0000000 333 #define GEN6_SURFACE_DW4_MIN_LOD__SHIFT 28 334 #define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x0ffe0000 335 #define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 17 336 #define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0001ff00 337 #define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 8 338 #define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000070 339 #define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 4 340 #define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 4) 341 #define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 4) 342 #define GEN6_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007 343 #define GEN6_SURFACE_DW4_MSPOS_INDEX__SHIFT 0 344 345 #define GEN6_SURFACE_DW5_X_OFFSET__MASK 0xfe000000 346 #define GEN6_SURFACE_DW5_X_OFFSET__SHIFT 25 347 #define GEN6_SURFACE_DW5_X_OFFSET__SHR 2 348 #define GEN6_SURFACE_DW5_VALIGN__MASK 0x01000000 349 #define GEN6_SURFACE_DW5_VALIGN__SHIFT 24 350 #define GEN6_SURFACE_DW5_VALIGN_2 (0x0 << 24) 351 #define GEN6_SURFACE_DW5_VALIGN_4 (0x1 << 24) 352 #define GEN6_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000 353 #define GEN6_SURFACE_DW5_Y_OFFSET__SHIFT 20 354 #define GEN6_SURFACE_DW5_Y_OFFSET__SHR 1 355 #define GEN6_SURFACE_DW5_MOCS__MASK 0x000f0000 356 #define GEN6_SURFACE_DW5_MOCS__SHIFT 16 357 358 359 #define GEN7_SURFACE_DW0_TYPE__MASK 0xe0000000 360 #define GEN7_SURFACE_DW0_TYPE__SHIFT 29 361 #define GEN7_SURFACE_DW0_IS_ARRAY (0x1 << 28) 362 #define GEN7_SURFACE_DW0_FORMAT__MASK 0x07fc0000 363 #define GEN7_SURFACE_DW0_FORMAT__SHIFT 18 364 #define GEN7_SURFACE_DW0_VALIGN__MASK 0x00030000 365 #define GEN7_SURFACE_DW0_VALIGN__SHIFT 16 366 #define GEN7_SURFACE_DW0_VALIGN_2 (0x0 << 16) 367 #define GEN7_SURFACE_DW0_VALIGN_4 (0x1 << 16) 368 #define GEN8_SURFACE_DW0_VALIGN_8 (0x2 << 16) 369 #define GEN8_SURFACE_DW0_VALIGN_16 (0x3 << 16) 370 #define GEN7_SURFACE_DW0_HALIGN__MASK 0x00008000 371 #define GEN7_SURFACE_DW0_HALIGN__SHIFT 15 372 #define GEN7_SURFACE_DW0_HALIGN_4 (0x0 << 15) 373 #define GEN7_SURFACE_DW0_HALIGN_8 (0x1 << 15) 374 #define GEN7_SURFACE_DW0_TILING__MASK 0x00006000 375 #define GEN7_SURFACE_DW0_TILING__SHIFT 13 376 #define GEN7_SURFACE_DW0_VSTRIDE (0x1 << 12) 377 #define GEN7_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11) 378 #define GEN7_SURFACE_DW0_ARYSPC__MASK 0x00000400 379 #define GEN7_SURFACE_DW0_ARYSPC__SHIFT 10 380 #define GEN7_SURFACE_DW0_ARYSPC_FULL (0x0 << 10) 381 #define GEN7_SURFACE_DW0_ARYSPC_LOD0 (0x1 << 10) 382 #define GEN8_SURFACE_DW0_HALIGN__MASK 0x0000c000 383 #define GEN8_SURFACE_DW0_HALIGN__SHIFT 14 384 #define GEN8_SURFACE_DW0_HALIGN_4 (0x1 << 14) 385 #define GEN8_SURFACE_DW0_HALIGN_8 (0x2 << 14) 386 #define GEN8_SURFACE_DW0_HALIGN_16 (0x3 << 14) 387 #define GEN8_SURFACE_DW0_TILING__MASK 0x00003000 388 #define GEN8_SURFACE_DW0_TILING__SHIFT 12 389 #define GEN8_SURFACE_DW0_VSTRIDE (0x1 << 11) 390 #define GEN8_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 10) 391 #define GEN8_SURFACE_DW0_SAMPLER_L2_BYPASS_DISABLE (0x1 << 9) 392 #define GEN7_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8) 393 #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0 394 #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6 395 #define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f 396 #define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0 397 398 399 #define GEN8_SURFACE_DW1_MOCS__MASK 0x7f000000 400 #define GEN8_SURFACE_DW1_MOCS__SHIFT 24 401 #define GEN8_SURFACE_DW1_BASE_LOD__MASK 0x00f80000 402 #define GEN8_SURFACE_DW1_BASE_LOD__SHIFT 19 403 #define GEN8_SURFACE_DW1_QPITCH__MASK 0x00007fff 404 #define GEN8_SURFACE_DW1_QPITCH__SHIFT 0 405 #define GEN8_SURFACE_DW1_QPITCH__SHR 2 406 407 #define GEN7_SURFACE_DW2_HEIGHT__MASK 0x3fff0000 408 #define GEN7_SURFACE_DW2_HEIGHT__SHIFT 16 409 #define GEN7_SURFACE_DW2_WIDTH__MASK 0x00003fff 410 #define GEN7_SURFACE_DW2_WIDTH__SHIFT 0 411 412 #define GEN7_SURFACE_DW3_DEPTH__MASK 0xffe00000 413 #define GEN7_SURFACE_DW3_DEPTH__SHIFT 21 414 #define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__MASK 0x001c0000 415 #define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT 18 416 #define GEN7_SURFACE_DW3_PITCH__MASK 0x0003ffff 417 #define GEN7_SURFACE_DW3_PITCH__SHIFT 0 418 419 #define GEN7_SURFACE_DW4_RTROTATE__MASK 0x60000000 420 #define GEN7_SURFACE_DW4_RTROTATE__SHIFT 29 421 #define GEN7_SURFACE_DW4_RTROTATE_0DEG (0x0 << 29) 422 #define GEN7_SURFACE_DW4_RTROTATE_90DEG (0x1 << 29) 423 #define GEN7_SURFACE_DW4_RTROTATE_270DEG (0x3 << 29) 424 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x1ffc0000 425 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 18 426 #define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0003ff80 427 #define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 7 428 #define GEN7_SURFACE_DW4_MSFMT__MASK 0x00000040 429 #define GEN7_SURFACE_DW4_MSFMT__SHIFT 6 430 #define GEN7_SURFACE_DW4_MSFMT_MSS (0x0 << 6) 431 #define GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL (0x1 << 6) 432 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000038 433 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 3 434 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 3) 435 #define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_2 (0x1 << 3) 436 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 3) 437 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3) 438 #define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007 439 #define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0 440 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__MASK 0x07ffffff 441 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__SHIFT 0 442 443 #define GEN7_SURFACE_DW5_X_OFFSET__MASK 0xfe000000 444 #define GEN7_SURFACE_DW5_X_OFFSET__SHIFT 25 445 #define GEN7_SURFACE_DW5_X_OFFSET__SHR 2 446 #define GEN7_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000 447 #define GEN7_SURFACE_DW5_Y_OFFSET__SHIFT 20 448 #define GEN7_SURFACE_DW5_Y_OFFSET__SHR 1 449 #define GEN7_SURFACE_DW5_MOCS__MASK 0x000f0000 450 #define GEN7_SURFACE_DW5_MOCS__SHIFT 16 451 #define GEN8_SURFACE_DW5_Y_OFFSET__MASK 0x00e00000 452 #define GEN8_SURFACE_DW5_Y_OFFSET__SHIFT 21 453 #define GEN8_SURFACE_DW5_Y_OFFSET__SHR 1 454 #define GEN8_SURFACE_DW5_CUBE_EWA_DISABLE (0x1 << 20) 455 #define GEN8_SURFACE_DW5_COHERENCY_TYPE__MASK 0x00004000 456 #define GEN8_SURFACE_DW5_COHERENCY_TYPE__SHIFT 14 457 #define GEN8_SURFACE_DW5_COHERENCY_TYPE_GPU (0x0 << 14) 458 #define GEN8_SURFACE_DW5_COHERENCY_TYPE_IA (0x1 << 14) 459 #define GEN7_SURFACE_DW5_MIN_LOD__MASK 0x000000f0 460 #define GEN7_SURFACE_DW5_MIN_LOD__SHIFT 4 461 #define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK 0x0000000f 462 #define GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT 0 463 464 #define GEN8_SURFACE_DW6_SEPARATE_UV_ENABLE (0x1 << 31) 465 #define GEN7_SURFACE_DW6_UV_X_OFFSET__MASK 0x3fff0000 466 #define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT 16 467 #define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK 0x00003fff 468 #define GEN7_SURFACE_DW6_UV_Y_OFFSET__SHIFT 0 469 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0 470 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6 471 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6 472 #define GEN7_SURFACE_DW6_MCS_ADDR__MASK 0xfffff000 473 #define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT 12 474 #define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12 475 #define GEN8_SURFACE_DW6_AUX_QPITCH__MASK 0x7fff0000 476 #define GEN8_SURFACE_DW6_AUX_QPITCH__SHIFT 16 477 #define GEN8_SURFACE_DW6_AUX_QPITCH__SHR 2 478 #define GEN7_SURFACE_DW6_AUX_PITCH__MASK 0x00000ff8 479 #define GEN7_SURFACE_DW6_AUX_PITCH__SHIFT 3 480 #define GEN7_SURFACE_DW6_AUX__MASK 0x00000007 481 #define GEN7_SURFACE_DW6_AUX__SHIFT 0 482 #define GEN7_SURFACE_DW6_AUX_NONE 0x0 483 #define GEN7_SURFACE_DW6_AUX_MCS 0x1 484 #define GEN7_SURFACE_DW6_AUX_APPEND 0x2 485 #define GEN8_SURFACE_DW6_AUX_HIZ 0x3 486 487 #define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000 488 #define GEN7_SURFACE_DW7_CC_R__SHIFT 31 489 #define GEN7_SURFACE_DW7_CC_G__MASK 0x40000000 490 #define GEN7_SURFACE_DW7_CC_G__SHIFT 30 491 #define GEN7_SURFACE_DW7_CC_B__MASK 0x20000000 492 #define GEN7_SURFACE_DW7_CC_B__SHIFT 29 493 #define GEN7_SURFACE_DW7_CC_A__MASK 0x10000000 494 #define GEN7_SURFACE_DW7_CC_A__SHIFT 28 495 #define GEN75_SURFACE_DW7_SCS__MASK 0x0fff0000 496 #define GEN75_SURFACE_DW7_SCS__SHIFT 16 497 #define GEN75_SURFACE_DW7_SCS_R__MASK 0x0e000000 498 #define GEN75_SURFACE_DW7_SCS_R__SHIFT 25 499 #define GEN75_SURFACE_DW7_SCS_G__MASK 0x01c00000 500 #define GEN75_SURFACE_DW7_SCS_G__SHIFT 22 501 #define GEN75_SURFACE_DW7_SCS_B__MASK 0x00380000 502 #define GEN75_SURFACE_DW7_SCS_B__SHIFT 19 503 #define GEN75_SURFACE_DW7_SCS_A__MASK 0x00070000 504 #define GEN75_SURFACE_DW7_SCS_A__SHIFT 16 505 #define GEN7_SURFACE_DW7_RES_MIN_LOD__MASK 0x00000fff 506 #define GEN7_SURFACE_DW7_RES_MIN_LOD__SHIFT 0 507 508 509 510 511 #define GEN8_SURFACE_DW11_V_X_OFFSET__MASK 0x3fff0000 512 #define GEN8_SURFACE_DW11_V_X_OFFSET__SHIFT 16 513 #define GEN8_SURFACE_DW11_V_Y_OFFSET__MASK 0x00003fff 514 #define GEN8_SURFACE_DW11_V_Y_OFFSET__SHIFT 0 515 #define GEN8_SURFACE_DW11_AUX_ADDR_HI__MASK 0xffffffff 516 #define GEN8_SURFACE_DW11_AUX_ADDR_HI__SHIFT 0 517 518 519 520 521 522 #define GEN6_BINDING_TABLE_STATE__SIZE 256 523 524 #define GEN6_BINDING_TABLE_DW_ADDR__MASK 0xffffffe0 525 #define GEN6_BINDING_TABLE_DW_ADDR__SHIFT 5 526 #define GEN6_BINDING_TABLE_DW_ADDR__SHR 5 527 528 #define GEN8_BINDING_TABLE_DW_ADDR__MASK 0xffffffc0 529 #define GEN8_BINDING_TABLE_DW_ADDR__SHIFT 6 530 #define GEN8_BINDING_TABLE_DW_ADDR__SHR 6 531 532 533 #endif /* GEN_RENDER_SURFACE_XML */ 534