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1 /*
2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial portions
15  * of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26 
27 #ifndef _I915_DRM_H_
28 #define _I915_DRM_H_
29 
30 #include "drm.h"
31 
32 #if defined(__cplusplus)
33 extern "C" {
34 #endif
35 
36 /* Please note that modifications to all structs defined here are
37  * subject to backwards-compatibility constraints.
38  */
39 
40 /**
41  * DOC: uevents generated by i915 on it's device node
42  *
43  * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44  *	event from the gpu l3 cache. Additional information supplied is ROW,
45  *	BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46  *	track of these events and if a specific cache-line seems to have a
47  *	persistent error remap it with the l3 remapping tool supplied in
48  *	intel-gpu-tools.  The value supplied with the event is always 1.
49  *
50  * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51  *	hangcheck. The error detection event is a good indicator of when things
52  *	began to go badly. The value supplied with the event is a 1 upon error
53  *	detection, and a 0 upon reset completion, signifying no more error
54  *	exists. NOTE: Disabling hangcheck or reset via module parameter will
55  *	cause the related events to not be seen.
56  *
57  * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58  *	the GPU. The value supplied with the event is always 1. NOTE: Disable
59  *	reset via module parameter will cause this event to not be seen.
60  */
61 #define I915_L3_PARITY_UEVENT		"L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT		"ERROR"
63 #define I915_RESET_UEVENT		"RESET"
64 
65 /*
66  * MOCS indexes used for GPU surfaces, defining the cacheability of the
67  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
68  */
69 enum i915_mocs_table_index {
70 	/*
71 	 * Not cached anywhere, coherency between CPU and GPU accesses is
72 	 * guaranteed.
73 	 */
74 	I915_MOCS_UNCACHED,
75 	/*
76 	 * Cacheability and coherency controlled by the kernel automatically
77 	 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
78 	 * usage of the surface (used for display scanout or not).
79 	 */
80 	I915_MOCS_PTE,
81 	/*
82 	 * Cached in all GPU caches available on the platform.
83 	 * Coherency between CPU and GPU accesses to the surface is not
84 	 * guaranteed without extra synchronization.
85 	 */
86 	I915_MOCS_CACHED,
87 };
88 
89 /* Each region is a minimum of 16k, and there are at most 255 of them.
90  */
91 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
92 				 * of chars for next/prev indices */
93 #define I915_LOG_MIN_TEX_REGION_SIZE 14
94 
95 typedef struct _drm_i915_init {
96 	enum {
97 		I915_INIT_DMA = 0x01,
98 		I915_CLEANUP_DMA = 0x02,
99 		I915_RESUME_DMA = 0x03
100 	} func;
101 	unsigned int mmio_offset;
102 	int sarea_priv_offset;
103 	unsigned int ring_start;
104 	unsigned int ring_end;
105 	unsigned int ring_size;
106 	unsigned int front_offset;
107 	unsigned int back_offset;
108 	unsigned int depth_offset;
109 	unsigned int w;
110 	unsigned int h;
111 	unsigned int pitch;
112 	unsigned int pitch_bits;
113 	unsigned int back_pitch;
114 	unsigned int depth_pitch;
115 	unsigned int cpp;
116 	unsigned int chipset;
117 } drm_i915_init_t;
118 
119 typedef struct _drm_i915_sarea {
120 	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
121 	int last_upload;	/* last time texture was uploaded */
122 	int last_enqueue;	/* last time a buffer was enqueued */
123 	int last_dispatch;	/* age of the most recently dispatched buffer */
124 	int ctxOwner;		/* last context to upload state */
125 	int texAge;
126 	int pf_enabled;		/* is pageflipping allowed? */
127 	int pf_active;
128 	int pf_current_page;	/* which buffer is being displayed? */
129 	int perf_boxes;		/* performance boxes to be displayed */
130 	int width, height;      /* screen size in pixels */
131 
132 	drm_handle_t front_handle;
133 	int front_offset;
134 	int front_size;
135 
136 	drm_handle_t back_handle;
137 	int back_offset;
138 	int back_size;
139 
140 	drm_handle_t depth_handle;
141 	int depth_offset;
142 	int depth_size;
143 
144 	drm_handle_t tex_handle;
145 	int tex_offset;
146 	int tex_size;
147 	int log_tex_granularity;
148 	int pitch;
149 	int rotation;           /* 0, 90, 180 or 270 */
150 	int rotated_offset;
151 	int rotated_size;
152 	int rotated_pitch;
153 	int virtualX, virtualY;
154 
155 	unsigned int front_tiled;
156 	unsigned int back_tiled;
157 	unsigned int depth_tiled;
158 	unsigned int rotated_tiled;
159 	unsigned int rotated2_tiled;
160 
161 	int pipeA_x;
162 	int pipeA_y;
163 	int pipeA_w;
164 	int pipeA_h;
165 	int pipeB_x;
166 	int pipeB_y;
167 	int pipeB_w;
168 	int pipeB_h;
169 
170 	/* fill out some space for old userspace triple buffer */
171 	drm_handle_t unused_handle;
172 	__u32 unused1, unused2, unused3;
173 
174 	/* buffer object handles for static buffers. May change
175 	 * over the lifetime of the client.
176 	 */
177 	__u32 front_bo_handle;
178 	__u32 back_bo_handle;
179 	__u32 unused_bo_handle;
180 	__u32 depth_bo_handle;
181 
182 } drm_i915_sarea_t;
183 
184 /* due to userspace building against these headers we need some compat here */
185 #define planeA_x pipeA_x
186 #define planeA_y pipeA_y
187 #define planeA_w pipeA_w
188 #define planeA_h pipeA_h
189 #define planeB_x pipeB_x
190 #define planeB_y pipeB_y
191 #define planeB_w pipeB_w
192 #define planeB_h pipeB_h
193 
194 /* Flags for perf_boxes
195  */
196 #define I915_BOX_RING_EMPTY    0x1
197 #define I915_BOX_FLIP          0x2
198 #define I915_BOX_WAIT          0x4
199 #define I915_BOX_TEXTURE_LOAD  0x8
200 #define I915_BOX_LOST_CONTEXT  0x10
201 
202 /*
203  * i915 specific ioctls.
204  *
205  * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
206  * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
207  * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
208  */
209 #define DRM_I915_INIT		0x00
210 #define DRM_I915_FLUSH		0x01
211 #define DRM_I915_FLIP		0x02
212 #define DRM_I915_BATCHBUFFER	0x03
213 #define DRM_I915_IRQ_EMIT	0x04
214 #define DRM_I915_IRQ_WAIT	0x05
215 #define DRM_I915_GETPARAM	0x06
216 #define DRM_I915_SETPARAM	0x07
217 #define DRM_I915_ALLOC		0x08
218 #define DRM_I915_FREE		0x09
219 #define DRM_I915_INIT_HEAP	0x0a
220 #define DRM_I915_CMDBUFFER	0x0b
221 #define DRM_I915_DESTROY_HEAP	0x0c
222 #define DRM_I915_SET_VBLANK_PIPE	0x0d
223 #define DRM_I915_GET_VBLANK_PIPE	0x0e
224 #define DRM_I915_VBLANK_SWAP	0x0f
225 #define DRM_I915_HWS_ADDR	0x11
226 #define DRM_I915_GEM_INIT	0x13
227 #define DRM_I915_GEM_EXECBUFFER	0x14
228 #define DRM_I915_GEM_PIN	0x15
229 #define DRM_I915_GEM_UNPIN	0x16
230 #define DRM_I915_GEM_BUSY	0x17
231 #define DRM_I915_GEM_THROTTLE	0x18
232 #define DRM_I915_GEM_ENTERVT	0x19
233 #define DRM_I915_GEM_LEAVEVT	0x1a
234 #define DRM_I915_GEM_CREATE	0x1b
235 #define DRM_I915_GEM_PREAD	0x1c
236 #define DRM_I915_GEM_PWRITE	0x1d
237 #define DRM_I915_GEM_MMAP	0x1e
238 #define DRM_I915_GEM_SET_DOMAIN	0x1f
239 #define DRM_I915_GEM_SW_FINISH	0x20
240 #define DRM_I915_GEM_SET_TILING	0x21
241 #define DRM_I915_GEM_GET_TILING	0x22
242 #define DRM_I915_GEM_GET_APERTURE 0x23
243 #define DRM_I915_GEM_MMAP_GTT	0x24
244 #define DRM_I915_GET_PIPE_FROM_CRTC_ID	0x25
245 #define DRM_I915_GEM_MADVISE	0x26
246 #define DRM_I915_OVERLAY_PUT_IMAGE	0x27
247 #define DRM_I915_OVERLAY_ATTRS	0x28
248 #define DRM_I915_GEM_EXECBUFFER2	0x29
249 #define DRM_I915_GEM_EXECBUFFER2_WR	DRM_I915_GEM_EXECBUFFER2
250 #define DRM_I915_GET_SPRITE_COLORKEY	0x2a
251 #define DRM_I915_SET_SPRITE_COLORKEY	0x2b
252 #define DRM_I915_GEM_WAIT	0x2c
253 #define DRM_I915_GEM_CONTEXT_CREATE	0x2d
254 #define DRM_I915_GEM_CONTEXT_DESTROY	0x2e
255 #define DRM_I915_GEM_SET_CACHING	0x2f
256 #define DRM_I915_GEM_GET_CACHING	0x30
257 #define DRM_I915_REG_READ		0x31
258 #define DRM_I915_GET_RESET_STATS	0x32
259 #define DRM_I915_GEM_USERPTR		0x33
260 #define DRM_I915_GEM_CONTEXT_GETPARAM	0x34
261 #define DRM_I915_GEM_CONTEXT_SETPARAM	0x35
262 #define DRM_I915_PERF_OPEN		0x36
263 
264 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
265 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
266 #define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
267 #define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
268 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
269 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
270 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
271 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
272 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
273 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
274 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
275 #define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
276 #define DRM_IOCTL_I915_DESTROY_HEAP	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
277 #define DRM_IOCTL_I915_SET_VBLANK_PIPE	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
278 #define DRM_IOCTL_I915_GET_VBLANK_PIPE	DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
279 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
280 #define DRM_IOCTL_I915_HWS_ADDR		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
281 #define DRM_IOCTL_I915_GEM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
282 #define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
283 #define DRM_IOCTL_I915_GEM_EXECBUFFER2	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
284 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
285 #define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
286 #define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
287 #define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
288 #define DRM_IOCTL_I915_GEM_SET_CACHING		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
289 #define DRM_IOCTL_I915_GEM_GET_CACHING		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
290 #define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
291 #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
292 #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
293 #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
294 #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
295 #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
296 #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
297 #define DRM_IOCTL_I915_GEM_MMAP_GTT	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
298 #define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
299 #define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
300 #define DRM_IOCTL_I915_GEM_SET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
301 #define DRM_IOCTL_I915_GEM_GET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
302 #define DRM_IOCTL_I915_GEM_GET_APERTURE	DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
303 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
304 #define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
305 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
306 #define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
307 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
308 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
309 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
310 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
311 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
312 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
313 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
314 #define DRM_IOCTL_I915_GEM_USERPTR			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
315 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
316 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
317 #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
318 
319 /* Allow drivers to submit batchbuffers directly to hardware, relying
320  * on the security mechanisms provided by hardware.
321  */
322 typedef struct drm_i915_batchbuffer {
323 	int start;		/* agp offset */
324 	int used;		/* nr bytes in use */
325 	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
326 	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
327 	int num_cliprects;	/* mulitpass with multiple cliprects? */
328 	struct drm_clip_rect *cliprects;	/* pointer to userspace cliprects */
329 } drm_i915_batchbuffer_t;
330 
331 /* As above, but pass a pointer to userspace buffer which can be
332  * validated by the kernel prior to sending to hardware.
333  */
334 typedef struct _drm_i915_cmdbuffer {
335 	char *buf;	/* pointer to userspace command buffer */
336 	int sz;			/* nr bytes in buf */
337 	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
338 	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
339 	int num_cliprects;	/* mulitpass with multiple cliprects? */
340 	struct drm_clip_rect *cliprects;	/* pointer to userspace cliprects */
341 } drm_i915_cmdbuffer_t;
342 
343 /* Userspace can request & wait on irq's:
344  */
345 typedef struct drm_i915_irq_emit {
346 	int *irq_seq;
347 } drm_i915_irq_emit_t;
348 
349 typedef struct drm_i915_irq_wait {
350 	int irq_seq;
351 } drm_i915_irq_wait_t;
352 
353 /* Ioctl to query kernel params:
354  */
355 #define I915_PARAM_IRQ_ACTIVE            1
356 #define I915_PARAM_ALLOW_BATCHBUFFER     2
357 #define I915_PARAM_LAST_DISPATCH         3
358 #define I915_PARAM_CHIPSET_ID            4
359 #define I915_PARAM_HAS_GEM               5
360 #define I915_PARAM_NUM_FENCES_AVAIL      6
361 #define I915_PARAM_HAS_OVERLAY           7
362 #define I915_PARAM_HAS_PAGEFLIPPING	 8
363 #define I915_PARAM_HAS_EXECBUF2          9
364 #define I915_PARAM_HAS_BSD		 10
365 #define I915_PARAM_HAS_BLT		 11
366 #define I915_PARAM_HAS_RELAXED_FENCING	 12
367 #define I915_PARAM_HAS_COHERENT_RINGS	 13
368 #define I915_PARAM_HAS_EXEC_CONSTANTS	 14
369 #define I915_PARAM_HAS_RELAXED_DELTA	 15
370 #define I915_PARAM_HAS_GEN7_SOL_RESET	 16
371 #define I915_PARAM_HAS_LLC     	 	 17
372 #define I915_PARAM_HAS_ALIASING_PPGTT	 18
373 #define I915_PARAM_HAS_WAIT_TIMEOUT	 19
374 #define I915_PARAM_HAS_SEMAPHORES	 20
375 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH	 21
376 #define I915_PARAM_HAS_VEBOX		 22
377 #define I915_PARAM_HAS_SECURE_BATCHES	 23
378 #define I915_PARAM_HAS_PINNED_BATCHES	 24
379 #define I915_PARAM_HAS_EXEC_NO_RELOC	 25
380 #define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
381 #define I915_PARAM_HAS_WT     	 	 27
382 #define I915_PARAM_CMD_PARSER_VERSION	 28
383 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
384 #define I915_PARAM_MMAP_VERSION          30
385 #define I915_PARAM_HAS_BSD2		 31
386 #define I915_PARAM_REVISION              32
387 #define I915_PARAM_SUBSLICE_TOTAL	 33
388 #define I915_PARAM_EU_TOTAL		 34
389 #define I915_PARAM_HAS_GPU_RESET	 35
390 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
391 #define I915_PARAM_HAS_EXEC_SOFTPIN	 37
392 #define I915_PARAM_HAS_POOLED_EU	 38
393 #define I915_PARAM_MIN_EU_IN_POOL	 39
394 #define I915_PARAM_MMAP_GTT_VERSION	 40
395 
396 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
397  * priorities and the driver will attempt to execute batches in priority order.
398  */
399 #define I915_PARAM_HAS_SCHEDULER	 41
400 #define I915_PARAM_HUC_STATUS		 42
401 
402 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
403  * synchronisation with implicit fencing on individual objects.
404  * See EXEC_OBJECT_ASYNC.
405  */
406 #define I915_PARAM_HAS_EXEC_ASYNC	 43
407 
408 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
409  * both being able to pass in a sync_file fd to wait upon before executing,
410  * and being able to return a new sync_file fd that is signaled when the
411  * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
412  */
413 #define I915_PARAM_HAS_EXEC_FENCE	 44
414 
415 typedef struct drm_i915_getparam {
416 	__s32 param;
417 	/*
418 	 * WARNING: Using pointers instead of fixed-size u64 means we need to write
419 	 * compat32 code. Don't repeat this mistake.
420 	 */
421 	int *value;
422 } drm_i915_getparam_t;
423 
424 /* Ioctl to set kernel params:
425  */
426 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
427 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
428 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
429 #define I915_SETPARAM_NUM_USED_FENCES                     4
430 
431 typedef struct drm_i915_setparam {
432 	int param;
433 	int value;
434 } drm_i915_setparam_t;
435 
436 /* A memory manager for regions of shared memory:
437  */
438 #define I915_MEM_REGION_AGP 1
439 
440 typedef struct drm_i915_mem_alloc {
441 	int region;
442 	int alignment;
443 	int size;
444 	int *region_offset;	/* offset from start of fb or agp */
445 } drm_i915_mem_alloc_t;
446 
447 typedef struct drm_i915_mem_free {
448 	int region;
449 	int region_offset;
450 } drm_i915_mem_free_t;
451 
452 typedef struct drm_i915_mem_init_heap {
453 	int region;
454 	int size;
455 	int start;
456 } drm_i915_mem_init_heap_t;
457 
458 /* Allow memory manager to be torn down and re-initialized (eg on
459  * rotate):
460  */
461 typedef struct drm_i915_mem_destroy_heap {
462 	int region;
463 } drm_i915_mem_destroy_heap_t;
464 
465 /* Allow X server to configure which pipes to monitor for vblank signals
466  */
467 #define	DRM_I915_VBLANK_PIPE_A	1
468 #define	DRM_I915_VBLANK_PIPE_B	2
469 
470 typedef struct drm_i915_vblank_pipe {
471 	int pipe;
472 } drm_i915_vblank_pipe_t;
473 
474 /* Schedule buffer swap at given vertical blank:
475  */
476 typedef struct drm_i915_vblank_swap {
477 	drm_drawable_t drawable;
478 	enum drm_vblank_seq_type seqtype;
479 	unsigned int sequence;
480 } drm_i915_vblank_swap_t;
481 
482 typedef struct drm_i915_hws_addr {
483 	__u64 addr;
484 } drm_i915_hws_addr_t;
485 
486 struct drm_i915_gem_init {
487 	/**
488 	 * Beginning offset in the GTT to be managed by the DRM memory
489 	 * manager.
490 	 */
491 	__u64 gtt_start;
492 	/**
493 	 * Ending offset in the GTT to be managed by the DRM memory
494 	 * manager.
495 	 */
496 	__u64 gtt_end;
497 };
498 
499 struct drm_i915_gem_create {
500 	/**
501 	 * Requested size for the object.
502 	 *
503 	 * The (page-aligned) allocated size for the object will be returned.
504 	 */
505 	__u64 size;
506 	/**
507 	 * Returned handle for the object.
508 	 *
509 	 * Object handles are nonzero.
510 	 */
511 	__u32 handle;
512 	__u32 pad;
513 };
514 
515 struct drm_i915_gem_pread {
516 	/** Handle for the object being read. */
517 	__u32 handle;
518 	__u32 pad;
519 	/** Offset into the object to read from */
520 	__u64 offset;
521 	/** Length of data to read */
522 	__u64 size;
523 	/**
524 	 * Pointer to write the data into.
525 	 *
526 	 * This is a fixed-size type for 32/64 compatibility.
527 	 */
528 	__u64 data_ptr;
529 };
530 
531 struct drm_i915_gem_pwrite {
532 	/** Handle for the object being written to. */
533 	__u32 handle;
534 	__u32 pad;
535 	/** Offset into the object to write to */
536 	__u64 offset;
537 	/** Length of data to write */
538 	__u64 size;
539 	/**
540 	 * Pointer to read the data from.
541 	 *
542 	 * This is a fixed-size type for 32/64 compatibility.
543 	 */
544 	__u64 data_ptr;
545 };
546 
547 struct drm_i915_gem_mmap {
548 	/** Handle for the object being mapped. */
549 	__u32 handle;
550 	__u32 pad;
551 	/** Offset in the object to map. */
552 	__u64 offset;
553 	/**
554 	 * Length of data to map.
555 	 *
556 	 * The value will be page-aligned.
557 	 */
558 	__u64 size;
559 	/**
560 	 * Returned pointer the data was mapped at.
561 	 *
562 	 * This is a fixed-size type for 32/64 compatibility.
563 	 */
564 	__u64 addr_ptr;
565 
566 	/**
567 	 * Flags for extended behaviour.
568 	 *
569 	 * Added in version 2.
570 	 */
571 	__u64 flags;
572 #define I915_MMAP_WC 0x1
573 };
574 
575 struct drm_i915_gem_mmap_gtt {
576 	/** Handle for the object being mapped. */
577 	__u32 handle;
578 	__u32 pad;
579 	/**
580 	 * Fake offset to use for subsequent mmap call
581 	 *
582 	 * This is a fixed-size type for 32/64 compatibility.
583 	 */
584 	__u64 offset;
585 };
586 
587 struct drm_i915_gem_set_domain {
588 	/** Handle for the object */
589 	__u32 handle;
590 
591 	/** New read domains */
592 	__u32 read_domains;
593 
594 	/** New write domain */
595 	__u32 write_domain;
596 };
597 
598 struct drm_i915_gem_sw_finish {
599 	/** Handle for the object */
600 	__u32 handle;
601 };
602 
603 struct drm_i915_gem_relocation_entry {
604 	/**
605 	 * Handle of the buffer being pointed to by this relocation entry.
606 	 *
607 	 * It's appealing to make this be an index into the mm_validate_entry
608 	 * list to refer to the buffer, but this allows the driver to create
609 	 * a relocation list for state buffers and not re-write it per
610 	 * exec using the buffer.
611 	 */
612 	__u32 target_handle;
613 
614 	/**
615 	 * Value to be added to the offset of the target buffer to make up
616 	 * the relocation entry.
617 	 */
618 	__u32 delta;
619 
620 	/** Offset in the buffer the relocation entry will be written into */
621 	__u64 offset;
622 
623 	/**
624 	 * Offset value of the target buffer that the relocation entry was last
625 	 * written as.
626 	 *
627 	 * If the buffer has the same offset as last time, we can skip syncing
628 	 * and writing the relocation.  This value is written back out by
629 	 * the execbuffer ioctl when the relocation is written.
630 	 */
631 	__u64 presumed_offset;
632 
633 	/**
634 	 * Target memory domains read by this operation.
635 	 */
636 	__u32 read_domains;
637 
638 	/**
639 	 * Target memory domains written by this operation.
640 	 *
641 	 * Note that only one domain may be written by the whole
642 	 * execbuffer operation, so that where there are conflicts,
643 	 * the application will get -EINVAL back.
644 	 */
645 	__u32 write_domain;
646 };
647 
648 /** @{
649  * Intel memory domains
650  *
651  * Most of these just align with the various caches in
652  * the system and are used to flush and invalidate as
653  * objects end up cached in different domains.
654  */
655 /** CPU cache */
656 #define I915_GEM_DOMAIN_CPU		0x00000001
657 /** Render cache, used by 2D and 3D drawing */
658 #define I915_GEM_DOMAIN_RENDER		0x00000002
659 /** Sampler cache, used by texture engine */
660 #define I915_GEM_DOMAIN_SAMPLER		0x00000004
661 /** Command queue, used to load batch buffers */
662 #define I915_GEM_DOMAIN_COMMAND		0x00000008
663 /** Instruction cache, used by shader programs */
664 #define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
665 /** Vertex address cache */
666 #define I915_GEM_DOMAIN_VERTEX		0x00000020
667 /** GTT domain - aperture and scanout */
668 #define I915_GEM_DOMAIN_GTT		0x00000040
669 /** @} */
670 
671 struct drm_i915_gem_exec_object {
672 	/**
673 	 * User's handle for a buffer to be bound into the GTT for this
674 	 * operation.
675 	 */
676 	__u32 handle;
677 
678 	/** Number of relocations to be performed on this buffer */
679 	__u32 relocation_count;
680 	/**
681 	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
682 	 * the relocations to be performed in this buffer.
683 	 */
684 	__u64 relocs_ptr;
685 
686 	/** Required alignment in graphics aperture */
687 	__u64 alignment;
688 
689 	/**
690 	 * Returned value of the updated offset of the object, for future
691 	 * presumed_offset writes.
692 	 */
693 	__u64 offset;
694 };
695 
696 struct drm_i915_gem_execbuffer {
697 	/**
698 	 * List of buffers to be validated with their relocations to be
699 	 * performend on them.
700 	 *
701 	 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
702 	 *
703 	 * These buffers must be listed in an order such that all relocations
704 	 * a buffer is performing refer to buffers that have already appeared
705 	 * in the validate list.
706 	 */
707 	__u64 buffers_ptr;
708 	__u32 buffer_count;
709 
710 	/** Offset in the batchbuffer to start execution from. */
711 	__u32 batch_start_offset;
712 	/** Bytes used in batchbuffer from batch_start_offset */
713 	__u32 batch_len;
714 	__u32 DR1;
715 	__u32 DR4;
716 	__u32 num_cliprects;
717 	/** This is a struct drm_clip_rect *cliprects */
718 	__u64 cliprects_ptr;
719 };
720 
721 struct drm_i915_gem_exec_object2 {
722 	/**
723 	 * User's handle for a buffer to be bound into the GTT for this
724 	 * operation.
725 	 */
726 	__u32 handle;
727 
728 	/** Number of relocations to be performed on this buffer */
729 	__u32 relocation_count;
730 	/**
731 	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
732 	 * the relocations to be performed in this buffer.
733 	 */
734 	__u64 relocs_ptr;
735 
736 	/** Required alignment in graphics aperture */
737 	__u64 alignment;
738 
739 	/**
740 	 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
741 	 * the user with the GTT offset at which this object will be pinned.
742 	 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
743 	 * presumed_offset of the object.
744 	 * During execbuffer2 the kernel populates it with the value of the
745 	 * current GTT offset of the object, for future presumed_offset writes.
746 	 */
747 	__u64 offset;
748 
749 #define EXEC_OBJECT_NEEDS_FENCE		 (1<<0)
750 #define EXEC_OBJECT_NEEDS_GTT		 (1<<1)
751 #define EXEC_OBJECT_WRITE		 (1<<2)
752 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
753 #define EXEC_OBJECT_PINNED		 (1<<4)
754 #define EXEC_OBJECT_PAD_TO_SIZE		 (1<<5)
755 /* The kernel implicitly tracks GPU activity on all GEM objects, and
756  * synchronises operations with outstanding rendering. This includes
757  * rendering on other devices if exported via dma-buf. However, sometimes
758  * this tracking is too coarse and the user knows better. For example,
759  * if the object is split into non-overlapping ranges shared between different
760  * clients or engines (i.e. suballocating objects), the implicit tracking
761  * by kernel assumes that each operation affects the whole object rather
762  * than an individual range, causing needless synchronisation between clients.
763  * The kernel will also forgo any CPU cache flushes prior to rendering from
764  * the object as the client is expected to be also handling such domain
765  * tracking.
766  *
767  * The kernel maintains the implicit tracking in order to manage resources
768  * used by the GPU - this flag only disables the synchronisation prior to
769  * rendering with this object in this execbuf.
770  *
771  * Opting out of implicit synhronisation requires the user to do its own
772  * explicit tracking to avoid rendering corruption. See, for example,
773  * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
774  */
775 #define EXEC_OBJECT_ASYNC		(1<<6)
776 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
777 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
778 	__u64 flags;
779 
780 	union {
781 		__u64 rsvd1;
782 		__u64 pad_to_size;
783 	};
784 	__u64 rsvd2;
785 };
786 
787 struct drm_i915_gem_execbuffer2 {
788 	/**
789 	 * List of gem_exec_object2 structs
790 	 */
791 	__u64 buffers_ptr;
792 	__u32 buffer_count;
793 
794 	/** Offset in the batchbuffer to start execution from. */
795 	__u32 batch_start_offset;
796 	/** Bytes used in batchbuffer from batch_start_offset */
797 	__u32 batch_len;
798 	__u32 DR1;
799 	__u32 DR4;
800 	__u32 num_cliprects;
801 	/** This is a struct drm_clip_rect *cliprects */
802 	__u64 cliprects_ptr;
803 #define I915_EXEC_RING_MASK              (7<<0)
804 #define I915_EXEC_DEFAULT                (0<<0)
805 #define I915_EXEC_RENDER                 (1<<0)
806 #define I915_EXEC_BSD                    (2<<0)
807 #define I915_EXEC_BLT                    (3<<0)
808 #define I915_EXEC_VEBOX                  (4<<0)
809 
810 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
811  * Gen6+ only supports relative addressing to dynamic state (default) and
812  * absolute addressing.
813  *
814  * These flags are ignored for the BSD and BLT rings.
815  */
816 #define I915_EXEC_CONSTANTS_MASK 	(3<<6)
817 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
818 #define I915_EXEC_CONSTANTS_ABSOLUTE 	(1<<6)
819 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
820 	__u64 flags;
821 	__u64 rsvd1; /* now used for context info */
822 	__u64 rsvd2;
823 };
824 
825 /** Resets the SO write offset registers for transform feedback on gen7. */
826 #define I915_EXEC_GEN7_SOL_RESET	(1<<8)
827 
828 /** Request a privileged ("secure") batch buffer. Note only available for
829  * DRM_ROOT_ONLY | DRM_MASTER processes.
830  */
831 #define I915_EXEC_SECURE		(1<<9)
832 
833 /** Inform the kernel that the batch is and will always be pinned. This
834  * negates the requirement for a workaround to be performed to avoid
835  * an incoherent CS (such as can be found on 830/845). If this flag is
836  * not passed, the kernel will endeavour to make sure the batch is
837  * coherent with the CS before execution. If this flag is passed,
838  * userspace assumes the responsibility for ensuring the same.
839  */
840 #define I915_EXEC_IS_PINNED		(1<<10)
841 
842 /** Provide a hint to the kernel that the command stream and auxiliary
843  * state buffers already holds the correct presumed addresses and so the
844  * relocation process may be skipped if no buffers need to be moved in
845  * preparation for the execbuffer.
846  */
847 #define I915_EXEC_NO_RELOC		(1<<11)
848 
849 /** Use the reloc.handle as an index into the exec object array rather
850  * than as the per-file handle.
851  */
852 #define I915_EXEC_HANDLE_LUT		(1<<12)
853 
854 /** Used for switching BSD rings on the platforms with two BSD rings */
855 #define I915_EXEC_BSD_SHIFT	 (13)
856 #define I915_EXEC_BSD_MASK	 (3 << I915_EXEC_BSD_SHIFT)
857 /* default ping-pong mode */
858 #define I915_EXEC_BSD_DEFAULT	 (0 << I915_EXEC_BSD_SHIFT)
859 #define I915_EXEC_BSD_RING1	 (1 << I915_EXEC_BSD_SHIFT)
860 #define I915_EXEC_BSD_RING2	 (2 << I915_EXEC_BSD_SHIFT)
861 
862 /** Tell the kernel that the batchbuffer is processed by
863  *  the resource streamer.
864  */
865 #define I915_EXEC_RESOURCE_STREAMER     (1<<15)
866 
867 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
868  * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
869  * the batch.
870  *
871  * Returns -EINVAL if the sync_file fd cannot be found.
872  */
873 #define I915_EXEC_FENCE_IN		(1<<16)
874 
875 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
876  * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
877  * to the caller, and it should be close() after use. (The fd is a regular
878  * file descriptor and will be cleaned up on process termination. It holds
879  * a reference to the request, but nothing else.)
880  *
881  * The sync_file fd can be combined with other sync_file and passed either
882  * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
883  * will only occur after this request completes), or to other devices.
884  *
885  * Using I915_EXEC_FENCE_OUT requires use of
886  * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
887  * back to userspace. Failure to do so will cause the out-fence to always
888  * be reported as zero, and the real fence fd to be leaked.
889  */
890 #define I915_EXEC_FENCE_OUT		(1<<17)
891 
892 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
893 
894 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
895 #define i915_execbuffer2_set_context_id(eb2, context) \
896 	(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
897 #define i915_execbuffer2_get_context_id(eb2) \
898 	((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
899 
900 struct drm_i915_gem_pin {
901 	/** Handle of the buffer to be pinned. */
902 	__u32 handle;
903 	__u32 pad;
904 
905 	/** alignment required within the aperture */
906 	__u64 alignment;
907 
908 	/** Returned GTT offset of the buffer. */
909 	__u64 offset;
910 };
911 
912 struct drm_i915_gem_unpin {
913 	/** Handle of the buffer to be unpinned. */
914 	__u32 handle;
915 	__u32 pad;
916 };
917 
918 struct drm_i915_gem_busy {
919 	/** Handle of the buffer to check for busy */
920 	__u32 handle;
921 
922 	/** Return busy status
923 	 *
924 	 * A return of 0 implies that the object is idle (after
925 	 * having flushed any pending activity), and a non-zero return that
926 	 * the object is still in-flight on the GPU. (The GPU has not yet
927 	 * signaled completion for all pending requests that reference the
928 	 * object.) An object is guaranteed to become idle eventually (so
929 	 * long as no new GPU commands are executed upon it). Due to the
930 	 * asynchronous nature of the hardware, an object reported
931 	 * as busy may become idle before the ioctl is completed.
932 	 *
933 	 * Furthermore, if the object is busy, which engine is busy is only
934 	 * provided as a guide. There are race conditions which prevent the
935 	 * report of which engines are busy from being always accurate.
936 	 * However, the converse is not true. If the object is idle, the
937 	 * result of the ioctl, that all engines are idle, is accurate.
938 	 *
939 	 * The returned dword is split into two fields to indicate both
940 	 * the engines on which the object is being read, and the
941 	 * engine on which it is currently being written (if any).
942 	 *
943 	 * The low word (bits 0:15) indicate if the object is being written
944 	 * to by any engine (there can only be one, as the GEM implicit
945 	 * synchronisation rules force writes to be serialised). Only the
946 	 * engine for the last write is reported.
947 	 *
948 	 * The high word (bits 16:31) are a bitmask of which engines are
949 	 * currently reading from the object. Multiple engines may be
950 	 * reading from the object simultaneously.
951 	 *
952 	 * The value of each engine is the same as specified in the
953 	 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
954 	 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
955 	 * the I915_EXEC_RENDER engine for execution, and so it is never
956 	 * reported as active itself. Some hardware may have parallel
957 	 * execution engines, e.g. multiple media engines, which are
958 	 * mapped to the same identifier in the EXECBUFFER2 ioctl and
959 	 * so are not separately reported for busyness.
960 	 *
961 	 * Caveat emptor:
962 	 * Only the boolean result of this query is reliable; that is whether
963 	 * the object is idle or busy. The report of which engines are busy
964 	 * should be only used as a heuristic.
965 	 */
966 	__u32 busy;
967 };
968 
969 /**
970  * I915_CACHING_NONE
971  *
972  * GPU access is not coherent with cpu caches. Default for machines without an
973  * LLC.
974  */
975 #define I915_CACHING_NONE		0
976 /**
977  * I915_CACHING_CACHED
978  *
979  * GPU access is coherent with cpu caches and furthermore the data is cached in
980  * last-level caches shared between cpu cores and the gpu GT. Default on
981  * machines with HAS_LLC.
982  */
983 #define I915_CACHING_CACHED		1
984 /**
985  * I915_CACHING_DISPLAY
986  *
987  * Special GPU caching mode which is coherent with the scanout engines.
988  * Transparently falls back to I915_CACHING_NONE on platforms where no special
989  * cache mode (like write-through or gfdt flushing) is available. The kernel
990  * automatically sets this mode when using a buffer as a scanout target.
991  * Userspace can manually set this mode to avoid a costly stall and clflush in
992  * the hotpath of drawing the first frame.
993  */
994 #define I915_CACHING_DISPLAY		2
995 
996 struct drm_i915_gem_caching {
997 	/**
998 	 * Handle of the buffer to set/get the caching level of. */
999 	__u32 handle;
1000 
1001 	/**
1002 	 * Cacheing level to apply or return value
1003 	 *
1004 	 * bits0-15 are for generic caching control (i.e. the above defined
1005 	 * values). bits16-31 are reserved for platform-specific variations
1006 	 * (e.g. l3$ caching on gen7). */
1007 	__u32 caching;
1008 };
1009 
1010 #define I915_TILING_NONE	0
1011 #define I915_TILING_X		1
1012 #define I915_TILING_Y		2
1013 #define I915_TILING_LAST	I915_TILING_Y
1014 
1015 #define I915_BIT_6_SWIZZLE_NONE		0
1016 #define I915_BIT_6_SWIZZLE_9		1
1017 #define I915_BIT_6_SWIZZLE_9_10		2
1018 #define I915_BIT_6_SWIZZLE_9_11		3
1019 #define I915_BIT_6_SWIZZLE_9_10_11	4
1020 /* Not seen by userland */
1021 #define I915_BIT_6_SWIZZLE_UNKNOWN	5
1022 /* Seen by userland. */
1023 #define I915_BIT_6_SWIZZLE_9_17		6
1024 #define I915_BIT_6_SWIZZLE_9_10_17	7
1025 
1026 struct drm_i915_gem_set_tiling {
1027 	/** Handle of the buffer to have its tiling state updated */
1028 	__u32 handle;
1029 
1030 	/**
1031 	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1032 	 * I915_TILING_Y).
1033 	 *
1034 	 * This value is to be set on request, and will be updated by the
1035 	 * kernel on successful return with the actual chosen tiling layout.
1036 	 *
1037 	 * The tiling mode may be demoted to I915_TILING_NONE when the system
1038 	 * has bit 6 swizzling that can't be managed correctly by GEM.
1039 	 *
1040 	 * Buffer contents become undefined when changing tiling_mode.
1041 	 */
1042 	__u32 tiling_mode;
1043 
1044 	/**
1045 	 * Stride in bytes for the object when in I915_TILING_X or
1046 	 * I915_TILING_Y.
1047 	 */
1048 	__u32 stride;
1049 
1050 	/**
1051 	 * Returned address bit 6 swizzling required for CPU access through
1052 	 * mmap mapping.
1053 	 */
1054 	__u32 swizzle_mode;
1055 };
1056 
1057 struct drm_i915_gem_get_tiling {
1058 	/** Handle of the buffer to get tiling state for. */
1059 	__u32 handle;
1060 
1061 	/**
1062 	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1063 	 * I915_TILING_Y).
1064 	 */
1065 	__u32 tiling_mode;
1066 
1067 	/**
1068 	 * Returned address bit 6 swizzling required for CPU access through
1069 	 * mmap mapping.
1070 	 */
1071 	__u32 swizzle_mode;
1072 
1073 	/**
1074 	 * Returned address bit 6 swizzling required for CPU access through
1075 	 * mmap mapping whilst bound.
1076 	 */
1077 	__u32 phys_swizzle_mode;
1078 };
1079 
1080 struct drm_i915_gem_get_aperture {
1081 	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1082 	__u64 aper_size;
1083 
1084 	/**
1085 	 * Available space in the aperture used by i915_gem_execbuffer, in
1086 	 * bytes
1087 	 */
1088 	__u64 aper_available_size;
1089 };
1090 
1091 struct drm_i915_get_pipe_from_crtc_id {
1092 	/** ID of CRTC being requested **/
1093 	__u32 crtc_id;
1094 
1095 	/** pipe of requested CRTC **/
1096 	__u32 pipe;
1097 };
1098 
1099 #define I915_MADV_WILLNEED 0
1100 #define I915_MADV_DONTNEED 1
1101 #define __I915_MADV_PURGED 2 /* internal state */
1102 
1103 struct drm_i915_gem_madvise {
1104 	/** Handle of the buffer to change the backing store advice */
1105 	__u32 handle;
1106 
1107 	/* Advice: either the buffer will be needed again in the near future,
1108 	 *         or wont be and could be discarded under memory pressure.
1109 	 */
1110 	__u32 madv;
1111 
1112 	/** Whether the backing store still exists. */
1113 	__u32 retained;
1114 };
1115 
1116 /* flags */
1117 #define I915_OVERLAY_TYPE_MASK 		0xff
1118 #define I915_OVERLAY_YUV_PLANAR 	0x01
1119 #define I915_OVERLAY_YUV_PACKED 	0x02
1120 #define I915_OVERLAY_RGB		0x03
1121 
1122 #define I915_OVERLAY_DEPTH_MASK		0xff00
1123 #define I915_OVERLAY_RGB24		0x1000
1124 #define I915_OVERLAY_RGB16		0x2000
1125 #define I915_OVERLAY_RGB15		0x3000
1126 #define I915_OVERLAY_YUV422		0x0100
1127 #define I915_OVERLAY_YUV411		0x0200
1128 #define I915_OVERLAY_YUV420		0x0300
1129 #define I915_OVERLAY_YUV410		0x0400
1130 
1131 #define I915_OVERLAY_SWAP_MASK		0xff0000
1132 #define I915_OVERLAY_NO_SWAP		0x000000
1133 #define I915_OVERLAY_UV_SWAP		0x010000
1134 #define I915_OVERLAY_Y_SWAP		0x020000
1135 #define I915_OVERLAY_Y_AND_UV_SWAP	0x030000
1136 
1137 #define I915_OVERLAY_FLAGS_MASK		0xff000000
1138 #define I915_OVERLAY_ENABLE		0x01000000
1139 
1140 struct drm_intel_overlay_put_image {
1141 	/* various flags and src format description */
1142 	__u32 flags;
1143 	/* source picture description */
1144 	__u32 bo_handle;
1145 	/* stride values and offsets are in bytes, buffer relative */
1146 	__u16 stride_Y; /* stride for packed formats */
1147 	__u16 stride_UV;
1148 	__u32 offset_Y; /* offset for packet formats */
1149 	__u32 offset_U;
1150 	__u32 offset_V;
1151 	/* in pixels */
1152 	__u16 src_width;
1153 	__u16 src_height;
1154 	/* to compensate the scaling factors for partially covered surfaces */
1155 	__u16 src_scan_width;
1156 	__u16 src_scan_height;
1157 	/* output crtc description */
1158 	__u32 crtc_id;
1159 	__u16 dst_x;
1160 	__u16 dst_y;
1161 	__u16 dst_width;
1162 	__u16 dst_height;
1163 };
1164 
1165 /* flags */
1166 #define I915_OVERLAY_UPDATE_ATTRS	(1<<0)
1167 #define I915_OVERLAY_UPDATE_GAMMA	(1<<1)
1168 #define I915_OVERLAY_DISABLE_DEST_COLORKEY	(1<<2)
1169 struct drm_intel_overlay_attrs {
1170 	__u32 flags;
1171 	__u32 color_key;
1172 	__s32 brightness;
1173 	__u32 contrast;
1174 	__u32 saturation;
1175 	__u32 gamma0;
1176 	__u32 gamma1;
1177 	__u32 gamma2;
1178 	__u32 gamma3;
1179 	__u32 gamma4;
1180 	__u32 gamma5;
1181 };
1182 
1183 /*
1184  * Intel sprite handling
1185  *
1186  * Color keying works with a min/mask/max tuple.  Both source and destination
1187  * color keying is allowed.
1188  *
1189  * Source keying:
1190  * Sprite pixels within the min & max values, masked against the color channels
1191  * specified in the mask field, will be transparent.  All other pixels will
1192  * be displayed on top of the primary plane.  For RGB surfaces, only the min
1193  * and mask fields will be used; ranged compares are not allowed.
1194  *
1195  * Destination keying:
1196  * Primary plane pixels that match the min value, masked against the color
1197  * channels specified in the mask field, will be replaced by corresponding
1198  * pixels from the sprite plane.
1199  *
1200  * Note that source & destination keying are exclusive; only one can be
1201  * active on a given plane.
1202  */
1203 
1204 #define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
1205 #define I915_SET_COLORKEY_DESTINATION	(1<<1)
1206 #define I915_SET_COLORKEY_SOURCE	(1<<2)
1207 struct drm_intel_sprite_colorkey {
1208 	__u32 plane_id;
1209 	__u32 min_value;
1210 	__u32 channel_mask;
1211 	__u32 max_value;
1212 	__u32 flags;
1213 };
1214 
1215 struct drm_i915_gem_wait {
1216 	/** Handle of BO we shall wait on */
1217 	__u32 bo_handle;
1218 	__u32 flags;
1219 	/** Number of nanoseconds to wait, Returns time remaining. */
1220 	__s64 timeout_ns;
1221 };
1222 
1223 struct drm_i915_gem_context_create {
1224 	/*  output: id of new context*/
1225 	__u32 ctx_id;
1226 	__u32 pad;
1227 };
1228 
1229 struct drm_i915_gem_context_destroy {
1230 	__u32 ctx_id;
1231 	__u32 pad;
1232 };
1233 
1234 struct drm_i915_reg_read {
1235 	/*
1236 	 * Register offset.
1237 	 * For 64bit wide registers where the upper 32bits don't immediately
1238 	 * follow the lower 32bits, the offset of the lower 32bits must
1239 	 * be specified
1240 	 */
1241 	__u64 offset;
1242 	__u64 val; /* Return value */
1243 };
1244 /* Known registers:
1245  *
1246  * Render engine timestamp - 0x2358 + 64bit - gen7+
1247  * - Note this register returns an invalid value if using the default
1248  *   single instruction 8byte read, in order to workaround that use
1249  *   offset (0x2538 | 1) instead.
1250  *
1251  */
1252 
1253 struct drm_i915_reset_stats {
1254 	__u32 ctx_id;
1255 	__u32 flags;
1256 
1257 	/* All resets since boot/module reload, for all contexts */
1258 	__u32 reset_count;
1259 
1260 	/* Number of batches lost when active in GPU, for this context */
1261 	__u32 batch_active;
1262 
1263 	/* Number of batches lost pending for execution, for this context */
1264 	__u32 batch_pending;
1265 
1266 	__u32 pad;
1267 };
1268 
1269 struct drm_i915_gem_userptr {
1270 	__u64 user_ptr;
1271 	__u64 user_size;
1272 	__u32 flags;
1273 #define I915_USERPTR_READ_ONLY 0x1
1274 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1275 	/**
1276 	 * Returned handle for the object.
1277 	 *
1278 	 * Object handles are nonzero.
1279 	 */
1280 	__u32 handle;
1281 };
1282 
1283 struct drm_i915_gem_context_param {
1284 	__u32 ctx_id;
1285 	__u32 size;
1286 	__u64 param;
1287 #define I915_CONTEXT_PARAM_BAN_PERIOD	0x1
1288 #define I915_CONTEXT_PARAM_NO_ZEROMAP	0x2
1289 #define I915_CONTEXT_PARAM_GTT_SIZE	0x3
1290 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE	0x4
1291 #define I915_CONTEXT_PARAM_BANNABLE	0x5
1292 	__u64 value;
1293 };
1294 
1295 enum drm_i915_oa_format {
1296 	I915_OA_FORMAT_A13 = 1,
1297 	I915_OA_FORMAT_A29,
1298 	I915_OA_FORMAT_A13_B8_C8,
1299 	I915_OA_FORMAT_B4_C8,
1300 	I915_OA_FORMAT_A45_B8_C8,
1301 	I915_OA_FORMAT_B4_C8_A16,
1302 	I915_OA_FORMAT_C4_B8,
1303 
1304 	I915_OA_FORMAT_MAX	    /* non-ABI */
1305 };
1306 
1307 enum drm_i915_perf_property_id {
1308 	/**
1309 	 * Open the stream for a specific context handle (as used with
1310 	 * execbuffer2). A stream opened for a specific context this way
1311 	 * won't typically require root privileges.
1312 	 */
1313 	DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1314 
1315 	/**
1316 	 * A value of 1 requests the inclusion of raw OA unit reports as
1317 	 * part of stream samples.
1318 	 */
1319 	DRM_I915_PERF_PROP_SAMPLE_OA,
1320 
1321 	/**
1322 	 * The value specifies which set of OA unit metrics should be
1323 	 * be configured, defining the contents of any OA unit reports.
1324 	 */
1325 	DRM_I915_PERF_PROP_OA_METRICS_SET,
1326 
1327 	/**
1328 	 * The value specifies the size and layout of OA unit reports.
1329 	 */
1330 	DRM_I915_PERF_PROP_OA_FORMAT,
1331 
1332 	/**
1333 	 * Specifying this property implicitly requests periodic OA unit
1334 	 * sampling and (at least on Haswell) the sampling frequency is derived
1335 	 * from this exponent as follows:
1336 	 *
1337 	 *   80ns * 2^(period_exponent + 1)
1338 	 */
1339 	DRM_I915_PERF_PROP_OA_EXPONENT,
1340 
1341 	DRM_I915_PERF_PROP_MAX /* non-ABI */
1342 };
1343 
1344 struct drm_i915_perf_open_param {
1345 	__u32 flags;
1346 #define I915_PERF_FLAG_FD_CLOEXEC	(1<<0)
1347 #define I915_PERF_FLAG_FD_NONBLOCK	(1<<1)
1348 #define I915_PERF_FLAG_DISABLED		(1<<2)
1349 
1350 	/** The number of u64 (id, value) pairs */
1351 	__u32 num_properties;
1352 
1353 	/**
1354 	 * Pointer to array of u64 (id, value) pairs configuring the stream
1355 	 * to open.
1356 	 */
1357 	__u64 properties_ptr;
1358 };
1359 
1360 /**
1361  * Enable data capture for a stream that was either opened in a disabled state
1362  * via I915_PERF_FLAG_DISABLED or was later disabled via
1363  * I915_PERF_IOCTL_DISABLE.
1364  *
1365  * It is intended to be cheaper to disable and enable a stream than it may be
1366  * to close and re-open a stream with the same configuration.
1367  *
1368  * It's undefined whether any pending data for the stream will be lost.
1369  */
1370 #define I915_PERF_IOCTL_ENABLE	_IO('i', 0x0)
1371 
1372 /**
1373  * Disable data capture for a stream.
1374  *
1375  * It is an error to try and read a stream that is disabled.
1376  */
1377 #define I915_PERF_IOCTL_DISABLE	_IO('i', 0x1)
1378 
1379 /**
1380  * Common to all i915 perf records
1381  */
1382 struct drm_i915_perf_record_header {
1383 	__u32 type;
1384 	__u16 pad;
1385 	__u16 size;
1386 };
1387 
1388 enum drm_i915_perf_record_type {
1389 
1390 	/**
1391 	 * Samples are the work horse record type whose contents are extensible
1392 	 * and defined when opening an i915 perf stream based on the given
1393 	 * properties.
1394 	 *
1395 	 * Boolean properties following the naming convention
1396 	 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1397 	 * every sample.
1398 	 *
1399 	 * The order of these sample properties given by userspace has no
1400 	 * affect on the ordering of data within a sample. The order is
1401 	 * documented here.
1402 	 *
1403 	 * struct {
1404 	 *     struct drm_i915_perf_record_header header;
1405 	 *
1406 	 *     { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1407 	 * };
1408 	 */
1409 	DRM_I915_PERF_RECORD_SAMPLE = 1,
1410 
1411 	/*
1412 	 * Indicates that one or more OA reports were not written by the
1413 	 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1414 	 * command collides with periodic sampling - which would be more likely
1415 	 * at higher sampling frequencies.
1416 	 */
1417 	DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1418 
1419 	/**
1420 	 * An error occurred that resulted in all pending OA reports being lost.
1421 	 */
1422 	DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1423 
1424 	DRM_I915_PERF_RECORD_MAX /* non-ABI */
1425 };
1426 
1427 #if defined(__cplusplus)
1428 }
1429 #endif
1430 
1431 #endif /* _I915_DRM_H_ */
1432