| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 304 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, in changeLoad()
362 bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, in changeStore()
424 const MachineOperand &ImmOp, in changeAddAsl()
490 const MachineOperand ImmOp = TfrMI->getOperand(1); in xformUseMI() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 282 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue()); in foldOperand() local
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| D | SIInstrInfo.cpp | 1231 const MachineOperand &ImmOp = DefMI.getOperand(1); in FoldImmediate() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 232 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 138 struct ImmOp { struct in __anon350cf59d0111::AMDGPUOperand
139 bool IsFPImm;
140 ImmTy Type;
141 int64_t Val;
142 Modifiers Mods;
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 595 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
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| D | ThumbRegisterInfo.cpp | 385 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
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| D | ARMBaseInstrInfo.cpp | 2246 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 521 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
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| D | Thumb1RegisterInfo.cpp | 493 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
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| D | ARMBaseInstrInfo.cpp | 1641 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex() local
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 206 struct ImmOp { struct in __anonf1be40530111::SparcOperand
207 const MCExpr *Val;
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 48 struct ImmOp { struct
49 const MCExpr *Val;
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| D | X86AsmParser.cpp | 2238 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2265 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2292 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 109 struct ImmOp { struct
110 const MCExpr *Value;
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 335 struct ImmOp { struct
336 int64_t Val;
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 611 struct ImmOp { struct in __anon62f483b30311::MipsOperand
612 const MCExpr *Val;
2313 const MCOperand &ImmOp = Inst.getOperand(1); in expandLoadImm() local
2591 const MCOperand &ImmOp = Inst.getOperand(1); in expandBranchImm() local
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 253 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 193 struct ImmOp { struct in __anon15a73d730211::AArch64Operand
194 const MCExpr *Val;
4001 AArch64Operand &ImmOp = static_cast<AArch64Operand &>(*Operands[2]); in MatchAndEmitInstruction() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1412 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { in lowerMSASplatImm()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 504 struct ImmOp { struct in __anon58d02de10311::ARMOperand
505 const MCExpr *Val;
4775 int CondOp = -1, ImmOp = -1; in cvtThumbBranches() local
|