1 //===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file defines the FastISel class. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_FASTISEL_H 16 #define LLVM_CODEGEN_FASTISEL_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/IR/CallingConv.h" 21 #include "llvm/IR/IntrinsicInst.h" 22 #include "llvm/Target/TargetLowering.h" 23 24 namespace llvm { 25 26 class MachineConstantPool; 27 28 /// \brief This is a fast-path instruction selection class that generates poor 29 /// code and doesn't support illegal types or non-trivial lowering, but runs 30 /// quickly. 31 class FastISel { 32 public: 33 struct ArgListEntry { 34 Value *Val; 35 Type *Ty; 36 bool IsSExt : 1; 37 bool IsZExt : 1; 38 bool IsInReg : 1; 39 bool IsSRet : 1; 40 bool IsNest : 1; 41 bool IsByVal : 1; 42 bool IsInAlloca : 1; 43 bool IsReturned : 1; 44 bool IsSwiftSelf : 1; 45 bool IsSwiftError : 1; 46 uint16_t Alignment; 47 ArgListEntryArgListEntry48 ArgListEntry() 49 : Val(nullptr), Ty(nullptr), IsSExt(false), IsZExt(false), 50 IsInReg(false), IsSRet(false), IsNest(false), IsByVal(false), 51 IsInAlloca(false), IsReturned(false), IsSwiftSelf(false), 52 IsSwiftError(false), Alignment(0) {} 53 54 /// \brief Set CallLoweringInfo attribute flags based on a call instruction 55 /// and called function attributes. 56 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx); 57 }; 58 typedef std::vector<ArgListEntry> ArgListTy; 59 60 struct CallLoweringInfo { 61 Type *RetTy; 62 bool RetSExt : 1; 63 bool RetZExt : 1; 64 bool IsVarArg : 1; 65 bool IsInReg : 1; 66 bool DoesNotReturn : 1; 67 bool IsReturnValueUsed : 1; 68 69 // \brief IsTailCall Should be modified by implementations of FastLowerCall 70 // that perform tail call conversions. 71 bool IsTailCall; 72 73 unsigned NumFixedArgs; 74 CallingConv::ID CallConv; 75 const Value *Callee; 76 MCSymbol *Symbol; 77 ArgListTy Args; 78 ImmutableCallSite *CS; 79 MachineInstr *Call; 80 unsigned ResultReg; 81 unsigned NumResultRegs; 82 83 bool IsPatchPoint; 84 85 SmallVector<Value *, 16> OutVals; 86 SmallVector<ISD::ArgFlagsTy, 16> OutFlags; 87 SmallVector<unsigned, 16> OutRegs; 88 SmallVector<ISD::InputArg, 4> Ins; 89 SmallVector<unsigned, 4> InRegs; 90 CallLoweringInfoCallLoweringInfo91 CallLoweringInfo() 92 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false), 93 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true), 94 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C), 95 Callee(nullptr), Symbol(nullptr), CS(nullptr), Call(nullptr), 96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {} 97 setCalleeCallLoweringInfo98 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy, 99 const Value *Target, ArgListTy &&ArgsList, 100 ImmutableCallSite &Call) { 101 RetTy = ResultTy; 102 Callee = Target; 103 104 IsInReg = Call.paramHasAttr(0, Attribute::InReg); 105 DoesNotReturn = Call.doesNotReturn(); 106 IsVarArg = FuncTy->isVarArg(); 107 IsReturnValueUsed = !Call.getInstruction()->use_empty(); 108 RetSExt = Call.paramHasAttr(0, Attribute::SExt); 109 RetZExt = Call.paramHasAttr(0, Attribute::ZExt); 110 111 CallConv = Call.getCallingConv(); 112 Args = std::move(ArgsList); 113 NumFixedArgs = FuncTy->getNumParams(); 114 115 CS = &Call; 116 117 return *this; 118 } 119 120 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy, 121 MCSymbol *Target, ArgListTy &&ArgsList, 122 ImmutableCallSite &Call, 123 unsigned FixedArgs = ~0U) { 124 RetTy = ResultTy; 125 Callee = Call.getCalledValue(); 126 Symbol = Target; 127 128 IsInReg = Call.paramHasAttr(0, Attribute::InReg); 129 DoesNotReturn = Call.doesNotReturn(); 130 IsVarArg = FuncTy->isVarArg(); 131 IsReturnValueUsed = !Call.getInstruction()->use_empty(); 132 RetSExt = Call.paramHasAttr(0, Attribute::SExt); 133 RetZExt = Call.paramHasAttr(0, Attribute::ZExt); 134 135 CallConv = Call.getCallingConv(); 136 Args = std::move(ArgsList); 137 NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs; 138 139 CS = &Call; 140 141 return *this; 142 } 143 144 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy, 145 const Value *Target, ArgListTy &&ArgsList, 146 unsigned FixedArgs = ~0U) { 147 RetTy = ResultTy; 148 Callee = Target; 149 CallConv = CC; 150 Args = std::move(ArgsList); 151 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs; 152 return *this; 153 } 154 155 CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx, 156 CallingConv::ID CC, Type *ResultTy, 157 const char *Target, ArgListTy &&ArgsList, 158 unsigned FixedArgs = ~0U); 159 160 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy, 161 MCSymbol *Target, ArgListTy &&ArgsList, 162 unsigned FixedArgs = ~0U) { 163 RetTy = ResultTy; 164 Symbol = Target; 165 CallConv = CC; 166 Args = std::move(ArgsList); 167 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs; 168 return *this; 169 } 170 171 CallLoweringInfo &setTailCall(bool Value = true) { 172 IsTailCall = Value; 173 return *this; 174 } 175 176 CallLoweringInfo &setIsPatchPoint(bool Value = true) { 177 IsPatchPoint = Value; 178 return *this; 179 } 180 getArgsCallLoweringInfo181 ArgListTy &getArgs() { return Args; } 182 clearOutsCallLoweringInfo183 void clearOuts() { 184 OutVals.clear(); 185 OutFlags.clear(); 186 OutRegs.clear(); 187 } 188 clearInsCallLoweringInfo189 void clearIns() { 190 Ins.clear(); 191 InRegs.clear(); 192 } 193 }; 194 195 protected: 196 DenseMap<const Value *, unsigned> LocalValueMap; 197 FunctionLoweringInfo &FuncInfo; 198 MachineFunction *MF; 199 MachineRegisterInfo &MRI; 200 MachineFrameInfo &MFI; 201 MachineConstantPool &MCP; 202 DebugLoc DbgLoc; 203 const TargetMachine &TM; 204 const DataLayout &DL; 205 const TargetInstrInfo &TII; 206 const TargetLowering &TLI; 207 const TargetRegisterInfo &TRI; 208 const TargetLibraryInfo *LibInfo; 209 bool SkipTargetIndependentISel; 210 211 /// \brief The position of the last instruction for materializing constants 212 /// for use in the current block. It resets to EmitStartPt when it makes sense 213 /// (for example, it's usually profitable to avoid function calls between the 214 /// definition and the use) 215 MachineInstr *LastLocalValue; 216 217 /// \brief The top most instruction in the current block that is allowed for 218 /// emitting local variables. LastLocalValue resets to EmitStartPt when it 219 /// makes sense (for example, on function calls) 220 MachineInstr *EmitStartPt; 221 222 public: 223 /// \brief Return the position of the last instruction emitted for 224 /// materializing constants for use in the current block. getLastLocalValue()225 MachineInstr *getLastLocalValue() { return LastLocalValue; } 226 227 /// \brief Update the position of the last instruction emitted for 228 /// materializing constants for use in the current block. setLastLocalValue(MachineInstr * I)229 void setLastLocalValue(MachineInstr *I) { 230 EmitStartPt = I; 231 LastLocalValue = I; 232 } 233 234 /// \brief Set the current block to which generated machine instructions will 235 /// be appended, and clear the local CSE map. 236 void startNewBlock(); 237 238 /// \brief Return current debug location information. getCurDebugLoc()239 DebugLoc getCurDebugLoc() const { return DbgLoc; } 240 241 /// \brief Do "fast" instruction selection for function arguments and append 242 /// the machine instructions to the current block. Returns true when 243 /// successful. 244 bool lowerArguments(); 245 246 /// \brief Do "fast" instruction selection for the given LLVM IR instruction 247 /// and append the generated machine instructions to the current block. 248 /// Returns true if selection was successful. 249 bool selectInstruction(const Instruction *I); 250 251 /// \brief Do "fast" instruction selection for the given LLVM IR operator 252 /// (Instruction or ConstantExpr), and append generated machine instructions 253 /// to the current block. Return true if selection was successful. 254 bool selectOperator(const User *I, unsigned Opcode); 255 256 /// \brief Create a virtual register and arrange for it to be assigned the 257 /// value for the given LLVM value. 258 unsigned getRegForValue(const Value *V); 259 260 /// \brief Look up the value to see if its value is already cached in a 261 /// register. It may be defined by instructions across blocks or defined 262 /// locally. 263 unsigned lookUpRegForValue(const Value *V); 264 265 /// \brief This is a wrapper around getRegForValue that also takes care of 266 /// truncating or sign-extending the given getelementptr index value. 267 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); 268 269 /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note 270 /// that we could have a sequence where multiple LLVM IR instructions are 271 /// folded into the same machineinstr. For example we could have: 272 /// 273 /// A: x = load i32 *P 274 /// B: y = icmp A, 42 275 /// C: br y, ... 276 /// 277 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B" 278 /// (and any other folded instructions) because it is between A and C. 279 /// 280 /// If we succeed folding, return true. 281 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst); 282 283 /// \brief The specified machine instr operand is a vreg, and that vreg is 284 /// being provided by the specified load instruction. If possible, try to 285 /// fold the load as an operand to the instruction, returning true if 286 /// possible. 287 /// 288 /// This method should be implemented by targets. tryToFoldLoadIntoMI(MachineInstr *,unsigned,const LoadInst *)289 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/, 290 const LoadInst * /*LI*/) { 291 return false; 292 } 293 294 /// \brief Reset InsertPt to prepare for inserting instructions into the 295 /// current block. 296 void recomputeInsertPt(); 297 298 /// \brief Remove all dead instructions between the I and E. 299 void removeDeadCode(MachineBasicBlock::iterator I, 300 MachineBasicBlock::iterator E); 301 302 struct SavePoint { 303 MachineBasicBlock::iterator InsertPt; 304 DebugLoc DL; 305 }; 306 307 /// \brief Prepare InsertPt to begin inserting instructions into the local 308 /// value area and return the old insert position. 309 SavePoint enterLocalValueArea(); 310 311 /// \brief Reset InsertPt to the given old insert position. 312 void leaveLocalValueArea(SavePoint Old); 313 314 virtual ~FastISel(); 315 316 protected: 317 explicit FastISel(FunctionLoweringInfo &FuncInfo, 318 const TargetLibraryInfo *LibInfo, 319 bool SkipTargetIndependentISel = false); 320 321 /// \brief This method is called by target-independent code when the normal 322 /// FastISel process fails to select an instruction. This gives targets a 323 /// chance to emit code for anything that doesn't fit into FastISel's 324 /// framework. It returns true if it was successful. 325 virtual bool fastSelectInstruction(const Instruction *I) = 0; 326 327 /// \brief This method is called by target-independent code to do target- 328 /// specific argument lowering. It returns true if it was successful. 329 virtual bool fastLowerArguments(); 330 331 /// \brief This method is called by target-independent code to do target- 332 /// specific call lowering. It returns true if it was successful. 333 virtual bool fastLowerCall(CallLoweringInfo &CLI); 334 335 /// \brief This method is called by target-independent code to do target- 336 /// specific intrinsic lowering. It returns true if it was successful. 337 virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II); 338 339 /// \brief This method is called by target-independent code to request that an 340 /// instruction with the given type and opcode be emitted. 341 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode); 342 343 /// \brief This method is called by target-independent code to request that an 344 /// instruction with the given type, opcode, and register operand be emitted. 345 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 346 bool Op0IsKill); 347 348 /// \brief This method is called by target-independent code to request that an 349 /// instruction with the given type, opcode, and register operands be emitted. 350 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 351 bool Op0IsKill, unsigned Op1, bool Op1IsKill); 352 353 /// \brief This method is called by target-independent code to request that an 354 /// instruction with the given type, opcode, and register and immediate 355 // operands be emitted. 356 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 357 bool Op0IsKill, uint64_t Imm); 358 359 /// \brief This method is called by target-independent code to request that an 360 /// instruction with the given type, opcode, and register and floating-point 361 /// immediate operands be emitted. 362 virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 363 bool Op0IsKill, const ConstantFP *FPImm); 364 365 /// \brief This method is called by target-independent code to request that an 366 /// instruction with the given type, opcode, and register and immediate 367 /// operands be emitted. 368 virtual unsigned fastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode, 369 unsigned Op0, bool Op0IsKill, unsigned Op1, 370 bool Op1IsKill, uint64_t Imm); 371 372 /// \brief This method is a wrapper of fastEmit_ri. 373 /// 374 /// It first tries to emit an instruction with an immediate operand using 375 /// fastEmit_ri. If that fails, it materializes the immediate into a register 376 /// and try fastEmit_rr instead. 377 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, 378 uint64_t Imm, MVT ImmType); 379 380 /// \brief This method is called by target-independent code to request that an 381 /// instruction with the given type, opcode, and immediate operand be emitted. 382 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm); 383 384 /// \brief This method is called by target-independent code to request that an 385 /// instruction with the given type, opcode, and floating-point immediate 386 /// operand be emitted. 387 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, 388 const ConstantFP *FPImm); 389 390 /// \brief Emit a MachineInstr with no operands and a result register in the 391 /// given register class. 392 unsigned fastEmitInst_(unsigned MachineInstOpcode, 393 const TargetRegisterClass *RC); 394 395 /// \brief Emit a MachineInstr with one register operand and a result register 396 /// in the given register class. 397 unsigned fastEmitInst_r(unsigned MachineInstOpcode, 398 const TargetRegisterClass *RC, unsigned Op0, 399 bool Op0IsKill); 400 401 /// \brief Emit a MachineInstr with two register operands and a result 402 /// register in the given register class. 403 unsigned fastEmitInst_rr(unsigned MachineInstOpcode, 404 const TargetRegisterClass *RC, unsigned Op0, 405 bool Op0IsKill, unsigned Op1, bool Op1IsKill); 406 407 /// \brief Emit a MachineInstr with three register operands and a result 408 /// register in the given register class. 409 unsigned fastEmitInst_rrr(unsigned MachineInstOpcode, 410 const TargetRegisterClass *RC, unsigned Op0, 411 bool Op0IsKill, unsigned Op1, bool Op1IsKill, 412 unsigned Op2, bool Op2IsKill); 413 414 /// \brief Emit a MachineInstr with a register operand, an immediate, and a 415 /// result register in the given register class. 416 unsigned fastEmitInst_ri(unsigned MachineInstOpcode, 417 const TargetRegisterClass *RC, unsigned Op0, 418 bool Op0IsKill, uint64_t Imm); 419 420 /// \brief Emit a MachineInstr with one register operand and two immediate 421 /// operands. 422 unsigned fastEmitInst_rii(unsigned MachineInstOpcode, 423 const TargetRegisterClass *RC, unsigned Op0, 424 bool Op0IsKill, uint64_t Imm1, uint64_t Imm2); 425 426 /// \brief Emit a MachineInstr with a floating point immediate, and a result 427 /// register in the given register class. 428 unsigned fastEmitInst_f(unsigned MachineInstOpcode, 429 const TargetRegisterClass *RC, 430 const ConstantFP *FPImm); 431 432 /// \brief Emit a MachineInstr with two register operands, an immediate, and a 433 /// result register in the given register class. 434 unsigned fastEmitInst_rri(unsigned MachineInstOpcode, 435 const TargetRegisterClass *RC, unsigned Op0, 436 bool Op0IsKill, unsigned Op1, bool Op1IsKill, 437 uint64_t Imm); 438 439 /// \brief Emit a MachineInstr with a single immediate operand, and a result 440 /// register in the given register class. 441 unsigned fastEmitInst_i(unsigned MachineInstrOpcode, 442 const TargetRegisterClass *RC, uint64_t Imm); 443 444 /// \brief Emit a MachineInstr for an extract_subreg from a specified index of 445 /// a superregister to a specified type. 446 unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, 447 uint32_t Idx); 448 449 /// \brief Emit MachineInstrs to compute the value of Op with all but the 450 /// least significant bit set to zero. 451 unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill); 452 453 /// \brief Emit an unconditional branch to the given block, unless it is the 454 /// immediate (fall-through) successor, and update the CFG. 455 void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL); 456 457 /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight 458 /// and adds TrueMBB and FalseMBB to the successor list. 459 void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, 460 MachineBasicBlock *FalseMBB); 461 462 /// \brief Update the value map to include the new mapping for this 463 /// instruction, or insert an extra copy to get the result in a previous 464 /// determined register. 465 /// 466 /// NOTE: This is only necessary because we might select a block that uses a 467 /// value before we select the block that defines the value. It might be 468 /// possible to fix this by selecting blocks in reverse postorder. 469 void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1); 470 471 unsigned createResultReg(const TargetRegisterClass *RC); 472 473 /// \brief Try to constrain Op so that it is usable by argument OpNum of the 474 /// provided MCInstrDesc. If this fails, create a new virtual register in the 475 /// correct class and COPY the value there. 476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, 477 unsigned OpNum); 478 479 /// \brief Emit a constant in a register using target-specific logic, such as 480 /// constant pool loads. fastMaterializeConstant(const Constant * C)481 virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; } 482 483 /// \brief Emit an alloca address in a register using target-specific logic. fastMaterializeAlloca(const AllocaInst * C)484 virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; } 485 486 /// \brief Emit the floating-point constant +0.0 in a register using target- 487 /// specific logic. fastMaterializeFloatZero(const ConstantFP * CF)488 virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) { 489 return 0; 490 } 491 492 /// \brief Check if \c Add is an add that can be safely folded into \c GEP. 493 /// 494 /// \c Add can be folded into \c GEP if: 495 /// - \c Add is an add, 496 /// - \c Add's size matches \c GEP's, 497 /// - \c Add is in the same basic block as \c GEP, and 498 /// - \c Add has a constant operand. 499 bool canFoldAddIntoGEP(const User *GEP, const Value *Add); 500 501 /// \brief Test whether the given value has exactly one use. 502 bool hasTrivialKill(const Value *V); 503 504 /// \brief Create a machine mem operand from the given instruction. 505 MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const; 506 507 CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const; 508 509 bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs); 510 bool lowerCallTo(const CallInst *CI, const char *SymbolName, 511 unsigned NumArgs); 512 bool lowerCallTo(CallLoweringInfo &CLI); 513 isCommutativeIntrinsic(IntrinsicInst const * II)514 bool isCommutativeIntrinsic(IntrinsicInst const *II) { 515 switch (II->getIntrinsicID()) { 516 case Intrinsic::sadd_with_overflow: 517 case Intrinsic::uadd_with_overflow: 518 case Intrinsic::smul_with_overflow: 519 case Intrinsic::umul_with_overflow: 520 return true; 521 default: 522 return false; 523 } 524 } 525 526 527 bool lowerCall(const CallInst *I); 528 /// \brief Select and emit code for a binary operator instruction, which has 529 /// an opcode which directly corresponds to the given ISD opcode. 530 bool selectBinaryOp(const User *I, unsigned ISDOpcode); 531 bool selectFNeg(const User *I); 532 bool selectGetElementPtr(const User *I); 533 bool selectStackmap(const CallInst *I); 534 bool selectPatchpoint(const CallInst *I); 535 bool selectCall(const User *Call); 536 bool selectIntrinsicCall(const IntrinsicInst *II); 537 bool selectBitCast(const User *I); 538 bool selectCast(const User *I, unsigned Opcode); 539 bool selectExtractValue(const User *I); 540 bool selectInsertValue(const User *I); 541 542 private: 543 /// \brief Handle PHI nodes in successor blocks. 544 /// 545 /// Emit code to ensure constants are copied into registers when needed. 546 /// Remember the virtual registers that need to be added to the Machine PHI 547 /// nodes as input. We cannot just directly add them, because expansion might 548 /// result in multiple MBB's for one BB. As such, the start of the BB might 549 /// correspond to a different MBB than the end. 550 bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 551 552 /// \brief Helper for materializeRegForValue to materialize a constant in a 553 /// target-independent way. 554 unsigned materializeConstant(const Value *V, MVT VT); 555 556 /// \brief Helper for getRegForVale. This function is called when the value 557 /// isn't already available in a register and must be materialized with new 558 /// instructions. 559 unsigned materializeRegForValue(const Value *V, MVT VT); 560 561 /// \brief Clears LocalValueMap and moves the area for the new local variables 562 /// to the beginning of the block. It helps to avoid spilling cached variables 563 /// across heavy instructions like calls. 564 void flushLocalValueMap(); 565 566 /// \brief Removes dead local value instructions after SavedLastLocalvalue. 567 void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue); 568 569 /// \brief Insertion point before trying to select the current instruction. 570 MachineBasicBlock::iterator SavedInsertPt; 571 572 /// \brief Add a stackmap or patchpoint intrinsic call's live variable 573 /// operands to a stackmap or patchpoint machine instruction. 574 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops, 575 const CallInst *CI, unsigned StartIdx); 576 bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs, 577 const Value *Callee, bool ForceRetVoidTy, 578 CallLoweringInfo &CLI); 579 }; 580 581 } // end namespace llvm 582 583 #endif 584