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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineOperand class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
15 #define LLVM_CODEGEN_MACHINEOPERAND_H
16 
17 #include "llvm/Support/DataTypes.h"
18 #include <cassert>
19 
20 namespace llvm {
21 
22 class BlockAddress;
23 class ConstantFP;
24 class ConstantInt;
25 class GlobalValue;
26 class MachineBasicBlock;
27 class MachineInstr;
28 class MachineRegisterInfo;
29 class MDNode;
30 class ModuleSlotTracker;
31 class TargetMachine;
32 class TargetRegisterInfo;
33 class hash_code;
34 class raw_ostream;
35 class MCSymbol;
36 
37 /// MachineOperand class - Representation of each machine instruction operand.
38 ///
39 /// This class isn't a POD type because it has a private constructor, but its
40 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
41 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
42 /// not having to call the MachineOperand destructor.
43 ///
44 class MachineOperand {
45 public:
46   enum MachineOperandType : unsigned char {
47     MO_Register,          ///< Register operand.
48     MO_Immediate,         ///< Immediate operand
49     MO_CImmediate,        ///< Immediate >64bit operand
50     MO_FPImmediate,       ///< Floating-point immediate operand
51     MO_MachineBasicBlock, ///< MachineBasicBlock reference
52     MO_FrameIndex,        ///< Abstract Stack Frame Index
53     MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
54     MO_TargetIndex,       ///< Target-dependent index+offset operand.
55     MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
56     MO_ExternalSymbol,    ///< Name of external global symbol
57     MO_GlobalAddress,     ///< Address of a global value
58     MO_BlockAddress,      ///< Address of a basic block
59     MO_RegisterMask,      ///< Mask of preserved registers.
60     MO_RegisterLiveOut,   ///< Mask of live-out registers.
61     MO_Metadata,          ///< Metadata reference (for debug info)
62     MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
63     MO_CFIIndex           ///< MCCFIInstruction index.
64   };
65 
66 private:
67   /// OpKind - Specify what kind of operand this is.  This discriminates the
68   /// union.
69   MachineOperandType OpKind : 8;
70 
71   /// Subregister number for MO_Register.  A value of 0 indicates the
72   /// MO_Register has no subReg.
73   ///
74   /// For all other kinds of operands, this field holds target-specific flags.
75   unsigned SubReg_TargetFlags : 12;
76 
77   /// TiedTo - Non-zero when this register operand is tied to another register
78   /// operand. The encoding of this field is described in the block comment
79   /// before MachineInstr::tieOperands().
80   unsigned char TiedTo : 4;
81 
82   /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
83   /// operands.
84 
85   /// IsDef - True if this is a def, false if this is a use of the register.
86   ///
87   bool IsDef : 1;
88 
89   /// IsImp - True if this is an implicit def or use, false if it is explicit.
90   ///
91   bool IsImp : 1;
92 
93   /// IsKill - True if this instruction is the last use of the register on this
94   /// path through the function.  This is only valid on uses of registers.
95   bool IsKill : 1;
96 
97   /// IsDead - True if this register is never used by a subsequent instruction.
98   /// This is only valid on definitions of registers.
99   bool IsDead : 1;
100 
101   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
102   /// read value doesn't matter.  This flag can be set on both use and def
103   /// operands.  On a sub-register def operand, it refers to the part of the
104   /// register that isn't written.  On a full-register def operand, it is a
105   /// noop.  See readsReg().
106   ///
107   /// This is only valid on registers.
108   ///
109   /// Note that an instruction may have multiple <undef> operands referring to
110   /// the same register.  In that case, the instruction may depend on those
111   /// operands reading the same dont-care value.  For example:
112   ///
113   ///   %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
114   ///
115   /// Any register can be used for %vreg2, and its value doesn't matter, but
116   /// the two operands must be the same register.
117   ///
118   bool IsUndef : 1;
119 
120   /// IsInternalRead - True if this operand reads a value that was defined
121   /// inside the same instruction or bundle.  This flag can be set on both use
122   /// and def operands.  On a sub-register def operand, it refers to the part
123   /// of the register that isn't written.  On a full-register def operand, it
124   /// is a noop.
125   ///
126   /// When this flag is set, the instruction bundle must contain at least one
127   /// other def of the register.  If multiple instructions in the bundle define
128   /// the register, the meaning is target-defined.
129   bool IsInternalRead : 1;
130 
131   /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
132   /// by the MachineInstr before all input registers are read.  This is used to
133   /// model the GCC inline asm '&' constraint modifier.
134   bool IsEarlyClobber : 1;
135 
136   /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
137   /// not a real instruction.  Such uses should be ignored during codegen.
138   bool IsDebug : 1;
139 
140   /// SmallContents - This really should be part of the Contents union, but
141   /// lives out here so we can get a better packed struct.
142   /// MO_Register: Register number.
143   /// OffsetedInfo: Low bits of offset.
144   union {
145     unsigned RegNo;           // For MO_Register.
146     unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
147   } SmallContents;
148 
149   /// ParentMI - This is the instruction that this operand is embedded into.
150   /// This is valid for all operand types, when the operand is in an instr.
151   MachineInstr *ParentMI;
152 
153   /// Contents union - This contains the payload for the various operand types.
154   union {
155     MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
156     const ConstantFP *CFP;   // For MO_FPImmediate.
157     const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
158     int64_t ImmVal;          // For MO_Immediate.
159     const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
160     const MDNode *MD;        // For MO_Metadata.
161     MCSymbol *Sym;           // For MO_MCSymbol.
162     unsigned CFIIndex;       // For MO_CFI.
163 
164     struct {                  // For MO_Register.
165       // Register number is in SmallContents.RegNo.
166       MachineOperand *Prev;   // Access list for register. See MRI.
167       MachineOperand *Next;
168     } Reg;
169 
170     /// OffsetedInfo - This struct contains the offset and an object identifier.
171     /// this represent the object as with an optional offset from it.
172     struct {
173       union {
174         int Index;                // For MO_*Index - The index itself.
175         const char *SymbolName;   // For MO_ExternalSymbol.
176         const GlobalValue *GV;    // For MO_GlobalAddress.
177         const BlockAddress *BA;   // For MO_BlockAddress.
178       } Val;
179       // Low bits of offset are in SmallContents.OffsetLo.
180       int OffsetHi;               // An offset from the object, high 32 bits.
181     } OffsetedInfo;
182   } Contents;
183 
MachineOperand(MachineOperandType K)184   explicit MachineOperand(MachineOperandType K)
185     : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {}
186 public:
187   /// getType - Returns the MachineOperandType for this operand.
188   ///
getType()189   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
190 
getTargetFlags()191   unsigned getTargetFlags() const {
192     return isReg() ? 0 : SubReg_TargetFlags;
193   }
setTargetFlags(unsigned F)194   void setTargetFlags(unsigned F) {
195     assert(!isReg() && "Register operands can't have target flags");
196     SubReg_TargetFlags = F;
197     assert(SubReg_TargetFlags == F && "Target flags out of range");
198   }
addTargetFlag(unsigned F)199   void addTargetFlag(unsigned F) {
200     assert(!isReg() && "Register operands can't have target flags");
201     SubReg_TargetFlags |= F;
202     assert((SubReg_TargetFlags & F) && "Target flags out of range");
203   }
204 
205 
206   /// getParent - Return the instruction that this operand belongs to.
207   ///
getParent()208   MachineInstr *getParent() { return ParentMI; }
getParent()209   const MachineInstr *getParent() const { return ParentMI; }
210 
211   /// clearParent - Reset the parent pointer.
212   ///
213   /// The MachineOperand copy constructor also copies ParentMI, expecting the
214   /// original to be deleted. If a MachineOperand is ever stored outside a
215   /// MachineInstr, the parent pointer must be cleared.
216   ///
217   /// Never call clearParent() on an operand in a MachineInstr.
218   ///
clearParent()219   void clearParent() { ParentMI = nullptr; }
220 
221   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr) const;
222   void print(raw_ostream &os, ModuleSlotTracker &MST,
223              const TargetRegisterInfo *TRI = nullptr) const;
224 
225   //===--------------------------------------------------------------------===//
226   // Accessors that tell you what kind of MachineOperand you're looking at.
227   //===--------------------------------------------------------------------===//
228 
229   /// isReg - Tests if this is a MO_Register operand.
isReg()230   bool isReg() const { return OpKind == MO_Register; }
231   /// isImm - Tests if this is a MO_Immediate operand.
isImm()232   bool isImm() const { return OpKind == MO_Immediate; }
233   /// isCImm - Test if this is a MO_CImmediate operand.
isCImm()234   bool isCImm() const { return OpKind == MO_CImmediate; }
235   /// isFPImm - Tests if this is a MO_FPImmediate operand.
isFPImm()236   bool isFPImm() const { return OpKind == MO_FPImmediate; }
237   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
isMBB()238   bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
239   /// isFI - Tests if this is a MO_FrameIndex operand.
isFI()240   bool isFI() const { return OpKind == MO_FrameIndex; }
241   /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
isCPI()242   bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
243   /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
isTargetIndex()244   bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
245   /// isJTI - Tests if this is a MO_JumpTableIndex operand.
isJTI()246   bool isJTI() const { return OpKind == MO_JumpTableIndex; }
247   /// isGlobal - Tests if this is a MO_GlobalAddress operand.
isGlobal()248   bool isGlobal() const { return OpKind == MO_GlobalAddress; }
249   /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
isSymbol()250   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
251   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
isBlockAddress()252   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
253   /// isRegMask - Tests if this is a MO_RegisterMask operand.
isRegMask()254   bool isRegMask() const { return OpKind == MO_RegisterMask; }
255   /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
isRegLiveOut()256   bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
257   /// isMetadata - Tests if this is a MO_Metadata operand.
isMetadata()258   bool isMetadata() const { return OpKind == MO_Metadata; }
isMCSymbol()259   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
isCFIIndex()260   bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
261 
262   //===--------------------------------------------------------------------===//
263   // Accessors for Register Operands
264   //===--------------------------------------------------------------------===//
265 
266   /// getReg - Returns the register number.
getReg()267   unsigned getReg() const {
268     assert(isReg() && "This is not a register operand!");
269     return SmallContents.RegNo;
270   }
271 
getSubReg()272   unsigned getSubReg() const {
273     assert(isReg() && "Wrong MachineOperand accessor");
274     return SubReg_TargetFlags;
275   }
276 
isUse()277   bool isUse() const {
278     assert(isReg() && "Wrong MachineOperand accessor");
279     return !IsDef;
280   }
281 
isDef()282   bool isDef() const {
283     assert(isReg() && "Wrong MachineOperand accessor");
284     return IsDef;
285   }
286 
isImplicit()287   bool isImplicit() const {
288     assert(isReg() && "Wrong MachineOperand accessor");
289     return IsImp;
290   }
291 
isDead()292   bool isDead() const {
293     assert(isReg() && "Wrong MachineOperand accessor");
294     return IsDead;
295   }
296 
isKill()297   bool isKill() const {
298     assert(isReg() && "Wrong MachineOperand accessor");
299     return IsKill;
300   }
301 
isUndef()302   bool isUndef() const {
303     assert(isReg() && "Wrong MachineOperand accessor");
304     return IsUndef;
305   }
306 
isInternalRead()307   bool isInternalRead() const {
308     assert(isReg() && "Wrong MachineOperand accessor");
309     return IsInternalRead;
310   }
311 
isEarlyClobber()312   bool isEarlyClobber() const {
313     assert(isReg() && "Wrong MachineOperand accessor");
314     return IsEarlyClobber;
315   }
316 
isTied()317   bool isTied() const {
318     assert(isReg() && "Wrong MachineOperand accessor");
319     return TiedTo;
320   }
321 
isDebug()322   bool isDebug() const {
323     assert(isReg() && "Wrong MachineOperand accessor");
324     return IsDebug;
325   }
326 
327   /// readsReg - Returns true if this operand reads the previous value of its
328   /// register.  A use operand with the <undef> flag set doesn't read its
329   /// register.  A sub-register def implicitly reads the other parts of the
330   /// register being redefined unless the <undef> flag is set.
331   ///
332   /// This refers to reading the register value from before the current
333   /// instruction or bundle. Internal bundle reads are not included.
readsReg()334   bool readsReg() const {
335     assert(isReg() && "Wrong MachineOperand accessor");
336     return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
337   }
338 
339   //===--------------------------------------------------------------------===//
340   // Mutators for Register Operands
341   //===--------------------------------------------------------------------===//
342 
343   /// Change the register this operand corresponds to.
344   ///
345   void setReg(unsigned Reg);
346 
setSubReg(unsigned subReg)347   void setSubReg(unsigned subReg) {
348     assert(isReg() && "Wrong MachineOperand accessor");
349     SubReg_TargetFlags = subReg;
350     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
351   }
352 
353   /// substVirtReg - Substitute the current register with the virtual
354   /// subregister Reg:SubReg. Take any existing SubReg index into account,
355   /// using TargetRegisterInfo to compose the subreg indices if necessary.
356   /// Reg must be a virtual register, SubIdx can be 0.
357   ///
358   void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
359 
360   /// substPhysReg - Substitute the current register with the physical register
361   /// Reg, taking any existing SubReg into account. For instance,
362   /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
363   ///
364   void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
365 
366   void setIsUse(bool Val = true) { setIsDef(!Val); }
367 
368   void setIsDef(bool Val = true);
369 
370   void setImplicit(bool Val = true) {
371     assert(isReg() && "Wrong MachineOperand accessor");
372     IsImp = Val;
373   }
374 
375   void setIsKill(bool Val = true) {
376     assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
377     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
378     IsKill = Val;
379   }
380 
381   void setIsDead(bool Val = true) {
382     assert(isReg() && IsDef && "Wrong MachineOperand accessor");
383     IsDead = Val;
384   }
385 
386   void setIsUndef(bool Val = true) {
387     assert(isReg() && "Wrong MachineOperand accessor");
388     IsUndef = Val;
389   }
390 
391   void setIsInternalRead(bool Val = true) {
392     assert(isReg() && "Wrong MachineOperand accessor");
393     IsInternalRead = Val;
394   }
395 
396   void setIsEarlyClobber(bool Val = true) {
397     assert(isReg() && IsDef && "Wrong MachineOperand accessor");
398     IsEarlyClobber = Val;
399   }
400 
401   void setIsDebug(bool Val = true) {
402     assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
403     IsDebug = Val;
404   }
405 
406   //===--------------------------------------------------------------------===//
407   // Accessors for various operand types.
408   //===--------------------------------------------------------------------===//
409 
getImm()410   int64_t getImm() const {
411     assert(isImm() && "Wrong MachineOperand accessor");
412     return Contents.ImmVal;
413   }
414 
getCImm()415   const ConstantInt *getCImm() const {
416     assert(isCImm() && "Wrong MachineOperand accessor");
417     return Contents.CI;
418   }
419 
getFPImm()420   const ConstantFP *getFPImm() const {
421     assert(isFPImm() && "Wrong MachineOperand accessor");
422     return Contents.CFP;
423   }
424 
getMBB()425   MachineBasicBlock *getMBB() const {
426     assert(isMBB() && "Wrong MachineOperand accessor");
427     return Contents.MBB;
428   }
429 
getIndex()430   int getIndex() const {
431     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
432            "Wrong MachineOperand accessor");
433     return Contents.OffsetedInfo.Val.Index;
434   }
435 
getGlobal()436   const GlobalValue *getGlobal() const {
437     assert(isGlobal() && "Wrong MachineOperand accessor");
438     return Contents.OffsetedInfo.Val.GV;
439   }
440 
getBlockAddress()441   const BlockAddress *getBlockAddress() const {
442     assert(isBlockAddress() && "Wrong MachineOperand accessor");
443     return Contents.OffsetedInfo.Val.BA;
444   }
445 
getMCSymbol()446   MCSymbol *getMCSymbol() const {
447     assert(isMCSymbol() && "Wrong MachineOperand accessor");
448     return Contents.Sym;
449   }
450 
getCFIIndex()451   unsigned getCFIIndex() const {
452     assert(isCFIIndex() && "Wrong MachineOperand accessor");
453     return Contents.CFIIndex;
454   }
455 
456   /// Return the offset from the symbol in this operand. This always returns 0
457   /// for ExternalSymbol operands.
getOffset()458   int64_t getOffset() const {
459     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
460             isTargetIndex() || isBlockAddress()) &&
461            "Wrong MachineOperand accessor");
462     return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
463            SmallContents.OffsetLo;
464   }
465 
getSymbolName()466   const char *getSymbolName() const {
467     assert(isSymbol() && "Wrong MachineOperand accessor");
468     return Contents.OffsetedInfo.Val.SymbolName;
469   }
470 
471   /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
472   /// It is sometimes necessary to detach the register mask pointer from its
473   /// machine operand. This static method can be used for such detached bit
474   /// mask pointers.
clobbersPhysReg(const uint32_t * RegMask,unsigned PhysReg)475   static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
476     // See TargetRegisterInfo.h.
477     assert(PhysReg < (1u << 30) && "Not a physical register");
478     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
479   }
480 
481   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
clobbersPhysReg(unsigned PhysReg)482   bool clobbersPhysReg(unsigned PhysReg) const {
483      return clobbersPhysReg(getRegMask(), PhysReg);
484   }
485 
486   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
487   /// operand.
getRegMask()488   const uint32_t *getRegMask() const {
489     assert(isRegMask() && "Wrong MachineOperand accessor");
490     return Contents.RegMask;
491   }
492 
493   /// getRegLiveOut - Returns a bit mask of live-out registers.
getRegLiveOut()494   const uint32_t *getRegLiveOut() const {
495     assert(isRegLiveOut() && "Wrong MachineOperand accessor");
496     return Contents.RegMask;
497   }
498 
getMetadata()499   const MDNode *getMetadata() const {
500     assert(isMetadata() && "Wrong MachineOperand accessor");
501     return Contents.MD;
502   }
503 
504   //===--------------------------------------------------------------------===//
505   // Mutators for various operand types.
506   //===--------------------------------------------------------------------===//
507 
setImm(int64_t immVal)508   void setImm(int64_t immVal) {
509     assert(isImm() && "Wrong MachineOperand mutator");
510     Contents.ImmVal = immVal;
511   }
512 
setFPImm(const ConstantFP * CFP)513   void setFPImm(const ConstantFP *CFP) {
514     assert(isFPImm() && "Wrong MachineOperand mutator");
515     Contents.CFP = CFP;
516   }
517 
setOffset(int64_t Offset)518   void setOffset(int64_t Offset) {
519     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
520             isTargetIndex() || isBlockAddress()) &&
521            "Wrong MachineOperand accessor");
522     SmallContents.OffsetLo = unsigned(Offset);
523     Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
524   }
525 
setIndex(int Idx)526   void setIndex(int Idx) {
527     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
528            "Wrong MachineOperand accessor");
529     Contents.OffsetedInfo.Val.Index = Idx;
530   }
531 
setMBB(MachineBasicBlock * MBB)532   void setMBB(MachineBasicBlock *MBB) {
533     assert(isMBB() && "Wrong MachineOperand accessor");
534     Contents.MBB = MBB;
535   }
536 
537   /// Sets value of register mask operand referencing Mask.  The
538   /// operand does not take ownership of the memory referenced by Mask, it must
539   /// remain valid for the lifetime of the operand. See CreateRegMask().
540   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
setRegMask(const uint32_t * RegMaskPtr)541   void setRegMask(const uint32_t *RegMaskPtr) {
542     assert(isRegMask() && "Wrong MachineOperand mutator");
543     Contents.RegMask = RegMaskPtr;
544   }
545 
546   //===--------------------------------------------------------------------===//
547   // Other methods.
548   //===--------------------------------------------------------------------===//
549 
550   /// isIdenticalTo - Return true if this operand is identical to the specified
551   /// operand. Note: This method ignores isKill and isDead properties.
552   bool isIdenticalTo(const MachineOperand &Other) const;
553 
554   /// \brief MachineOperand hash_value overload.
555   ///
556   /// Note that this includes the same information in the hash that
557   /// isIdenticalTo uses for comparison. It is thus suited for use in hash
558   /// tables which use that function for equality comparisons only.
559   friend hash_code hash_value(const MachineOperand &MO);
560 
561   /// ChangeToImmediate - Replace this operand with a new immediate operand of
562   /// the specified value.  If an operand is known to be an immediate already,
563   /// the setImm method should be used.
564   void ChangeToImmediate(int64_t ImmVal);
565 
566   /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
567   /// of the specified value.  If an operand is known to be an FP immediate
568   /// already, the setFPImm method should be used.
569   void ChangeToFPImmediate(const ConstantFP *FPImm);
570 
571   /// ChangeToES - Replace this operand with a new external symbol operand.
572   void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
573 
574   /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
575   void ChangeToMCSymbol(MCSymbol *Sym);
576 
577   /// ChangeToRegister - Replace this operand with a new register operand of
578   /// the specified value.  If an operand is known to be an register already,
579   /// the setReg method should be used.
580   void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
581                         bool isKill = false, bool isDead = false,
582                         bool isUndef = false, bool isDebug = false);
583 
584   //===--------------------------------------------------------------------===//
585   // Construction methods.
586   //===--------------------------------------------------------------------===//
587 
CreateImm(int64_t Val)588   static MachineOperand CreateImm(int64_t Val) {
589     MachineOperand Op(MachineOperand::MO_Immediate);
590     Op.setImm(Val);
591     return Op;
592   }
593 
CreateCImm(const ConstantInt * CI)594   static MachineOperand CreateCImm(const ConstantInt *CI) {
595     MachineOperand Op(MachineOperand::MO_CImmediate);
596     Op.Contents.CI = CI;
597     return Op;
598   }
599 
CreateFPImm(const ConstantFP * CFP)600   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
601     MachineOperand Op(MachineOperand::MO_FPImmediate);
602     Op.Contents.CFP = CFP;
603     return Op;
604   }
605 
606   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
607                                   bool isKill = false, bool isDead = false,
608                                   bool isUndef = false,
609                                   bool isEarlyClobber = false,
610                                   unsigned SubReg = 0,
611                                   bool isDebug = false,
612                                   bool isInternalRead = false) {
613     assert(!(isDead && !isDef) && "Dead flag on non-def");
614     assert(!(isKill && isDef) && "Kill flag on def");
615     MachineOperand Op(MachineOperand::MO_Register);
616     Op.IsDef = isDef;
617     Op.IsImp = isImp;
618     Op.IsKill = isKill;
619     Op.IsDead = isDead;
620     Op.IsUndef = isUndef;
621     Op.IsInternalRead = isInternalRead;
622     Op.IsEarlyClobber = isEarlyClobber;
623     Op.TiedTo = 0;
624     Op.IsDebug = isDebug;
625     Op.SmallContents.RegNo = Reg;
626     Op.Contents.Reg.Prev = nullptr;
627     Op.Contents.Reg.Next = nullptr;
628     Op.setSubReg(SubReg);
629     return Op;
630   }
631   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
632                                   unsigned char TargetFlags = 0) {
633     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
634     Op.setMBB(MBB);
635     Op.setTargetFlags(TargetFlags);
636     return Op;
637   }
CreateFI(int Idx)638   static MachineOperand CreateFI(int Idx) {
639     MachineOperand Op(MachineOperand::MO_FrameIndex);
640     Op.setIndex(Idx);
641     return Op;
642   }
643   static MachineOperand CreateCPI(unsigned Idx, int Offset,
644                                   unsigned char TargetFlags = 0) {
645     MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
646     Op.setIndex(Idx);
647     Op.setOffset(Offset);
648     Op.setTargetFlags(TargetFlags);
649     return Op;
650   }
651   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
652                                           unsigned char TargetFlags = 0) {
653     MachineOperand Op(MachineOperand::MO_TargetIndex);
654     Op.setIndex(Idx);
655     Op.setOffset(Offset);
656     Op.setTargetFlags(TargetFlags);
657     return Op;
658   }
659   static MachineOperand CreateJTI(unsigned Idx,
660                                   unsigned char TargetFlags = 0) {
661     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
662     Op.setIndex(Idx);
663     Op.setTargetFlags(TargetFlags);
664     return Op;
665   }
666   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
667                                  unsigned char TargetFlags = 0) {
668     MachineOperand Op(MachineOperand::MO_GlobalAddress);
669     Op.Contents.OffsetedInfo.Val.GV = GV;
670     Op.setOffset(Offset);
671     Op.setTargetFlags(TargetFlags);
672     return Op;
673   }
674   static MachineOperand CreateES(const char *SymName,
675                                  unsigned char TargetFlags = 0) {
676     MachineOperand Op(MachineOperand::MO_ExternalSymbol);
677     Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
678     Op.setOffset(0); // Offset is always 0.
679     Op.setTargetFlags(TargetFlags);
680     return Op;
681   }
682   static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
683                                  unsigned char TargetFlags = 0) {
684     MachineOperand Op(MachineOperand::MO_BlockAddress);
685     Op.Contents.OffsetedInfo.Val.BA = BA;
686     Op.setOffset(Offset);
687     Op.setTargetFlags(TargetFlags);
688     return Op;
689   }
690   /// CreateRegMask - Creates a register mask operand referencing Mask.  The
691   /// operand does not take ownership of the memory referenced by Mask, it must
692   /// remain valid for the lifetime of the operand.
693   ///
694   /// A RegMask operand represents a set of non-clobbered physical registers on
695   /// an instruction that clobbers many registers, typically a call.  The bit
696   /// mask has a bit set for each physreg that is preserved by this
697   /// instruction, as described in the documentation for
698   /// TargetRegisterInfo::getCallPreservedMask().
699   ///
700   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
701   ///
CreateRegMask(const uint32_t * Mask)702   static MachineOperand CreateRegMask(const uint32_t *Mask) {
703     assert(Mask && "Missing register mask");
704     MachineOperand Op(MachineOperand::MO_RegisterMask);
705     Op.Contents.RegMask = Mask;
706     return Op;
707   }
CreateRegLiveOut(const uint32_t * Mask)708   static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
709     assert(Mask && "Missing live-out register mask");
710     MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
711     Op.Contents.RegMask = Mask;
712     return Op;
713   }
CreateMetadata(const MDNode * Meta)714   static MachineOperand CreateMetadata(const MDNode *Meta) {
715     MachineOperand Op(MachineOperand::MO_Metadata);
716     Op.Contents.MD = Meta;
717     return Op;
718   }
719 
720   static MachineOperand CreateMCSymbol(MCSymbol *Sym,
721                                        unsigned char TargetFlags = 0) {
722     MachineOperand Op(MachineOperand::MO_MCSymbol);
723     Op.Contents.Sym = Sym;
724     Op.setOffset(0);
725     Op.setTargetFlags(TargetFlags);
726     return Op;
727   }
728 
CreateCFIIndex(unsigned CFIIndex)729   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
730     MachineOperand Op(MachineOperand::MO_CFIIndex);
731     Op.Contents.CFIIndex = CFIIndex;
732     return Op;
733   }
734 
735   friend class MachineInstr;
736   friend class MachineRegisterInfo;
737 private:
738   void removeRegFromUses();
739 
740   //===--------------------------------------------------------------------===//
741   // Methods for handling register use/def lists.
742   //===--------------------------------------------------------------------===//
743 
744   /// isOnRegUseList - Return true if this operand is on a register use/def list
745   /// or false if not.  This can only be called for register operands that are
746   /// part of a machine instruction.
isOnRegUseList()747   bool isOnRegUseList() const {
748     assert(isReg() && "Can only add reg operand to use lists");
749     return Contents.Reg.Prev != nullptr;
750   }
751 };
752 
753 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
754   MO.print(OS, nullptr);
755   return OS;
756 }
757 
758   // See friend declaration above. This additional declaration is required in
759   // order to compile LLVM with IBM xlC compiler.
760   hash_code hash_value(const MachineOperand &MO);
761 } // End llvm namespace
762 
763 #endif
764