1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
19
20 // FIXME: Is it easiest to fix this layering violation by moving the .inc
21 // #includes from AArch64MCTargetDesc.h to here?
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/MC/SubtargetFeature.h"
26 #include "llvm/Support/ErrorHandling.h"
27
28 namespace llvm {
29
getWRegFromXReg(unsigned Reg)30 inline static unsigned getWRegFromXReg(unsigned Reg) {
31 switch (Reg) {
32 case AArch64::X0: return AArch64::W0;
33 case AArch64::X1: return AArch64::W1;
34 case AArch64::X2: return AArch64::W2;
35 case AArch64::X3: return AArch64::W3;
36 case AArch64::X4: return AArch64::W4;
37 case AArch64::X5: return AArch64::W5;
38 case AArch64::X6: return AArch64::W6;
39 case AArch64::X7: return AArch64::W7;
40 case AArch64::X8: return AArch64::W8;
41 case AArch64::X9: return AArch64::W9;
42 case AArch64::X10: return AArch64::W10;
43 case AArch64::X11: return AArch64::W11;
44 case AArch64::X12: return AArch64::W12;
45 case AArch64::X13: return AArch64::W13;
46 case AArch64::X14: return AArch64::W14;
47 case AArch64::X15: return AArch64::W15;
48 case AArch64::X16: return AArch64::W16;
49 case AArch64::X17: return AArch64::W17;
50 case AArch64::X18: return AArch64::W18;
51 case AArch64::X19: return AArch64::W19;
52 case AArch64::X20: return AArch64::W20;
53 case AArch64::X21: return AArch64::W21;
54 case AArch64::X22: return AArch64::W22;
55 case AArch64::X23: return AArch64::W23;
56 case AArch64::X24: return AArch64::W24;
57 case AArch64::X25: return AArch64::W25;
58 case AArch64::X26: return AArch64::W26;
59 case AArch64::X27: return AArch64::W27;
60 case AArch64::X28: return AArch64::W28;
61 case AArch64::FP: return AArch64::W29;
62 case AArch64::LR: return AArch64::W30;
63 case AArch64::SP: return AArch64::WSP;
64 case AArch64::XZR: return AArch64::WZR;
65 }
66 // For anything else, return it unchanged.
67 return Reg;
68 }
69
getXRegFromWReg(unsigned Reg)70 inline static unsigned getXRegFromWReg(unsigned Reg) {
71 switch (Reg) {
72 case AArch64::W0: return AArch64::X0;
73 case AArch64::W1: return AArch64::X1;
74 case AArch64::W2: return AArch64::X2;
75 case AArch64::W3: return AArch64::X3;
76 case AArch64::W4: return AArch64::X4;
77 case AArch64::W5: return AArch64::X5;
78 case AArch64::W6: return AArch64::X6;
79 case AArch64::W7: return AArch64::X7;
80 case AArch64::W8: return AArch64::X8;
81 case AArch64::W9: return AArch64::X9;
82 case AArch64::W10: return AArch64::X10;
83 case AArch64::W11: return AArch64::X11;
84 case AArch64::W12: return AArch64::X12;
85 case AArch64::W13: return AArch64::X13;
86 case AArch64::W14: return AArch64::X14;
87 case AArch64::W15: return AArch64::X15;
88 case AArch64::W16: return AArch64::X16;
89 case AArch64::W17: return AArch64::X17;
90 case AArch64::W18: return AArch64::X18;
91 case AArch64::W19: return AArch64::X19;
92 case AArch64::W20: return AArch64::X20;
93 case AArch64::W21: return AArch64::X21;
94 case AArch64::W22: return AArch64::X22;
95 case AArch64::W23: return AArch64::X23;
96 case AArch64::W24: return AArch64::X24;
97 case AArch64::W25: return AArch64::X25;
98 case AArch64::W26: return AArch64::X26;
99 case AArch64::W27: return AArch64::X27;
100 case AArch64::W28: return AArch64::X28;
101 case AArch64::W29: return AArch64::FP;
102 case AArch64::W30: return AArch64::LR;
103 case AArch64::WSP: return AArch64::SP;
104 case AArch64::WZR: return AArch64::XZR;
105 }
106 // For anything else, return it unchanged.
107 return Reg;
108 }
109
getBRegFromDReg(unsigned Reg)110 static inline unsigned getBRegFromDReg(unsigned Reg) {
111 switch (Reg) {
112 case AArch64::D0: return AArch64::B0;
113 case AArch64::D1: return AArch64::B1;
114 case AArch64::D2: return AArch64::B2;
115 case AArch64::D3: return AArch64::B3;
116 case AArch64::D4: return AArch64::B4;
117 case AArch64::D5: return AArch64::B5;
118 case AArch64::D6: return AArch64::B6;
119 case AArch64::D7: return AArch64::B7;
120 case AArch64::D8: return AArch64::B8;
121 case AArch64::D9: return AArch64::B9;
122 case AArch64::D10: return AArch64::B10;
123 case AArch64::D11: return AArch64::B11;
124 case AArch64::D12: return AArch64::B12;
125 case AArch64::D13: return AArch64::B13;
126 case AArch64::D14: return AArch64::B14;
127 case AArch64::D15: return AArch64::B15;
128 case AArch64::D16: return AArch64::B16;
129 case AArch64::D17: return AArch64::B17;
130 case AArch64::D18: return AArch64::B18;
131 case AArch64::D19: return AArch64::B19;
132 case AArch64::D20: return AArch64::B20;
133 case AArch64::D21: return AArch64::B21;
134 case AArch64::D22: return AArch64::B22;
135 case AArch64::D23: return AArch64::B23;
136 case AArch64::D24: return AArch64::B24;
137 case AArch64::D25: return AArch64::B25;
138 case AArch64::D26: return AArch64::B26;
139 case AArch64::D27: return AArch64::B27;
140 case AArch64::D28: return AArch64::B28;
141 case AArch64::D29: return AArch64::B29;
142 case AArch64::D30: return AArch64::B30;
143 case AArch64::D31: return AArch64::B31;
144 }
145 // For anything else, return it unchanged.
146 return Reg;
147 }
148
149
getDRegFromBReg(unsigned Reg)150 static inline unsigned getDRegFromBReg(unsigned Reg) {
151 switch (Reg) {
152 case AArch64::B0: return AArch64::D0;
153 case AArch64::B1: return AArch64::D1;
154 case AArch64::B2: return AArch64::D2;
155 case AArch64::B3: return AArch64::D3;
156 case AArch64::B4: return AArch64::D4;
157 case AArch64::B5: return AArch64::D5;
158 case AArch64::B6: return AArch64::D6;
159 case AArch64::B7: return AArch64::D7;
160 case AArch64::B8: return AArch64::D8;
161 case AArch64::B9: return AArch64::D9;
162 case AArch64::B10: return AArch64::D10;
163 case AArch64::B11: return AArch64::D11;
164 case AArch64::B12: return AArch64::D12;
165 case AArch64::B13: return AArch64::D13;
166 case AArch64::B14: return AArch64::D14;
167 case AArch64::B15: return AArch64::D15;
168 case AArch64::B16: return AArch64::D16;
169 case AArch64::B17: return AArch64::D17;
170 case AArch64::B18: return AArch64::D18;
171 case AArch64::B19: return AArch64::D19;
172 case AArch64::B20: return AArch64::D20;
173 case AArch64::B21: return AArch64::D21;
174 case AArch64::B22: return AArch64::D22;
175 case AArch64::B23: return AArch64::D23;
176 case AArch64::B24: return AArch64::D24;
177 case AArch64::B25: return AArch64::D25;
178 case AArch64::B26: return AArch64::D26;
179 case AArch64::B27: return AArch64::D27;
180 case AArch64::B28: return AArch64::D28;
181 case AArch64::B29: return AArch64::D29;
182 case AArch64::B30: return AArch64::D30;
183 case AArch64::B31: return AArch64::D31;
184 }
185 // For anything else, return it unchanged.
186 return Reg;
187 }
188
189 namespace AArch64CC {
190
191 // The CondCodes constants map directly to the 4-bit encoding of the condition
192 // field for predicated instructions.
193 enum CondCode { // Meaning (integer) Meaning (floating-point)
194 EQ = 0x0, // Equal Equal
195 NE = 0x1, // Not equal Not equal, or unordered
196 HS = 0x2, // Unsigned higher or same >, ==, or unordered
197 LO = 0x3, // Unsigned lower Less than
198 MI = 0x4, // Minus, negative Less than
199 PL = 0x5, // Plus, positive or zero >, ==, or unordered
200 VS = 0x6, // Overflow Unordered
201 VC = 0x7, // No overflow Not unordered
202 HI = 0x8, // Unsigned higher Greater than, or unordered
203 LS = 0x9, // Unsigned lower or same Less than or equal
204 GE = 0xa, // Greater than or equal Greater than or equal
205 LT = 0xb, // Less than Less than, or unordered
206 GT = 0xc, // Greater than Greater than
207 LE = 0xd, // Less than or equal <, ==, or unordered
208 AL = 0xe, // Always (unconditional) Always (unconditional)
209 NV = 0xf, // Always (unconditional) Always (unconditional)
210 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
211 Invalid
212 };
213
getCondCodeName(CondCode Code)214 inline static const char *getCondCodeName(CondCode Code) {
215 switch (Code) {
216 default: llvm_unreachable("Unknown condition code");
217 case EQ: return "eq";
218 case NE: return "ne";
219 case HS: return "hs";
220 case LO: return "lo";
221 case MI: return "mi";
222 case PL: return "pl";
223 case VS: return "vs";
224 case VC: return "vc";
225 case HI: return "hi";
226 case LS: return "ls";
227 case GE: return "ge";
228 case LT: return "lt";
229 case GT: return "gt";
230 case LE: return "le";
231 case AL: return "al";
232 case NV: return "nv";
233 }
234 }
235
getInvertedCondCode(CondCode Code)236 inline static CondCode getInvertedCondCode(CondCode Code) {
237 // To reverse a condition it's necessary to only invert the low bit:
238
239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
240 }
241
242 /// Given a condition code, return NZCV flags that would satisfy that condition.
243 /// The flag bits are in the format expected by the ccmp instructions.
244 /// Note that many different flag settings can satisfy a given condition code,
245 /// this function just returns one of them.
getNZCVToSatisfyCondCode(CondCode Code)246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
247 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
248 enum { N = 8, Z = 4, C = 2, V = 1 };
249 switch (Code) {
250 default: llvm_unreachable("Unknown condition code");
251 case EQ: return Z; // Z == 1
252 case NE: return 0; // Z == 0
253 case HS: return C; // C == 1
254 case LO: return 0; // C == 0
255 case MI: return N; // N == 1
256 case PL: return 0; // N == 0
257 case VS: return V; // V == 1
258 case VC: return 0; // V == 0
259 case HI: return C; // C == 1 && Z == 0
260 case LS: return 0; // C == 0 || Z == 1
261 case GE: return 0; // N == V
262 case LT: return N; // N != V
263 case GT: return 0; // Z == 0 && N == V
264 case LE: return Z; // Z == 1 || N != V
265 }
266 }
267 } // end namespace AArch64CC
268
269 namespace AArch64AT{
270 struct AT {
271 const char *Name;
272 uint16_t Encoding;
273 };
274
275 #define GET_AT_DECL
276 #include "AArch64GenSystemOperands.inc"
277
278 }
279 namespace AArch64DB {
280 struct DB {
281 const char *Name;
282 uint16_t Encoding;
283 };
284
285 #define GET_DB_DECL
286 #include "AArch64GenSystemOperands.inc"
287 }
288
289 namespace AArch64DC {
290 struct DC {
291 const char *Name;
292 uint16_t Encoding;
293 };
294
295 #define GET_DC_DECL
296 #include "AArch64GenSystemOperands.inc"
297 }
298
299 namespace AArch64IC {
300 struct IC {
301 const char *Name;
302 uint16_t Encoding;
303 bool NeedsReg;
304 };
305 #define GET_IC_DECL
306 #include "AArch64GenSystemOperands.inc"
307 }
308
309 namespace AArch64ISB {
310 struct ISB {
311 const char *Name;
312 uint16_t Encoding;
313 };
314 #define GET_ISB_DECL
315 #include "AArch64GenSystemOperands.inc"
316 }
317
318 namespace AArch64PRFM {
319 struct PRFM {
320 const char *Name;
321 uint16_t Encoding;
322 };
323 #define GET_PRFM_DECL
324 #include "AArch64GenSystemOperands.inc"
325 }
326
327 namespace AArch64PState {
328 struct PState {
329 const char *Name;
330 uint16_t Encoding;
331 FeatureBitset FeaturesRequired;
332
haveFeaturesPState333 bool haveFeatures(FeatureBitset ActiveFeatures) const {
334 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
335 }
336 };
337 #define GET_PSTATE_DECL
338 #include "AArch64GenSystemOperands.inc"
339 }
340
341 namespace AArch64PSBHint {
342 struct PSB {
343 const char *Name;
344 uint16_t Encoding;
345 };
346 #define GET_PSB_DECL
347 #include "AArch64GenSystemOperands.inc"
348 }
349
350 namespace AArch64SE {
351 enum ShiftExtSpecifiers {
352 Invalid = -1,
353 LSL,
354 MSL,
355 LSR,
356 ASR,
357 ROR,
358
359 UXTB,
360 UXTH,
361 UXTW,
362 UXTX,
363
364 SXTB,
365 SXTH,
366 SXTW,
367 SXTX
368 };
369 }
370
371 namespace AArch64Layout {
372 enum VectorLayout {
373 Invalid = -1,
374 VL_8B,
375 VL_4H,
376 VL_2S,
377 VL_1D,
378
379 VL_16B,
380 VL_8H,
381 VL_4S,
382 VL_2D,
383
384 // Bare layout for the 128-bit vector
385 // (only show ".b", ".h", ".s", ".d" without vector number)
386 VL_B,
387 VL_H,
388 VL_S,
389 VL_D
390 };
391 }
392
393 inline static const char *
AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)394 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
395 switch (Layout) {
396 case AArch64Layout::VL_8B: return ".8b";
397 case AArch64Layout::VL_4H: return ".4h";
398 case AArch64Layout::VL_2S: return ".2s";
399 case AArch64Layout::VL_1D: return ".1d";
400 case AArch64Layout::VL_16B: return ".16b";
401 case AArch64Layout::VL_8H: return ".8h";
402 case AArch64Layout::VL_4S: return ".4s";
403 case AArch64Layout::VL_2D: return ".2d";
404 case AArch64Layout::VL_B: return ".b";
405 case AArch64Layout::VL_H: return ".h";
406 case AArch64Layout::VL_S: return ".s";
407 case AArch64Layout::VL_D: return ".d";
408 default: llvm_unreachable("Unknown Vector Layout");
409 }
410 }
411
412 inline static AArch64Layout::VectorLayout
AArch64StringToVectorLayout(StringRef LayoutStr)413 AArch64StringToVectorLayout(StringRef LayoutStr) {
414 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
415 .Case(".8b", AArch64Layout::VL_8B)
416 .Case(".4h", AArch64Layout::VL_4H)
417 .Case(".2s", AArch64Layout::VL_2S)
418 .Case(".1d", AArch64Layout::VL_1D)
419 .Case(".16b", AArch64Layout::VL_16B)
420 .Case(".8h", AArch64Layout::VL_8H)
421 .Case(".4s", AArch64Layout::VL_4S)
422 .Case(".2d", AArch64Layout::VL_2D)
423 .Case(".b", AArch64Layout::VL_B)
424 .Case(".h", AArch64Layout::VL_H)
425 .Case(".s", AArch64Layout::VL_S)
426 .Case(".d", AArch64Layout::VL_D)
427 .Default(AArch64Layout::Invalid);
428 }
429
430 namespace AArch64SysReg {
431 struct SysReg {
432 const char *Name;
433 unsigned Encoding;
434 bool Readable;
435 bool Writeable;
436 FeatureBitset FeaturesRequired;
437
haveFeaturesSysReg438 bool haveFeatures(FeatureBitset ActiveFeatures) const {
439 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
440 }
441 };
442
443 #define GET_SYSREG_DECL
444 #include "AArch64GenSystemOperands.inc"
445
446 const SysReg *lookupSysRegByName(StringRef);
447 const SysReg *lookupSysRegByEncoding(uint16_t);
448
449 uint32_t parseGenericRegister(StringRef Name);
450 std::string genericRegisterString(uint32_t Bits);
451 }
452
453 namespace AArch64TLBI {
454 struct TLBI {
455 const char *Name;
456 uint16_t Encoding;
457 bool NeedsReg;
458 };
459 #define GET_TLBI_DECL
460 #include "AArch64GenSystemOperands.inc"
461 }
462
463 namespace AArch64II {
464 /// Target Operand Flag enum.
465 enum TOF {
466 //===------------------------------------------------------------------===//
467 // AArch64 Specific MachineOperand flags.
468
469 MO_NO_FLAG,
470
471 MO_FRAGMENT = 0xf,
472
473 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
474 /// offset of the 4K page containing the symbol. This is used with the
475 /// ADRP instruction.
476 MO_PAGE = 1,
477
478 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
479 /// that symbol within a 4K page. This offset is added to the page address
480 /// to produce the complete address.
481 MO_PAGEOFF = 2,
482
483 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
484 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
485 MO_G3 = 3,
486
487 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
488 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
489 MO_G2 = 4,
490
491 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
492 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
493 MO_G1 = 5,
494
495 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
496 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
497 MO_G0 = 6,
498
499 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
500 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
501 /// by-12-bits instruction.
502 MO_HI12 = 7,
503
504 /// MO_GOT - This flag indicates that a symbol operand represents the
505 /// address of the GOT entry for the symbol, rather than the address of
506 /// the symbol itself.
507 MO_GOT = 0x10,
508
509 /// MO_NC - Indicates whether the linker is expected to check the symbol
510 /// reference for overflow. For example in an ADRP/ADD pair of relocations
511 /// the ADRP usually does check, but not the ADD.
512 MO_NC = 0x20,
513
514 /// MO_TLS - Indicates that the operand being accessed is some kind of
515 /// thread-local symbol. On Darwin, only one type of thread-local access
516 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
517 /// referee will affect interpretation.
518 MO_TLS = 0x40
519 };
520 } // end namespace AArch64II
521
522 } // end namespace llvm
523
524 #endif
525