| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
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| D | HexagonVLIWPacketizer.cpp | 422 int NewOpcode; in promoteToDotNew() local
432 int NewOpcode = HII->getDotOldOp(MI->getOpcode()); in demoteToDotOld() local
768 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
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| D | HexagonInstrInfo.cpp | 1333 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); in ReverseBranchCondition() local
3601 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in getDotNewPredOp() local
4231 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode()); in invertAndChangeJumpTarget() local
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.cpp | 232 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDILCFGStructurizer.cpp | 454 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd()
463 int NewOpcode, in insertInstrBefore()
476 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore()
488 MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) { in insertCondBranchBefore()
501 MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, in insertCondBranchBefore()
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| D | SIInstrInfo.cpp | 2506 unsigned NewOpcode = getVALUOp(Inst); in moveToVALU() local
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| D | SIISelLowering.cpp | 3262 unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet); in AdjustInstrPostInstrSelection() local
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 286 int NewOpcode; in eliminateFrameIndex() local
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 138 int NewOpcode; in InsertSPImmInst() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 618 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 273 int NewOpcode; in fixupIncDec() local
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| D | X86MCInstLower.cpp | 275 unsigned NewOpcode = 0; in SimplifyMOVSX() local
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| D | X86InstrInfo.cpp | 5049 unsigned NewOpcode = 0; in optimizeCompareInstr() local
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| D | X86ISelLowering.cpp | 29565 auto NewOpcode = IsFadd ? X86ISD::FHADD : X86ISD::FHSUB; in combineFaddFsub() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 967 unsigned NewOpcode = in EmitInstruction() local
981 unsigned NewOpcode = in EmitInstruction() local
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| D | PPCRegisterInfo.cpp | 908 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
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| D | PPCISelDAGToDAG.cpp | 4175 unsigned NewOpcode; in PeepholePPC64ZExt() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 458 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
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| D | SystemZInstrInfo.cpp | 97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
845 unsigned NewOpcode; in convertToThreeAddress() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 537 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 231 int NewOpcode = -1; in encodeInstruction() local
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 1670 std::string NewOpcode; in ParseInstruction() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3119 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3131 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2731 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 4206 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
4218 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
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