| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.cpp | 63 template <> const char *InstMIPS32Abs_d::Opcode = "abs.d"; member in Ice::MIPS32::InstMIPS32Abs_d
64 template <> const char *InstMIPS32Abs_s::Opcode = "abs.s"; member in Ice::MIPS32::InstMIPS32Abs_s
65 template <> const char *InstMIPS32Addi::Opcode = "addi"; member in Ice::MIPS32::InstMIPS32Addi
66 template <> const char *InstMIPS32Add::Opcode = "add"; member in Ice::MIPS32::InstMIPS32Add
67 template <> const char *InstMIPS32Add_d::Opcode = "add.d"; member in Ice::MIPS32::InstMIPS32Add_d
68 template <> const char *InstMIPS32Add_s::Opcode = "add.s"; member in Ice::MIPS32::InstMIPS32Add_s
69 template <> const char *InstMIPS32Addiu::Opcode = "addiu"; member in Ice::MIPS32::InstMIPS32Addiu
70 template <> const char *InstMIPS32Addu::Opcode = "addu"; member in Ice::MIPS32::InstMIPS32Addu
71 template <> const char *InstMIPS32And::Opcode = "and"; member in Ice::MIPS32::InstMIPS32And
72 template <> const char *InstMIPS32Andi::Opcode = "andi"; member in Ice::MIPS32::InstMIPS32Andi
[all …]
|
| D | IceAssemblerMIPS32.cpp | 207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel()
255 void AssemblerMIPS32::emitFtRsImm16(IValueT Opcode, const Operand *OpFt, in emitFtRsImm16()
268 void AssemblerMIPS32::emitRdRtSa(IValueT Opcode, const Operand *OpRd, in emitRdRtSa()
281 void AssemblerMIPS32::emitRdRsRt(IValueT Opcode, const Operand *OpRd, in emitRdRsRt()
295 void AssemblerMIPS32::emitCOP1Fcmp(IValueT Opcode, FPInstDataFormat Format, in emitCOP1Fcmp()
309 void AssemblerMIPS32::emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFsFd()
322 void AssemblerMIPS32::emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFtFsFd()
339 void AssemblerMIPS32::emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtRtFsFd()
[all …]
|
| D | IceInstARM32.cpp | 111 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode, in dumpOpcodePred()
162 void InstARM32Pred::emitUnaryopGPR(const char *Opcode, in emitUnaryopGPR()
177 void InstARM32Pred::emitUnaryopFP(const char *Opcode, FPSign Sign, in emitUnaryopFP()
200 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Instr, in emitTwoAddr()
214 void InstARM32Pred::emitThreeAddr(const char *Opcode, in emitThreeAddr()
230 void InstARM32::emitThreeAddrFP(const char *Opcode, FPSign SignType, in emitThreeAddrFP()
245 void InstARM32::emitFourAddrFP(const char *Opcode, FPSign SignType, in emitFourAddrFP()
261 void InstARM32Pred::emitFourAddr(const char *Opcode, const InstARM32Pred *Instr, in emitFourAddr()
313 void InstARM32Pred::emitCmpLike(const char *Opcode, const InstARM32Pred *Instr, in emitCmpLike()
1595 template <> const char *InstARM32Movt::Opcode = "movt"; member in Ice::ARM32::InstARM32Movt
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 187 bool isSALU(uint16_t Opcode) const { in isSALU()
195 bool isVALU(uint16_t Opcode) const { in isVALU()
203 bool isVMEM(uint16_t Opcode) const { in isVMEM()
211 bool isSOP1(uint16_t Opcode) const { in isSOP1()
219 bool isSOP2(uint16_t Opcode) const { in isSOP2()
227 bool isSOPC(uint16_t Opcode) const { in isSOPC()
235 bool isSOPK(uint16_t Opcode) const { in isSOPK()
243 bool isSOPP(uint16_t Opcode) const { in isSOPP()
251 bool isVOP1(uint16_t Opcode) const { in isVOP1()
259 bool isVOP2(uint16_t Opcode) const { in isVOP2()
[all …]
|
| D | AMDGPUTargetTransformInfo.cpp | 111 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
204 unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) { in getCFInstrCost()
215 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 59 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty) { in buildInstr()
72 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
77 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
88 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
95 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) { in buildInstr()
99 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 141 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
155 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
165 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
|
| D | LanaiRegisterInfo.cpp | 73 static bool isALUArithLoOpcode(unsigned Opcode) { in isALUArithLoOpcode()
89 static unsigned getOppositeALULoOpcode(unsigned Opcode) { in getOppositeALULoOpcode()
112 static unsigned getRRMOpcodeVariant(unsigned Opcode) { in getRRMOpcodeVariant()
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 74 void EmitInt8(unsigned Opcode) { in EmitInt8()
79 void EmitInt16(unsigned Opcode) { in EmitInt16()
85 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes()
|
| /external/libchrome/sandbox/win/src/sidestep/ |
| D | mini_disassembler_types.h | 140 struct Opcode { struct
162 SpecificOpcode opcode_if_f2_prefix_; argument
163 SpecificOpcode opcode_if_f3_prefix_; argument
164 SpecificOpcode opcode_if_66_prefix_; argument
170 const Opcode* table_; argument
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 53 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
76 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
269 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
294 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
412 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
483 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
496 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|
| D | ARMSelectionDAGInfo.h | 24 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
|
| /external/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 97 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
102 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
120 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
128 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
132 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
138 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
144 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
161 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
187 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh()
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) { in lowerRIEfLow()
85 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorLoad()
95 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorStore()
|
| D | SystemZShortenInst.cpp | 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 108 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
281 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
304 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
310 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
314 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { in getVectorInstrCost()
353 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
410 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstrInfo.h | 45 const MCInstrDesc &get(unsigned Opcode) const { in get()
51 const char *getName(unsigned Opcode) const { in getName()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 64 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, in getIntImmCost()
179 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
294 int AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, Type *Dst, in getExtractWithExtendCost()
349 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
375 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
435 int AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
466 int AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
495 int AArch64TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|
| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 47 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) { in getOperationCost()
260 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCodeSizeCost()
267 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
293 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, in getArithmeticInstrCost()
306 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { return 1; } in getCastInstrCost()
308 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst, in getExtractWithExtendCost()
313 unsigned getCFInstrCost(unsigned Opcode) { return 1; } in getCFInstrCost()
315 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
319 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { in getVectorInstrCost()
323 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
[all …]
|
| /external/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 50 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty, in getOperationCost()
212 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
226 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx, in getIntImmCost()
273 unsigned Opcode, Type *Ty, OperandValueKind Opd1Info, in getArithmeticInstrCost()
289 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, in getCastInstrCost()
296 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst, in getExtractWithExtendCost()
310 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
317 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
324 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
332 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost()
[all …]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyTargetTransformInfo.cpp | 47 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
74 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 66 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, in GetInstrType()
134 unsigned Opcode = Node->getMachineOpcode(); in getHazardType() local
233 unsigned Opcode = Node->getMachineOpcode(); in EmitInstruction() local
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard() local
85 unsigned Opcode = MI->getOpcode(); in EmitInstruction() local
|