1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
26
27 /* The public winsys interface header for the radeon driver. */
28
29 #include "pipebuffer/pb_buffer.h"
30
31 #include "amd/common/amd_family.h"
32
33 #define RADEON_FLUSH_ASYNC (1 << 0)
34 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
35
36 /* Tiling flags. */
37 enum radeon_bo_layout {
38 RADEON_LAYOUT_LINEAR = 0,
39 RADEON_LAYOUT_TILED,
40 RADEON_LAYOUT_SQUARETILED,
41
42 RADEON_LAYOUT_UNKNOWN
43 };
44
45 enum radeon_bo_domain { /* bitfield */
46 RADEON_DOMAIN_GTT = 2,
47 RADEON_DOMAIN_VRAM = 4,
48 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
49 };
50
51 enum radeon_bo_flag { /* bitfield */
52 RADEON_FLAG_GTT_WC = (1 << 0),
53 RADEON_FLAG_CPU_ACCESS = (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
55 RADEON_FLAG_HANDLE = (1 << 3), /* the buffer most not be suballocated */
56 };
57
58 enum radeon_bo_usage { /* bitfield */
59 RADEON_USAGE_READ = 2,
60 RADEON_USAGE_WRITE = 4,
61 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
62
63 /* The winsys ensures that the CS submission will be scheduled after
64 * previously flushed CSs referencing this BO in a conflicting way.
65 */
66 RADEON_USAGE_SYNCHRONIZED = 8
67 };
68
69 enum ring_type {
70 RING_GFX = 0,
71 RING_COMPUTE,
72 RING_DMA,
73 RING_UVD,
74 RING_VCE,
75 RING_LAST,
76 };
77
78 enum radeon_value_id {
79 RADEON_REQUESTED_VRAM_MEMORY,
80 RADEON_REQUESTED_GTT_MEMORY,
81 RADEON_MAPPED_VRAM,
82 RADEON_MAPPED_GTT,
83 RADEON_BUFFER_WAIT_TIME_NS,
84 RADEON_TIMESTAMP,
85 RADEON_NUM_GFX_IBS,
86 RADEON_NUM_SDMA_IBS,
87 RADEON_NUM_BYTES_MOVED,
88 RADEON_NUM_EVICTIONS,
89 RADEON_VRAM_USAGE,
90 RADEON_GTT_USAGE,
91 RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
92 RADEON_CURRENT_SCLK,
93 RADEON_CURRENT_MCLK,
94 RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
95 };
96
97 /* Each group of four has the same priority. */
98 enum radeon_bo_priority {
99 RADEON_PRIO_FENCE = 0,
100 RADEON_PRIO_TRACE,
101 RADEON_PRIO_SO_FILLED_SIZE,
102 RADEON_PRIO_QUERY,
103
104 RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
105 RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
106 RADEON_PRIO_DRAW_INDIRECT,
107 RADEON_PRIO_INDEX_BUFFER,
108
109 RADEON_PRIO_VCE = 8,
110 RADEON_PRIO_UVD,
111 RADEON_PRIO_SDMA_BUFFER,
112 RADEON_PRIO_SDMA_TEXTURE,
113
114 RADEON_PRIO_CP_DMA = 12,
115
116 RADEON_PRIO_CONST_BUFFER = 16,
117 RADEON_PRIO_DESCRIPTORS,
118 RADEON_PRIO_BORDER_COLORS,
119
120 RADEON_PRIO_SAMPLER_BUFFER = 20,
121 RADEON_PRIO_VERTEX_BUFFER,
122
123 RADEON_PRIO_SHADER_RW_BUFFER = 24,
124 RADEON_PRIO_COMPUTE_GLOBAL,
125
126 RADEON_PRIO_SAMPLER_TEXTURE = 28,
127 RADEON_PRIO_SHADER_RW_IMAGE,
128
129 RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
130
131 RADEON_PRIO_COLOR_BUFFER = 36,
132
133 RADEON_PRIO_DEPTH_BUFFER = 40,
134
135 RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
136
137 RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
138
139 RADEON_PRIO_CMASK = 52,
140 RADEON_PRIO_DCC,
141 RADEON_PRIO_HTILE,
142 RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
143
144 RADEON_PRIO_SHADER_RINGS = 56,
145
146 RADEON_PRIO_SCRATCH_BUFFER = 60,
147 /* 63 is the maximum value */
148 };
149
150 struct winsys_handle;
151 struct radeon_winsys_ctx;
152
153 struct radeon_winsys_cs_chunk {
154 unsigned cdw; /* Number of used dwords. */
155 unsigned max_dw; /* Maximum number of dwords. */
156 uint32_t *buf; /* The base pointer of the chunk. */
157 };
158
159 struct radeon_winsys_cs {
160 struct radeon_winsys_cs_chunk current;
161 struct radeon_winsys_cs_chunk *prev;
162 unsigned num_prev; /* Number of previous chunks. */
163 unsigned max_prev; /* Space in array pointed to by prev. */
164 unsigned prev_dw; /* Total number of dwords in previous chunks. */
165
166 /* Memory usage of the buffer list. These are always 0 for CE and preamble
167 * IBs. */
168 uint64_t used_vram;
169 uint64_t used_gart;
170 };
171
172 struct radeon_info {
173 /* PCI info: domain:bus:dev:func */
174 uint32_t pci_domain;
175 uint32_t pci_bus;
176 uint32_t pci_dev;
177 uint32_t pci_func;
178
179 /* Device info. */
180 uint32_t pci_id;
181 enum radeon_family family;
182 enum chip_class chip_class;
183 uint32_t gart_page_size;
184 uint64_t gart_size;
185 uint64_t vram_size;
186 uint64_t max_alloc_size;
187 uint32_t min_alloc_size;
188 bool has_dedicated_vram;
189 bool has_virtual_memory;
190 bool gfx_ib_pad_with_type2;
191 bool has_sdma;
192 bool has_uvd;
193 uint32_t uvd_fw_version;
194 uint32_t vce_fw_version;
195 uint32_t me_fw_version;
196 uint32_t pfp_fw_version;
197 uint32_t ce_fw_version;
198 uint32_t vce_harvest_config;
199 uint32_t clock_crystal_freq;
200
201 /* Kernel info. */
202 uint32_t drm_major; /* version */
203 uint32_t drm_minor;
204 uint32_t drm_patchlevel;
205 bool has_userptr;
206
207 /* Shader cores. */
208 uint32_t r600_max_quad_pipes; /* wave size / 16 */
209 uint32_t max_shader_clock;
210 uint32_t num_good_compute_units;
211 uint32_t max_se; /* shader engines */
212 uint32_t max_sh_per_se; /* shader arrays per shader engine */
213
214 /* Render backends (color + depth blocks). */
215 uint32_t r300_num_gb_pipes;
216 uint32_t r300_num_z_pipes;
217 uint32_t r600_gb_backend_map; /* R600 harvest config */
218 bool r600_gb_backend_map_valid;
219 uint32_t r600_num_banks;
220 uint32_t num_render_backends;
221 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
222 uint32_t pipe_interleave_bytes;
223 uint32_t enabled_rb_mask; /* GCN harvest config */
224
225 /* Tile modes. */
226 uint32_t si_tile_mode_array[32];
227 uint32_t cik_macrotile_mode_array[16];
228 };
229
230 /* Tiling info for display code, DRI sharing, and other data. */
231 struct radeon_bo_metadata {
232 /* Tiling flags describing the texture layout for display code
233 * and DRI sharing.
234 */
235 enum radeon_bo_layout microtile;
236 enum radeon_bo_layout macrotile;
237 unsigned pipe_config;
238 unsigned bankw;
239 unsigned bankh;
240 unsigned tile_split;
241 unsigned mtilea;
242 unsigned num_banks;
243 unsigned stride;
244 bool scanout;
245
246 /* Additional metadata associated with the buffer, in bytes.
247 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
248 * Supported by amdgpu only.
249 */
250 uint32_t size_metadata;
251 uint32_t metadata[64];
252 };
253
254 enum radeon_feature_id {
255 RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
256 RADEON_FID_R300_CMASK_ACCESS,
257 };
258
259 #define RADEON_SURF_MAX_LEVELS 15
260
261 enum radeon_surf_mode {
262 RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
263 RADEON_SURF_MODE_1D = 2,
264 RADEON_SURF_MODE_2D = 3,
265 };
266
267 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
268 enum radeon_micro_mode {
269 RADEON_MICRO_MODE_DISPLAY = 0,
270 RADEON_MICRO_MODE_THIN = 1,
271 RADEON_MICRO_MODE_DEPTH = 2,
272 RADEON_MICRO_MODE_ROTATED = 3,
273 };
274
275 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
276 #define RADEON_SURF_SCANOUT (1 << 16)
277 #define RADEON_SURF_ZBUFFER (1 << 17)
278 #define RADEON_SURF_SBUFFER (1 << 18)
279 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
280 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
281 #define RADEON_SURF_FMASK (1 << 21)
282 #define RADEON_SURF_DISABLE_DCC (1 << 22)
283 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
284 #define RADEON_SURF_IMPORTED (1 << 24)
285 #define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
286
287 struct radeon_surf_level {
288 uint64_t offset;
289 uint64_t slice_size;
290 uint64_t dcc_offset;
291 uint64_t dcc_fast_clear_size;
292 uint16_t nblk_x;
293 uint16_t nblk_y;
294 enum radeon_surf_mode mode;
295 };
296
297 struct radeon_surf {
298 /* Format properties. */
299 unsigned blk_w:4;
300 unsigned blk_h:4;
301 unsigned bpe:5;
302 /* Number of mipmap levels where DCC is enabled starting from level 0.
303 * Non-zero levels may be disabled due to alignment constraints, but not
304 * the first level.
305 */
306 unsigned num_dcc_levels:4;
307 unsigned is_linear:1;
308 uint32_t flags;
309
310 /* These are return values. Some of them can be set by the caller, but
311 * they will be treated as hints (e.g. bankw, bankh) and might be
312 * changed by the calculator.
313 */
314 uint64_t surf_size;
315 uint64_t dcc_size;
316 uint64_t htile_size;
317
318 uint32_t surf_alignment;
319 uint32_t dcc_alignment;
320 uint32_t htile_alignment;
321
322 /* This applies to EG and later. */
323 unsigned bankw:4; /* max 8 */
324 unsigned bankh:4; /* max 8 */
325 unsigned mtilea:4; /* max 8 */
326 unsigned tile_split:13; /* max 4K */
327 unsigned stencil_tile_split:13; /* max 4K */
328 unsigned pipe_config:5; /* max 17 */
329 unsigned num_banks:5; /* max 16 */
330 unsigned macro_tile_index:4; /* max 15 */
331 unsigned micro_tile_mode:3; /* displayable, thin, depth, rotated */
332
333 /* Whether the depth miptree or stencil miptree as used by the DB are
334 * adjusted from their TC compatible form to ensure depth/stencil
335 * compatibility. If either is true, the corresponding plane cannot be
336 * sampled from.
337 */
338 unsigned depth_adjusted:1;
339 unsigned stencil_adjusted:1;
340
341 struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
342 struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
343 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
344 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
345 };
346
347 struct radeon_bo_list_item {
348 uint64_t bo_size;
349 uint64_t vm_address;
350 uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
351 };
352
353 struct radeon_winsys {
354 /**
355 * The screen object this winsys was created for
356 */
357 struct pipe_screen *screen;
358
359 /**
360 * Decrement the winsys reference count.
361 *
362 * \param ws The winsys this function is called for.
363 * \return True if the winsys and screen should be destroyed.
364 */
365 bool (*unref)(struct radeon_winsys *ws);
366
367 /**
368 * Destroy this winsys.
369 *
370 * \param ws The winsys this function is called from.
371 */
372 void (*destroy)(struct radeon_winsys *ws);
373
374 /**
375 * Query an info structure from winsys.
376 *
377 * \param ws The winsys this function is called from.
378 * \param info Return structure
379 */
380 void (*query_info)(struct radeon_winsys *ws,
381 struct radeon_info *info);
382
383 /**************************************************************************
384 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
385 *
386 * Remember that gallium gets to choose the interface it needs, and the
387 * window systems must then implement that interface (rather than the
388 * other way around...).
389 *************************************************************************/
390
391 /**
392 * Create a buffer object.
393 *
394 * \param ws The winsys this function is called from.
395 * \param size The size to allocate.
396 * \param alignment An alignment of the buffer in memory.
397 * \param use_reusable_pool Whether the cache buffer manager should be used.
398 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
399 * \return The created buffer object.
400 */
401 struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
402 uint64_t size,
403 unsigned alignment,
404 enum radeon_bo_domain domain,
405 enum radeon_bo_flag flags);
406
407 /**
408 * Map the entire data store of a buffer object into the client's address
409 * space.
410 *
411 * \param buf A winsys buffer object to map.
412 * \param cs A command stream to flush if the buffer is referenced by it.
413 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
414 * \return The pointer at the beginning of the buffer.
415 */
416 void *(*buffer_map)(struct pb_buffer *buf,
417 struct radeon_winsys_cs *cs,
418 enum pipe_transfer_usage usage);
419
420 /**
421 * Unmap a buffer object from the client's address space.
422 *
423 * \param buf A winsys buffer object to unmap.
424 */
425 void (*buffer_unmap)(struct pb_buffer *buf);
426
427 /**
428 * Wait for the buffer and return true if the buffer is not used
429 * by the device.
430 *
431 * The timeout of 0 will only return the status.
432 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
433 * is idle.
434 */
435 bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
436 enum radeon_bo_usage usage);
437
438 /**
439 * Return buffer metadata.
440 * (tiling info for display code, DRI sharing, and other data)
441 *
442 * \param buf A winsys buffer object to get the flags from.
443 * \param md Metadata
444 */
445 void (*buffer_get_metadata)(struct pb_buffer *buf,
446 struct radeon_bo_metadata *md);
447
448 /**
449 * Set buffer metadata.
450 * (tiling info for display code, DRI sharing, and other data)
451 *
452 * \param buf A winsys buffer object to set the flags for.
453 * \param md Metadata
454 */
455 void (*buffer_set_metadata)(struct pb_buffer *buf,
456 struct radeon_bo_metadata *md);
457
458 /**
459 * Get a winsys buffer from a winsys handle. The internal structure
460 * of the handle is platform-specific and only a winsys should access it.
461 *
462 * \param ws The winsys this function is called from.
463 * \param whandle A winsys handle pointer as was received from a state
464 * tracker.
465 * \param stride The returned buffer stride in bytes.
466 */
467 struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
468 struct winsys_handle *whandle,
469 unsigned *stride, unsigned *offset);
470
471 /**
472 * Get a winsys buffer from a user pointer. The resulting buffer can't
473 * be exported. Both pointer and size must be page aligned.
474 *
475 * \param ws The winsys this function is called from.
476 * \param pointer User pointer to turn into a buffer object.
477 * \param Size Size in bytes for the new buffer.
478 */
479 struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
480 void *pointer, uint64_t size);
481
482 /**
483 * Whether the buffer was created from a user pointer.
484 *
485 * \param buf A winsys buffer object
486 * \return whether \p buf was created via buffer_from_ptr
487 */
488 bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
489
490 /**
491 * Get a winsys handle from a winsys buffer. The internal structure
492 * of the handle is platform-specific and only a winsys should access it.
493 *
494 * \param buf A winsys buffer object to get the handle from.
495 * \param whandle A winsys handle pointer.
496 * \param stride A stride of the buffer in bytes, for texturing.
497 * \return true on success.
498 */
499 bool (*buffer_get_handle)(struct pb_buffer *buf,
500 unsigned stride, unsigned offset,
501 unsigned slice_size,
502 struct winsys_handle *whandle);
503
504 /**
505 * Return the virtual address of a buffer.
506 *
507 * When virtual memory is not in use, this is the offset relative to the
508 * relocation base (non-zero for sub-allocated buffers).
509 *
510 * \param buf A winsys buffer object
511 * \return virtual address
512 */
513 uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
514
515 /**
516 * Return the offset of this buffer relative to the relocation base.
517 * This is only non-zero for sub-allocated buffers.
518 *
519 * This is only supported in the radeon winsys, since amdgpu uses virtual
520 * addresses in submissions even for the video engines.
521 *
522 * \param buf A winsys buffer object
523 * \return the offset for relocations
524 */
525 unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
526
527 /**
528 * Query the initial placement of the buffer from the kernel driver.
529 */
530 enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
531
532 /**************************************************************************
533 * Command submission.
534 *
535 * Each pipe context should create its own command stream and submit
536 * commands independently of other contexts.
537 *************************************************************************/
538
539 /**
540 * Create a command submission context.
541 * Various command streams can be submitted to the same context.
542 */
543 struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
544
545 /**
546 * Destroy a context.
547 */
548 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
549
550 /**
551 * Query a GPU reset status.
552 */
553 enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
554
555 /**
556 * Create a command stream.
557 *
558 * \param ctx The submission context
559 * \param ring_type The ring type (GFX, DMA, UVD)
560 * \param flush Flush callback function associated with the command stream.
561 * \param user User pointer that will be passed to the flush callback.
562 */
563 struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
564 enum ring_type ring_type,
565 void (*flush)(void *ctx, unsigned flags,
566 struct pipe_fence_handle **fence),
567 void *flush_ctx);
568
569 /**
570 * Add a constant engine IB to a graphics CS. This makes the graphics CS
571 * from "cs_create" a group of two IBs that share a buffer list and are
572 * flushed together.
573 *
574 * The returned constant CS is only a stream for writing packets to the new
575 * IB. Calling other winsys functions with it is not allowed, not even
576 * "cs_destroy".
577 *
578 * In order to add buffers and check memory usage, use the graphics CS.
579 * In order to flush it, use the graphics CS, which will flush both IBs.
580 * Destroying the graphics CS will destroy both of them.
581 *
582 * \param cs The graphics CS from "cs_create" that will hold the buffer
583 * list and will be used for flushing.
584 */
585 struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
586
587 /**
588 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
589 * in similar manner to cs_add_const_ib. This should always be called after
590 * cs_add_const_ib.
591 *
592 * The returned IB is a constant engine IB that only gets flushed if the
593 * context changed.
594 *
595 * \param cs The graphics CS from "cs_create" that will hold the buffer
596 * list and will be used for flushing.
597 */
598 struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
599 /**
600 * Destroy a command stream.
601 *
602 * \param cs A command stream to destroy.
603 */
604 void (*cs_destroy)(struct radeon_winsys_cs *cs);
605
606 /**
607 * Add a buffer. Each buffer used by a CS must be added using this function.
608 *
609 * \param cs Command stream
610 * \param buf Buffer
611 * \param usage Whether the buffer is used for read and/or write.
612 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
613 * \param priority A higher number means a greater chance of being
614 * placed in the requested domain. 15 is the maximum.
615 * \return Buffer index.
616 */
617 unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
618 struct pb_buffer *buf,
619 enum radeon_bo_usage usage,
620 enum radeon_bo_domain domain,
621 enum radeon_bo_priority priority);
622
623 /**
624 * Return the index of an already-added buffer.
625 *
626 * Not supported on amdgpu. Drivers with GPUVM should not care about
627 * buffer indices.
628 *
629 * \param cs Command stream
630 * \param buf Buffer
631 * \return The buffer index, or -1 if the buffer has not been added.
632 */
633 int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
634 struct pb_buffer *buf);
635
636 /**
637 * Return true if there is enough memory in VRAM and GTT for the buffers
638 * added so far. If the validation fails, all buffers which have
639 * been added since the last call of cs_validate will be removed and
640 * the CS will be flushed (provided there are still any buffers).
641 *
642 * \param cs A command stream to validate.
643 */
644 bool (*cs_validate)(struct radeon_winsys_cs *cs);
645
646 /**
647 * Check whether the given number of dwords is available in the IB.
648 * Optionally chain a new chunk of the IB if necessary and supported.
649 *
650 * \param cs A command stream.
651 * \param dw Number of CS dwords requested by the caller.
652 */
653 bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
654
655 /**
656 * Return the buffer list.
657 *
658 * This is the buffer list as passed to the kernel, i.e. it only contains
659 * the parent buffers of sub-allocated buffers.
660 *
661 * \param cs Command stream
662 * \param list Returned buffer list. Set to NULL to query the count only.
663 * \return The buffer count.
664 */
665 unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
666 struct radeon_bo_list_item *list);
667
668 /**
669 * Flush a command stream.
670 *
671 * \param cs A command stream to flush.
672 * \param flags, RADEON_FLUSH_ASYNC or 0.
673 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
674 * after the CS and is returned through this parameter.
675 * \return Negative POSIX error code or 0 for success.
676 * Asynchronous submissions never return an error.
677 */
678 int (*cs_flush)(struct radeon_winsys_cs *cs,
679 unsigned flags,
680 struct pipe_fence_handle **fence);
681
682 /**
683 * Create a fence before the CS is flushed.
684 * The user must flush manually to complete the initializaton of the fence.
685 * The fence must not be used before the flush.
686 */
687 struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
688
689 /**
690 * Return true if a buffer is referenced by a command stream.
691 *
692 * \param cs A command stream.
693 * \param buf A winsys buffer.
694 */
695 bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
696 struct pb_buffer *buf,
697 enum radeon_bo_usage usage);
698
699 /**
700 * Request access to a feature for a command stream.
701 *
702 * \param cs A command stream.
703 * \param fid Feature ID, one of RADEON_FID_*
704 * \param enable Whether to enable or disable the feature.
705 */
706 bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
707 enum radeon_feature_id fid,
708 bool enable);
709 /**
710 * Make sure all asynchronous flush of the cs have completed
711 *
712 * \param cs A command stream.
713 */
714 void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
715
716 /**
717 * Wait for the fence and return true if the fence has been signalled.
718 * The timeout of 0 will only return the status.
719 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
720 * is signalled.
721 */
722 bool (*fence_wait)(struct radeon_winsys *ws,
723 struct pipe_fence_handle *fence,
724 uint64_t timeout);
725
726 /**
727 * Reference counting for fences.
728 */
729 void (*fence_reference)(struct pipe_fence_handle **dst,
730 struct pipe_fence_handle *src);
731
732 /**
733 * Initialize surface
734 *
735 * \param ws The winsys this function is called from.
736 * \param tex Input texture description
737 * \param flags Bitmask of RADEON_SURF_* flags
738 * \param bpe Bytes per pixel, it can be different for Z buffers.
739 * \param mode Preferred tile mode. (linear, 1D, or 2D)
740 * \param surf Output structure
741 */
742 int (*surface_init)(struct radeon_winsys *ws,
743 const struct pipe_resource *tex,
744 unsigned flags, unsigned bpe,
745 enum radeon_surf_mode mode,
746 struct radeon_surf *surf);
747
748 uint64_t (*query_value)(struct radeon_winsys *ws,
749 enum radeon_value_id value);
750
751 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
752 unsigned num_registers, uint32_t *out);
753 };
754
radeon_emitted(struct radeon_winsys_cs * cs,unsigned num_dw)755 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
756 {
757 return cs && (cs->prev_dw + cs->current.cdw > num_dw);
758 }
759
radeon_emit(struct radeon_winsys_cs * cs,uint32_t value)760 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
761 {
762 cs->current.buf[cs->current.cdw++] = value;
763 }
764
radeon_emit_array(struct radeon_winsys_cs * cs,const uint32_t * values,unsigned count)765 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
766 const uint32_t *values, unsigned count)
767 {
768 memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
769 cs->current.cdw += count;
770 }
771
772 #endif
773