| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 141 void setUsed(BitVector &Regs) { in setUsed()
144 void setUnused(BitVector &Regs) { in setUnused()
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| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated()
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg()
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg()
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| D | MachineRegisterInfo.h | 285 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } in addPhysRegsUsed()
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand()
313 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
325 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
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| D | CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
939 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1309 CodeGenRegister::Vec Regs; member
1338 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2101 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
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| D | CodeGenTarget.cpp | 235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 127 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 99 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping()
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runMCDesc() local
677 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runTargetDesc() local
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| D | CodeGenTarget.cpp | 175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 972 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
981 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
990 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1028 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 153 BitVector &Regs) { in collectChangingRegs()
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| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 86 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs, in removeRegsFromMap()
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| D | CallingConvLower.cpp | 193 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
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| D | AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs, in GetGroupRegs()
544 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
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| D | ExecutionDepsFix.cpp | 655 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 544 const unsigned *Regs, bool IsAddress) { in parseRegister()
561 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
580 const MCExpr *&Length, const unsigned *Regs, in parseAddress()
641 const unsigned *Regs, RegisterKind RegKind) { in parseAddress()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 201 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, in lookupCandidateBaseReg()
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| D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, in GetGroupRegs()
558 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 561 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
628 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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| D | Thumb2SizeReduction.cpp | 189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) in HasImplicitCPSRDef() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 582 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
597 ArrayRef<std::pair<unsigned, bool>> Regs) { in CreateLoadStoreMulti()
818 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.cpp | 1534 void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) { in addLiveRegs()
1545 std::set<unsigned> &Regs) { in decreaseLiveRegs()
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| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 728 SmallPtrSet<const SCEV *, 16> &Regs, in RateRegister()
796 SmallPtrSet<const SCEV *, 16> &Regs, in RatePrimaryRegister()
804 SmallPtrSet<const SCEV *, 16> &Regs, in RateFormula()
1055 SmallPtrSet<const SCEV *, 4> Regs; member in __anonb55a72010611::LSRUse
2916 SmallPtrSet<const SCEV *, 16> Regs; in FilterOutUndesirableDedicatedRegisters() local
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