1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keithw@vmware.com>
33 */
34
35 #ifndef __R200_CONTEXT_H__
36 #define __R200_CONTEXT_H__
37
38 #include "tnl/t_vertex.h"
39 #include "drm.h"
40 #include "radeon_drm.h"
41 #include "dri_util.h"
42
43 #include "main/macros.h"
44 #include "main/mtypes.h"
45 #include "r200_reg.h"
46 #include "r200_vertprog.h"
47
48 #ifndef R200_EMIT_VAP_PVS_CNTL
49 #error This driver requires a newer libdrm to compile
50 #endif
51
52 #include "radeon_screen.h"
53 #include "radeon_common.h"
54
55 struct r200_context;
56 typedef struct r200_context r200ContextRec;
57 typedef struct r200_context *r200ContextPtr;
58
59 #include "main/mm.h"
60
61 struct r200_vertex_program {
62 struct gl_program mesa_program; /* Must be first */
63 int translated;
64 /* need excess instr: 1 for late loop checking, 2 for
65 additional instr due to instr/attr, 3 for fog */
66 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6];
67 int pos_end;
68 int inputs[VERT_ATTRIB_MAX];
69 GLubyte inputmap_rev[16];
70 int native;
71 int fogpidx;
72 int fogmode;
73 };
74
75 #define R200_TEX_ALL 0x3f
76
77
78 struct r200_texture_env_state {
79 radeonTexObjPtr texobj;
80 GLuint outputreg;
81 GLuint unitneeded;
82 };
83
84 #define R200_MAX_TEXTURE_UNITS 6
85
86 struct r200_texture_state {
87 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS];
88 };
89
90
91 /* Trying to keep these relatively short as the variables are becoming
92 * extravagently long. Drop the driver name prefix off the front of
93 * everything - I think we know which driver we're in by now, and keep the
94 * prefix to 3 letters unless absolutely impossible.
95 */
96
97 #define CTX_CMD_0 0
98 #define CTX_PP_MISC 1
99 #define CTX_PP_FOG_COLOR 2
100 #define CTX_RE_SOLID_COLOR 3
101 #define CTX_RB3D_BLENDCNTL 4
102 #define CTX_RB3D_DEPTHOFFSET 5
103 #define CTX_RB3D_DEPTHPITCH 6
104 #define CTX_RB3D_ZSTENCILCNTL 7
105 #define CTX_CMD_1 8
106 #define CTX_PP_CNTL 9
107 #define CTX_RB3D_CNTL 10
108 #define CTX_RB3D_COLOROFFSET 11
109 #define CTX_CMD_2 12 /* why */
110 #define CTX_RB3D_COLORPITCH 13 /* why */
111 #define CTX_CMD_3 14
112 #define CTX_RB3D_BLENDCOLOR 15
113 #define CTX_RB3D_ABLENDCNTL 16
114 #define CTX_RB3D_CBLENDCNTL 17
115 #define CTX_STATE_SIZE_NEWDRM 18
116
117 #define SET_CMD_0 0
118 #define SET_SE_CNTL 1
119 #define SET_RE_CNTL 2 /* replace se_coord_fmt */
120 #define SET_STATE_SIZE 3
121
122 #define VTE_CMD_0 0
123 #define VTE_SE_VTE_CNTL 1
124 #define VTE_STATE_SIZE 2
125
126 #define LIN_CMD_0 0
127 #define LIN_RE_LINE_PATTERN 1
128 #define LIN_RE_LINE_STATE 2
129 #define LIN_CMD_1 3
130 #define LIN_SE_LINE_WIDTH 4
131 #define LIN_STATE_SIZE 5
132
133 #define MSK_CMD_0 0
134 #define MSK_RB3D_STENCILREFMASK 1
135 #define MSK_RB3D_ROPCNTL 2
136 #define MSK_RB3D_PLANEMASK 3
137 #define MSK_STATE_SIZE 4
138
139 #define VPT_CMD_0 0
140 #define VPT_SE_VPORT_XSCALE 1
141 #define VPT_SE_VPORT_XOFFSET 2
142 #define VPT_SE_VPORT_YSCALE 3
143 #define VPT_SE_VPORT_YOFFSET 4
144 #define VPT_SE_VPORT_ZSCALE 5
145 #define VPT_SE_VPORT_ZOFFSET 6
146 #define VPT_STATE_SIZE 7
147
148 #define ZBS_CMD_0 0
149 #define ZBS_SE_ZBIAS_FACTOR 1
150 #define ZBS_SE_ZBIAS_CONSTANT 2
151 #define ZBS_STATE_SIZE 3
152
153 #define MSC_CMD_0 0
154 #define MSC_RE_MISC 1
155 #define MSC_STATE_SIZE 2
156
157 #define TAM_CMD_0 0
158 #define TAM_DEBUG3 1
159 #define TAM_STATE_SIZE 2
160
161 #define TEX_CMD_0 0
162 #define TEX_PP_TXFILTER 1 /*2c00*/
163 #define TEX_PP_TXFORMAT 2 /*2c04*/
164 #define TEX_PP_TXFORMAT_X 3 /*2c08*/
165 #define TEX_PP_TXSIZE 4 /*2c0c*/
166 #define TEX_PP_TXPITCH 5 /*2c10*/
167 #define TEX_PP_BORDER_COLOR 6 /*2c14*/
168 #define TEX_PP_CUBIC_FACES 7
169 #define TEX_PP_TXMULTI_CTL 8
170 #define TEX_CMD_1_NEWDRM 9
171 #define TEX_PP_TXOFFSET_NEWDRM 10
172 #define TEX_STATE_SIZE_NEWDRM 11
173
174 #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */
175 #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */
176 #define CUBE_CMD_1 2 /* 5 registers follow */
177 #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */
178 #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */
179 #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */
180 #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */
181 #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */
182 #define CUBE_STATE_SIZE 8
183
184 #define PIX_CMD_0 0
185 #define PIX_PP_TXCBLEND 1
186 #define PIX_PP_TXCBLEND2 2
187 #define PIX_PP_TXABLEND 3
188 #define PIX_PP_TXABLEND2 4
189 #define PIX_STATE_SIZE 5
190
191 #define TF_CMD_0 0
192 #define TF_TFACTOR_0 1
193 #define TF_TFACTOR_1 2
194 #define TF_TFACTOR_2 3
195 #define TF_TFACTOR_3 4
196 #define TF_TFACTOR_4 5
197 #define TF_TFACTOR_5 6
198 #define TF_STATE_SIZE 7
199
200 #define ATF_CMD_0 0
201 #define ATF_TFACTOR_0 1
202 #define ATF_TFACTOR_1 2
203 #define ATF_TFACTOR_2 3
204 #define ATF_TFACTOR_3 4
205 #define ATF_TFACTOR_4 5
206 #define ATF_TFACTOR_5 6
207 #define ATF_TFACTOR_6 7
208 #define ATF_TFACTOR_7 8
209 #define ATF_STATE_SIZE 9
210
211 /* ATI_FRAGMENT_SHADER */
212 #define AFS_CMD_0 0
213 #define AFS_IC0 1 /* 2f00 */
214 #define AFS_IC1 2 /* 2f04 */
215 #define AFS_IA0 3 /* 2f08 */
216 #define AFS_IA1 4 /* 2f0c */
217 #define AFS_STATE_SIZE 33
218
219 #define PVS_CMD_0 0
220 #define PVS_CNTL_1 1
221 #define PVS_CNTL_2 2
222 #define PVS_STATE_SIZE 3
223
224 /* those are quite big... */
225 #define VPI_CMD_0 0
226 #define VPI_OPDST_0 1
227 #define VPI_SRC0_0 2
228 #define VPI_SRC1_0 3
229 #define VPI_SRC2_0 4
230 #define VPI_OPDST_63 253
231 #define VPI_SRC0_63 254
232 #define VPI_SRC1_63 255
233 #define VPI_SRC2_63 256
234 #define VPI_STATE_SIZE 257
235
236 #define VPP_CMD_0 0
237 #define VPP_PARAM0_0 1
238 #define VPP_PARAM1_0 2
239 #define VPP_PARAM2_0 3
240 #define VPP_PARAM3_0 4
241 #define VPP_PARAM0_95 381
242 #define VPP_PARAM1_95 382
243 #define VPP_PARAM2_95 383
244 #define VPP_PARAM3_95 384
245 #define VPP_STATE_SIZE 385
246
247 #define TCL_CMD_0 0
248 #define TCL_LIGHT_MODEL_CTL_0 1
249 #define TCL_LIGHT_MODEL_CTL_1 2
250 #define TCL_PER_LIGHT_CTL_0 3
251 #define TCL_PER_LIGHT_CTL_1 4
252 #define TCL_PER_LIGHT_CTL_2 5
253 #define TCL_PER_LIGHT_CTL_3 6
254 #define TCL_CMD_1 7
255 #define TCL_UCP_VERT_BLEND_CTL 8
256 #define TCL_STATE_SIZE 9
257
258 #define MSL_CMD_0 0
259 #define MSL_MATRIX_SELECT_0 1
260 #define MSL_MATRIX_SELECT_1 2
261 #define MSL_MATRIX_SELECT_2 3
262 #define MSL_MATRIX_SELECT_3 4
263 #define MSL_MATRIX_SELECT_4 5
264 #define MSL_STATE_SIZE 6
265
266 #define TCG_CMD_0 0
267 #define TCG_TEX_PROC_CTL_2 1
268 #define TCG_TEX_PROC_CTL_3 2
269 #define TCG_TEX_PROC_CTL_0 3
270 #define TCG_TEX_PROC_CTL_1 4
271 #define TCG_TEX_CYL_WRAP_CTL 5
272 #define TCG_STATE_SIZE 6
273
274 #define MTL_CMD_0 0
275 #define MTL_EMMISSIVE_RED 1
276 #define MTL_EMMISSIVE_GREEN 2
277 #define MTL_EMMISSIVE_BLUE 3
278 #define MTL_EMMISSIVE_ALPHA 4
279 #define MTL_AMBIENT_RED 5
280 #define MTL_AMBIENT_GREEN 6
281 #define MTL_AMBIENT_BLUE 7
282 #define MTL_AMBIENT_ALPHA 8
283 #define MTL_DIFFUSE_RED 9
284 #define MTL_DIFFUSE_GREEN 10
285 #define MTL_DIFFUSE_BLUE 11
286 #define MTL_DIFFUSE_ALPHA 12
287 #define MTL_SPECULAR_RED 13
288 #define MTL_SPECULAR_GREEN 14
289 #define MTL_SPECULAR_BLUE 15
290 #define MTL_SPECULAR_ALPHA 16
291 #define MTL_CMD_1 17
292 #define MTL_SHININESS 18
293 #define MTL_STATE_SIZE 19
294
295 #define VAP_CMD_0 0
296 #define VAP_SE_VAP_CNTL 1
297 #define VAP_STATE_SIZE 2
298
299 /* Replaces a lot of packet info from radeon
300 */
301 #define VTX_CMD_0 0
302 #define VTX_VTXFMT_0 1
303 #define VTX_VTXFMT_1 2
304 #define VTX_TCL_OUTPUT_VTXFMT_0 3
305 #define VTX_TCL_OUTPUT_VTXFMT_1 4
306 #define VTX_CMD_1 5
307 #define VTX_TCL_OUTPUT_COMPSEL 6
308 #define VTX_CMD_2 7
309 #define VTX_STATE_CNTL 8
310 #define VTX_STATE_SIZE 9
311
312 /* SPR - point sprite state
313 */
314 #define SPR_CMD_0 0
315 #define SPR_POINT_SPRITE_CNTL 1
316 #define SPR_STATE_SIZE 2
317
318 #define PTP_CMD_0 0
319 #define PTP_VPORT_SCALE_0 1
320 #define PTP_VPORT_SCALE_1 2
321 #define PTP_VPORT_SCALE_PTSIZE 3
322 #define PTP_VPORT_SCALE_3 4
323 #define PTP_CMD_1 5
324 #define PTP_ATT_CONST_QUAD 6
325 #define PTP_ATT_CONST_LIN 7
326 #define PTP_ATT_CONST_CON 8
327 #define PTP_ATT_CONST_3 9
328 #define PTP_EYE_X 10
329 #define PTP_EYE_Y 11
330 #define PTP_EYE_Z 12
331 #define PTP_EYE_3 13
332 #define PTP_CLAMP_MIN 14
333 #define PTP_CLAMP_MAX 15
334 #define PTP_CLAMP_2 16
335 #define PTP_CLAMP_3 17
336 #define PTP_STATE_SIZE 18
337
338 #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
339 R200_VTX_COLOR_MASK)
340
341 /**
342 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine
343 * how many components are in texture coordinate \c n.
344 */
345 #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07)
346
347 #define MAT_CMD_0 0
348 #define MAT_ELT_0 1
349 #define MAT_STATE_SIZE 17
350
351 #define GRD_CMD_0 0
352 #define GRD_VERT_GUARD_CLIP_ADJ 1
353 #define GRD_VERT_GUARD_DISCARD_ADJ 2
354 #define GRD_HORZ_GUARD_CLIP_ADJ 3
355 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
356 #define GRD_STATE_SIZE 5
357
358 /* position changes frequently when lighting in modelpos - separate
359 * out to new state item?
360 */
361 #define LIT_CMD_0 0
362 #define LIT_AMBIENT_RED 1
363 #define LIT_AMBIENT_GREEN 2
364 #define LIT_AMBIENT_BLUE 3
365 #define LIT_AMBIENT_ALPHA 4
366 #define LIT_DIFFUSE_RED 5
367 #define LIT_DIFFUSE_GREEN 6
368 #define LIT_DIFFUSE_BLUE 7
369 #define LIT_DIFFUSE_ALPHA 8
370 #define LIT_SPECULAR_RED 9
371 #define LIT_SPECULAR_GREEN 10
372 #define LIT_SPECULAR_BLUE 11
373 #define LIT_SPECULAR_ALPHA 12
374 #define LIT_POSITION_X 13
375 #define LIT_POSITION_Y 14
376 #define LIT_POSITION_Z 15
377 #define LIT_POSITION_W 16
378 #define LIT_DIRECTION_X 17
379 #define LIT_DIRECTION_Y 18
380 #define LIT_DIRECTION_Z 19
381 #define LIT_DIRECTION_W 20
382 #define LIT_ATTEN_QUADRATIC 21
383 #define LIT_ATTEN_LINEAR 22
384 #define LIT_ATTEN_CONST 23
385 #define LIT_ATTEN_XXX 24
386 #define LIT_CMD_1 25
387 #define LIT_SPOT_DCD 26
388 #define LIT_SPOT_DCM 27
389 #define LIT_SPOT_EXPONENT 28
390 #define LIT_SPOT_CUTOFF 29
391 #define LIT_SPECULAR_THRESH 30
392 #define LIT_RANGE_CUTOFF 31 /* ? */
393 #define LIT_ATTEN_CONST_INV 32
394 #define LIT_STATE_SIZE 33
395
396 /* Fog
397 */
398 #define FOG_CMD_0 0
399 #define FOG_R 1
400 #define FOG_C 2
401 #define FOG_D 3
402 #define FOG_PAD 4
403 #define FOG_STATE_SIZE 5
404
405 /* UCP
406 */
407 #define UCP_CMD_0 0
408 #define UCP_X 1
409 #define UCP_Y 2
410 #define UCP_Z 3
411 #define UCP_W 4
412 #define UCP_STATE_SIZE 5
413
414 /* GLT - Global ambient
415 */
416 #define GLT_CMD_0 0
417 #define GLT_RED 1
418 #define GLT_GREEN 2
419 #define GLT_BLUE 3
420 #define GLT_ALPHA 4
421 #define GLT_STATE_SIZE 5
422
423 /* EYE
424 */
425 #define EYE_CMD_0 0
426 #define EYE_X 1
427 #define EYE_Y 2
428 #define EYE_Z 3
429 #define EYE_RESCALE_FACTOR 4
430 #define EYE_STATE_SIZE 5
431
432 /* CST - constant state
433 */
434 #define CST_CMD_0 0
435 #define CST_PP_CNTL_X 1
436 #define CST_CMD_1 2
437 #define CST_RB3D_DEPTHXY_OFFSET 3
438 #define CST_CMD_2 4
439 #define CST_RE_AUX_SCISSOR_CNTL 5
440 #define CST_CMD_4 6
441 #define CST_SE_VAP_CNTL_STATUS 7
442 #define CST_CMD_5 8
443 #define CST_RE_POINTSIZE 9
444 #define CST_CMD_6 10
445 #define CST_SE_TCL_INPUT_VTX_0 11
446 #define CST_SE_TCL_INPUT_VTX_1 12
447 #define CST_SE_TCL_INPUT_VTX_2 13
448 #define CST_SE_TCL_INPUT_VTX_3 14
449 #define CST_STATE_SIZE 15
450
451 #define PRF_CMD_0 0
452 #define PRF_PP_TRI_PERF 1
453 #define PRF_PP_PERF_CNTL 2
454 #define PRF_STATE_SIZE 3
455
456
457 #define SCI_CMD_1 0
458 #define SCI_XY_1 1
459 #define SCI_CMD_2 2
460 #define SCI_XY_2 3
461 #define SCI_STATE_SIZE 4
462
463 #define R200_QUERYOBJ_CMD_0 0
464 #define R200_QUERYOBJ_DATA_0 1
465 #define R200_QUERYOBJ_CMDSIZE 2
466
467 #define STP_CMD_0 0
468 #define STP_DATA_0 1
469 #define STP_CMD_1 2
470 #define STP_STATE_SIZE 35
471
472 struct r200_hw_state {
473 /* Hardware state, stored as cmdbuf commands:
474 * -- Need to doublebuffer for
475 * - reviving state after loss of context
476 * - eliding noop statechange loops? (except line stipple count)
477 */
478 struct radeon_state_atom ctx;
479 struct radeon_state_atom set;
480 struct radeon_state_atom sci;
481 struct radeon_state_atom vte;
482 struct radeon_state_atom lin;
483 struct radeon_state_atom msk;
484 struct radeon_state_atom vpt;
485 struct radeon_state_atom vap;
486 struct radeon_state_atom vtx;
487 struct radeon_state_atom tcl;
488 struct radeon_state_atom msl;
489 struct radeon_state_atom tcg;
490 struct radeon_state_atom msc;
491 struct radeon_state_atom cst;
492 struct radeon_state_atom tam;
493 struct radeon_state_atom tf;
494 struct radeon_state_atom tex[6];
495 struct radeon_state_atom cube[6];
496 struct radeon_state_atom zbs;
497 struct radeon_state_atom mtl[2];
498 struct radeon_state_atom mat[9];
499 struct radeon_state_atom lit[8]; /* includes vec, scl commands */
500 struct radeon_state_atom ucp[6];
501 struct radeon_state_atom pix[6]; /* pixshader stages */
502 struct radeon_state_atom eye; /* eye pos */
503 struct radeon_state_atom grd; /* guard band clipping */
504 struct radeon_state_atom fog;
505 struct radeon_state_atom glt;
506 struct radeon_state_atom prf;
507 struct radeon_state_atom afs[2];
508 struct radeon_state_atom pvs;
509 struct radeon_state_atom vpi[2];
510 struct radeon_state_atom vpp[2];
511 struct radeon_state_atom atf;
512 struct radeon_state_atom spr;
513 struct radeon_state_atom ptp;
514 struct radeon_state_atom stp;
515 };
516
517 struct r200_state {
518 /* Derived state for internal purposes:
519 */
520 struct r200_texture_state texture;
521 GLuint envneeded;
522 };
523
524 #define R200_CMD_BUF_SZ (16*1024)
525
526 #define R200_ELT_BUF_SZ (16*1024)
527 /* r200_tcl.c
528 */
529 struct r200_tcl_info {
530 GLuint hw_primitive;
531
532 int elt_used;
533
534 };
535
536
537 /* r200_swtcl.c
538 */
539 struct r200_swtcl_info {
540
541
542 radeon_point_func draw_point;
543 radeon_line_func draw_line;
544 radeon_tri_func draw_tri;
545
546 /**
547 * Offset of the 4UB color data within a hardware (swtcl) vertex.
548 */
549 GLuint coloroffset;
550
551 /**
552 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
553 */
554 GLuint specoffset;
555
556 /**
557 * Should Mesa project vertex data or will the hardware do it?
558 */
559 GLboolean needproj;
560 };
561
562
563
564
565 /* A maximum total of 29 elements per vertex: 3 floats for position, 3
566 * floats for normal, 4 floats for color, 4 bytes for secondary color,
567 * 3 floats for each texture unit (18 floats total).
568 *
569 * we maybe need add. 4 to prevent segfault if someone specifies
570 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
571 *
572 * The position data is never actually stored here, so 3 elements could be
573 * trimmed out of the buffer.
574 */
575
576 #define R200_MAX_VERTEX_SIZE ((3*6)+11)
577
578 struct r200_context {
579 struct radeon_context radeon;
580
581 /* Driver and hardware state management
582 */
583 struct r200_hw_state hw;
584 struct r200_state state;
585 struct r200_vertex_program *curr_vp_hw;
586
587 /* Vertex buffers
588 */
589 struct radeon_ioctl ioctl;
590 struct radeon_store store;
591
592 /* Clientdata textures;
593 */
594 GLuint prefer_gart_client_texturing;
595
596 /* TCL stuff
597 */
598 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS];
599 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS];
600 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS];
601 GLuint TexMatEnabled;
602 GLuint TexMatCompSel;
603 GLuint TexGenEnabled;
604 GLuint TexGenCompSel;
605 GLmatrix tmpmat;
606
607 /* r200_tcl.c
608 */
609 struct r200_tcl_info tcl;
610
611 /* r200_swtcl.c
612 */
613 struct r200_swtcl_info swtcl;
614
615 GLboolean using_hyperz;
616
617 struct ati_fragment_shader *afs_loaded;
618 };
619
620
621 static inline r200ContextPtr
R200_CONTEXT(struct gl_context * ctx)622 R200_CONTEXT(struct gl_context *ctx)
623 {
624 return (r200ContextPtr) ctx;
625 }
626
627
628 extern void r200DestroyContext( __DRIcontext *driContextPriv );
629 extern GLboolean r200CreateContext( gl_api api,
630 const struct gl_config *glVisual,
631 __DRIcontext *driContextPriv,
632 unsigned major_version,
633 unsigned minor_version,
634 uint32_t flags,
635 bool notify_reset,
636 unsigned *error,
637 void *sharedContextPrivate);
638 extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv,
639 __DRIdrawable *driDrawPriv,
640 __DRIdrawable *driReadPriv );
641 extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv );
642
643 extern void r200_init_texcopy_functions(struct dd_function_table *table);
644
645 /* ================================================================
646 * Debugging:
647 */
648
649 #define R200_DEBUG RADEON_DEBUG
650
651
652
653 #endif /* __R200_CONTEXT_H__ */
654