1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17
18 #include "SystemZ.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
22
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28 // Return with a flag operand. Operand 0 is the chain operand.
29 RET_FLAG,
30
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
34 CALL,
35 SIBCALL,
36
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
39 TLS_GDCALL,
40 TLS_LDCALL,
41
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
44 PCREL_WRAPPER,
45
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
51 PCREL_OFFSET,
52
53 // Integer absolute.
54 IABS,
55
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
58 ICMP,
59
60 // Floating-point comparisons. The two operands are the values to compare.
61 FCMP,
62
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
68 TM,
69
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
74 BR_CCMASK,
75
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
80 SELECT_CCMASK,
81
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
84 ADJDYNALLOC,
85
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
88 EXTRACT_ACCESS,
89
90 // Count number of bits set in operand 0 per byte.
91 POPCNT,
92
93 // Wrappers around the ISD opcodes of the same name. The output and
94 // first input operands are GR128s. The trailing numbers are the
95 // widths of the second operand in bits.
96 UMUL_LOHI64,
97 SDIVREM32,
98 SDIVREM64,
99 UDIVREM32,
100 UDIVREM64,
101
102 // Use a series of MVCs to copy bytes from one memory location to another.
103 // The operands are:
104 // - the target address
105 // - the source address
106 // - the constant length
107 //
108 // This isn't a memory opcode because we'd need to attach two
109 // MachineMemOperands rather than one.
110 MVC,
111
112 // Like MVC, but implemented as a loop that handles X*256 bytes
113 // followed by straight-line code to handle the rest (if any).
114 // The value of X is passed as an additional operand.
115 MVC_LOOP,
116
117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
118 NC,
119 NC_LOOP,
120 OC,
121 OC_LOOP,
122 XC,
123 XC_LOOP,
124
125 // Use CLC to compare two blocks of memory, with the same comments
126 // as for MVC and MVC_LOOP.
127 CLC,
128 CLC_LOOP,
129
130 // Use an MVST-based sequence to implement stpcpy().
131 STPCPY,
132
133 // Use a CLST-based sequence to implement strcmp(). The two input operands
134 // are the addresses of the strings to compare.
135 STRCMP,
136
137 // Use an SRST-based sequence to search a block of memory. The first
138 // operand is the end address, the second is the start, and the third
139 // is the character to search for. CC is set to 1 on success and 2
140 // on failure.
141 SEARCH_STRING,
142
143 // Store the CC value in bits 29 and 28 of an integer.
144 IPM,
145
146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
147 SERIALIZE,
148
149 // Compiler barrier only; generate a no-op.
150 MEMBARRIER,
151
152 // Transaction begin. The first operand is the chain, the second
153 // the TDB pointer, and the third the immediate control field.
154 // Returns chain and glue.
155 TBEGIN,
156 TBEGIN_NOFLOAT,
157
158 // Transaction end. Just the chain operand. Returns chain and glue.
159 TEND,
160
161 // Create a vector constant by filling byte N of the result with bit
162 // 15-N of the single operand.
163 BYTE_MASK,
164
165 // Create a vector constant by replicating an element-sized RISBG-style mask.
166 // The first operand specifies the starting set bit and the second operand
167 // specifies the ending set bit. Both operands count from the MSB of the
168 // element.
169 ROTATE_MASK,
170
171 // Replicate a GPR scalar value into all elements of a vector.
172 REPLICATE,
173
174 // Create a vector from two i64 GPRs.
175 JOIN_DWORDS,
176
177 // Replicate one element of a vector into all elements. The first operand
178 // is the vector and the second is the index of the element to replicate.
179 SPLAT,
180
181 // Interleave elements from the high half of operand 0 and the high half
182 // of operand 1.
183 MERGE_HIGH,
184
185 // Likewise for the low halves.
186 MERGE_LOW,
187
188 // Concatenate the vectors in the first two operands, shift them left
189 // by the third operand, and take the first half of the result.
190 SHL_DOUBLE,
191
192 // Take one element of the first v2i64 operand and the one element of
193 // the second v2i64 operand and concatenate them to form a v2i64 result.
194 // The third operand is a 4-bit value of the form 0A0B, where A and B
195 // are the element selectors for the first operand and second operands
196 // respectively.
197 PERMUTE_DWORDS,
198
199 // Perform a general vector permute on vector operands 0 and 1.
200 // Each byte of operand 2 controls the corresponding byte of the result,
201 // in the same way as a byte-level VECTOR_SHUFFLE mask.
202 PERMUTE,
203
204 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
205 PACK,
206
207 // Likewise, but saturate the result and set CC. PACKS_CC does signed
208 // saturation and PACKLS_CC does unsigned saturation.
209 PACKS_CC,
210 PACKLS_CC,
211
212 // Unpack the first half of vector operand 0 into double-sized elements.
213 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
214 UNPACK_HIGH,
215 UNPACKL_HIGH,
216
217 // Likewise for the second half.
218 UNPACK_LOW,
219 UNPACKL_LOW,
220
221 // Shift each element of vector operand 0 by the number of bits specified
222 // by scalar operand 1.
223 VSHL_BY_SCALAR,
224 VSRL_BY_SCALAR,
225 VSRA_BY_SCALAR,
226
227 // For each element of the output type, sum across all sub-elements of
228 // operand 0 belonging to the corresponding element, and add in the
229 // rightmost sub-element of the corresponding element of operand 1.
230 VSUM,
231
232 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
233 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
234 // and VICMPHL for "unsigned greater than".
235 VICMPE,
236 VICMPH,
237 VICMPHL,
238
239 // Likewise, but also set the condition codes on the result.
240 VICMPES,
241 VICMPHS,
242 VICMPHLS,
243
244 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
245 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
246 // greater than" and VFCMPHE for "ordered and greater than or equal to".
247 VFCMPE,
248 VFCMPH,
249 VFCMPHE,
250
251 // Likewise, but also set the condition codes on the result.
252 VFCMPES,
253 VFCMPHS,
254 VFCMPHES,
255
256 // Test floating-point data class for vectors.
257 VFTCI,
258
259 // Extend the even f32 elements of vector operand 0 to produce a vector
260 // of f64 elements.
261 VEXTEND,
262
263 // Round the f64 elements of vector operand 0 to f32s and store them in the
264 // even elements of the result.
265 VROUND,
266
267 // AND the two vector operands together and set CC based on the result.
268 VTM,
269
270 // String operations that set CC as a side-effect.
271 VFAE_CC,
272 VFAEZ_CC,
273 VFEE_CC,
274 VFEEZ_CC,
275 VFENE_CC,
276 VFENEZ_CC,
277 VISTR_CC,
278 VSTRC_CC,
279 VSTRCZ_CC,
280
281 // Test Data Class.
282 //
283 // Operand 0: the value to test
284 // Operand 1: the bit mask
285 TDC,
286
287 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
288 // ATOMIC_LOAD_<op>.
289 //
290 // Operand 0: the address of the containing 32-bit-aligned field
291 // Operand 1: the second operand of <op>, in the high bits of an i32
292 // for everything except ATOMIC_SWAPW
293 // Operand 2: how many bits to rotate the i32 left to bring the first
294 // operand into the high bits
295 // Operand 3: the negative of operand 2, for rotating the other way
296 // Operand 4: the width of the field in bits (8 or 16)
297 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
298 ATOMIC_LOADW_ADD,
299 ATOMIC_LOADW_SUB,
300 ATOMIC_LOADW_AND,
301 ATOMIC_LOADW_OR,
302 ATOMIC_LOADW_XOR,
303 ATOMIC_LOADW_NAND,
304 ATOMIC_LOADW_MIN,
305 ATOMIC_LOADW_MAX,
306 ATOMIC_LOADW_UMIN,
307 ATOMIC_LOADW_UMAX,
308
309 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
310 //
311 // Operand 0: the address of the containing 32-bit-aligned field
312 // Operand 1: the compare value, in the low bits of an i32
313 // Operand 2: the swap value, in the low bits of an i32
314 // Operand 3: how many bits to rotate the i32 left to bring the first
315 // operand into the high bits
316 // Operand 4: the negative of operand 2, for rotating the other way
317 // Operand 5: the width of the field in bits (8 or 16)
318 ATOMIC_CMP_SWAPW,
319
320 // Byte swapping load.
321 //
322 // Operand 0: the address to load from
323 // Operand 1: the type of load (i16, i32, i64)
324 LRV,
325
326 // Byte swapping store.
327 //
328 // Operand 0: the value to store
329 // Operand 1: the address to store to
330 // Operand 2: the type of store (i16, i32, i64)
331 STRV,
332
333 // Prefetch from the second operand using the 4-bit control code in
334 // the first operand. The code is 1 for a load prefetch and 2 for
335 // a store prefetch.
336 PREFETCH
337 };
338
339 // Return true if OPCODE is some kind of PC-relative address.
isPCREL(unsigned Opcode)340 inline bool isPCREL(unsigned Opcode) {
341 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
342 }
343 } // end namespace SystemZISD
344
345 namespace SystemZICMP {
346 // Describes whether an integer comparison needs to be signed or unsigned,
347 // or whether either type is OK.
348 enum {
349 Any,
350 UnsignedOnly,
351 SignedOnly
352 };
353 } // end namespace SystemZICMP
354
355 class SystemZSubtarget;
356 class SystemZTargetMachine;
357
358 class SystemZTargetLowering : public TargetLowering {
359 public:
360 explicit SystemZTargetLowering(const TargetMachine &TM,
361 const SystemZSubtarget &STI);
362
363 // Override TargetLowering.
getScalarShiftAmountTy(const DataLayout &,EVT)364 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
365 return MVT::i32;
366 }
getVectorIdxTy(const DataLayout & DL)367 MVT getVectorIdxTy(const DataLayout &DL) const override {
368 // Only the lower 12 bits of an element index are used, so we don't
369 // want to clobber the upper 32 bits of a GPR unnecessarily.
370 return MVT::i32;
371 }
getPreferredVectorAction(EVT VT)372 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
373 const override {
374 // Widen subvectors to the full width rather than promoting integer
375 // elements. This is better because:
376 //
377 // (a) it means that we can handle the ABI for passing and returning
378 // sub-128 vectors without having to handle them as legal types.
379 //
380 // (b) we don't have instructions to extend on load and truncate on store,
381 // so promoting the integers is less efficient.
382 //
383 // (c) there are no multiplication instructions for the widest integer
384 // type (v2i64).
385 if (VT.getVectorElementType().getSizeInBits() % 8 == 0)
386 return TypeWidenVector;
387 return TargetLoweringBase::getPreferredVectorAction(VT);
388 }
389 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
390 EVT) const override;
391 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
392 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
393 bool isLegalICmpImmediate(int64_t Imm) const override;
394 bool isLegalAddImmediate(int64_t Imm) const override;
395 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
396 unsigned AS) const override;
397 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
398 unsigned Align,
399 bool *Fast) const override;
400 bool isTruncateFree(Type *, Type *) const override;
401 bool isTruncateFree(EVT, EVT) const override;
402 const char *getTargetNodeName(unsigned Opcode) const override;
403 std::pair<unsigned, const TargetRegisterClass *>
404 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
405 StringRef Constraint, MVT VT) const override;
406 TargetLowering::ConstraintType
407 getConstraintType(StringRef Constraint) const override;
408 TargetLowering::ConstraintWeight
409 getSingleConstraintMatchWeight(AsmOperandInfo &info,
410 const char *constraint) const override;
411 void LowerAsmOperandForConstraint(SDValue Op,
412 std::string &Constraint,
413 std::vector<SDValue> &Ops,
414 SelectionDAG &DAG) const override;
415
getInlineAsmMemConstraint(StringRef ConstraintCode)416 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
417 if (ConstraintCode.size() == 1) {
418 switch(ConstraintCode[0]) {
419 default:
420 break;
421 case 'Q':
422 return InlineAsm::Constraint_Q;
423 case 'R':
424 return InlineAsm::Constraint_R;
425 case 'S':
426 return InlineAsm::Constraint_S;
427 case 'T':
428 return InlineAsm::Constraint_T;
429 }
430 }
431 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
432 }
433
434 /// If a physical register, this returns the register that receives the
435 /// exception address on entry to an EH pad.
436 unsigned
getExceptionPointerRegister(const Constant * PersonalityFn)437 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
438 return SystemZ::R6D;
439 }
440
441 /// If a physical register, this returns the register that receives the
442 /// exception typeid on entry to a landing pad.
443 unsigned
getExceptionSelectorRegister(const Constant * PersonalityFn)444 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
445 return SystemZ::R7D;
446 }
447
448 /// Override to support customized stack guard loading.
useLoadStackGuardNode()449 bool useLoadStackGuardNode() const override {
450 return true;
451 }
insertSSPDeclarations(Module & M)452 void insertSSPDeclarations(Module &M) const override {
453 }
454
455 MachineBasicBlock *
456 EmitInstrWithCustomInserter(MachineInstr &MI,
457 MachineBasicBlock *BB) const override;
458 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
459 bool allowTruncateForTailCall(Type *, Type *) const override;
460 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
461 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
462 bool isVarArg,
463 const SmallVectorImpl<ISD::InputArg> &Ins,
464 const SDLoc &DL, SelectionDAG &DAG,
465 SmallVectorImpl<SDValue> &InVals) const override;
466 SDValue LowerCall(CallLoweringInfo &CLI,
467 SmallVectorImpl<SDValue> &InVals) const override;
468
469 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
470 bool isVarArg,
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
472 LLVMContext &Context) const override;
473 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
474 const SmallVectorImpl<ISD::OutputArg> &Outs,
475 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
476 SelectionDAG &DAG) const override;
477 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
478 SelectionDAG &DAG) const override;
479 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
480
getExtendForAtomicOps()481 ISD::NodeType getExtendForAtomicOps() const override {
482 return ISD::ANY_EXTEND;
483 }
484
supportSwiftError()485 bool supportSwiftError() const override {
486 return true;
487 }
488
489 private:
490 const SystemZSubtarget &Subtarget;
491
492 // Implement LowerOperation for individual opcodes.
493 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
494 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
495 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
496 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
497 SelectionDAG &DAG) const;
498 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
499 SelectionDAG &DAG, unsigned Opcode,
500 SDValue GOTOffset) const;
501 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
502 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
503 SelectionDAG &DAG) const;
504 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
505 SelectionDAG &DAG) const;
506 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
507 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
508 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
509 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
510 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
511 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
512 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
513 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
514 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
515 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
516 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
517 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
518 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
519 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
520 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
521 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
522 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
523 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
524 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
525 unsigned Opcode) const;
526 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
527 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
528 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
529 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
530 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
531 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
532 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
533 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
534 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
540 unsigned UnpackHigh) const;
541 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
542
543 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
544 unsigned Index, DAGCombinerInfo &DCI,
545 bool Force) const;
546 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
547 DAGCombinerInfo &DCI) const;
548 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
549 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
550 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
551 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
552 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
553 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
554 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
555 SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
556
557 // If the last instruction before MBBI in MBB was some form of COMPARE,
558 // try to replace it with a COMPARE AND BRANCH just before MBBI.
559 // CCMask and Target are the BRC-like operands for the branch.
560 // Return true if the change was made.
561 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
562 MachineBasicBlock::iterator MBBI,
563 unsigned CCMask,
564 MachineBasicBlock *Target) const;
565
566 // Implement EmitInstrWithCustomInserter for individual operation types.
567 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
568 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
569 unsigned StoreOpcode, unsigned STOCOpcode,
570 bool Invert) const;
571 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
572 bool ClearEven, unsigned SubReg) const;
573 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
574 MachineBasicBlock *BB,
575 unsigned BinOpcode, unsigned BitSize,
576 bool Invert = false) const;
577 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
578 MachineBasicBlock *MBB,
579 unsigned CompareOpcode,
580 unsigned KeepOldMask,
581 unsigned BitSize) const;
582 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
583 MachineBasicBlock *BB) const;
584 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
585 unsigned Opcode) const;
586 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
587 unsigned Opcode) const;
588 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
589 MachineBasicBlock *MBB,
590 unsigned Opcode, bool NoFloat) const;
591 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
592 MachineBasicBlock *MBB,
593 unsigned Opcode) const;
594 };
595 } // end namespace llvm
596
597 #endif
598