1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "Hexagon.h"
11 #include "MCTargetDesc/HexagonBaseInfo.h"
12 #include "MCTargetDesc/HexagonFixupKinds.h"
13 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/EndianStream.h"
26 #include "llvm/Support/raw_ostream.h"
27
28 #define DEBUG_TYPE "mccodeemitter"
29
30 using namespace llvm;
31 using namespace Hexagon;
32
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
34
HexagonMCCodeEmitter(MCInstrInfo const & aMII,MCContext & aMCT)35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
36 MCContext &aMCT)
37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38 Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
39
parseBits(size_t Instruction,size_t Last,MCInst const & MCB,MCInst const & MCI) const40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
41 MCInst const &MCB,
42 MCInst const &MCI) const {
43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
44 if (Instruction == 0) {
45 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
46 assert(!Duplex);
47 assert(Instruction != Last);
48 return HexagonII::INST_PARSE_LOOP_END;
49 }
50 }
51 if (Instruction == 1) {
52 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
53 assert(!Duplex);
54 assert(Instruction != Last);
55 return HexagonII::INST_PARSE_LOOP_END;
56 }
57 }
58 if (Duplex) {
59 assert(Instruction == Last);
60 return HexagonII::INST_PARSE_DUPLEX;
61 }
62 if(Instruction == Last)
63 return HexagonII::INST_PARSE_PACKET_END;
64 return HexagonII::INST_PARSE_NOT_END;
65 }
66
encodeInstruction(MCInst const & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,MCSubtargetInfo const & STI) const67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
68 SmallVectorImpl<MCFixup> &Fixups,
69 MCSubtargetInfo const &STI) const {
70 MCInst &HMB = const_cast<MCInst &>(MI);
71
72 assert(HexagonMCInstrInfo::isBundle(HMB));
73 DEBUG(dbgs() << "Encoding bundle\n";);
74 *Addend = 0;
75 *Extended = false;
76 *CurrentBundle = &MI;
77 size_t Instruction = 0;
78 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
79 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
80 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
81 EncodeSingleInstruction(HMI, OS, Fixups, STI,
82 parseBits(Instruction, Last, HMB, HMI),
83 Instruction);
84 *Extended = HexagonMCInstrInfo::isImmext(HMI);
85 *Addend += HEXAGON_INSTR_SIZE;
86 ++Instruction;
87 }
88 return;
89 }
90
RegisterMatches(unsigned Consumer,unsigned Producer,unsigned Producer2)91 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
92 unsigned Producer2) {
93 if (Consumer == Producer)
94 return true;
95 if (Consumer == Producer2)
96 return true;
97 // Calculate if we're a single vector consumer referencing a double producer
98 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
99 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
100 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
101 return false;
102 }
103
104 /// EncodeSingleInstruction - Emit a single
EncodeSingleInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,uint32_t Parse,size_t Index) const105 void HexagonMCCodeEmitter::EncodeSingleInstruction(
106 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
107 const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
108 MCInst HMB = MI;
109 assert(!HexagonMCInstrInfo::isBundle(HMB));
110 uint64_t Binary;
111
112 // Compound instructions are limited to using registers 0-7 and 16-23
113 // and here we make a map 16-23 to 8-15 so they can be correctly encoded.
114 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10,
115 Hexagon::R11, Hexagon::R12, Hexagon::R13,
116 Hexagon::R14, Hexagon::R15};
117
118 // Pseudo instructions don't get encoded and shouldn't be here
119 // in the first place!
120 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
121 "pseudo-instruction found");
122 DEBUG(dbgs() << "Encoding insn"
123 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
124 "\n");
125
126 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
127 for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
128 if (HMB.getOperand(i).isReg()) {
129 unsigned Reg =
130 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
131 if ((Reg <= 23) && (Reg >= 16))
132 HMB.getOperand(i).setReg(RegMap[Reg - 16]);
133 }
134 }
135
136 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
137 // Calculate the new value distance to the associated producer
138 MCOperand &MCO =
139 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
140 unsigned SOffset = 0;
141 unsigned VOffset = 0;
142 unsigned Register = MCO.getReg();
143 unsigned Register1;
144 unsigned Register2;
145 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
146 auto i = Instructions.begin() + Index - 1;
147 for (;; --i) {
148 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
149 MCInst const &Inst = *i->getInst();
150 if (HexagonMCInstrInfo::isImmext(Inst))
151 continue;
152 ++SOffset;
153 if (HexagonMCInstrInfo::isVector(MCII, Inst))
154 // Vector instructions don't count scalars
155 ++VOffset;
156 Register1 =
157 HexagonMCInstrInfo::hasNewValue(MCII, Inst)
158 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
159 : static_cast<unsigned>(Hexagon::NoRegister);
160 Register2 =
161 HexagonMCInstrInfo::hasNewValue2(MCII, Inst)
162 ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg()
163 : static_cast<unsigned>(Hexagon::NoRegister);
164 if (!RegisterMatches(Register, Register1, Register2))
165 // This isn't the register we're looking for
166 continue;
167 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
168 // Producer is unpredicated
169 break;
170 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
171 "Unpredicated consumer depending on predicated producer");
172 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
173 HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
174 // Producer predicate sense matched ours
175 break;
176 }
177 // Hexagon PRM 10.11 Construct Nt from distance
178 unsigned Offset =
179 HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset;
180 Offset <<= 1;
181 Offset |=
182 HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2);
183 MCO.setReg(Offset + Hexagon::R0);
184 }
185
186 Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
187 // Check for unimplemented instructions. Immediate extenders
188 // are encoded as zero, so they need to be accounted for.
189 if ((!Binary) &&
190 ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
191 (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
192 (HMB.getOpcode() != A4_ext_g))) {
193 DEBUG(dbgs() << "Unimplemented inst: "
194 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
195 "\n");
196 llvm_unreachable("Unimplemented Instruction");
197 }
198 Binary |= Parse;
199
200 // if we need to emit a duplexed instruction
201 if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
202 HMB.getOpcode() <= Hexagon::DuplexIClassF) {
203 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
204 "Emitting duplex without duplex parse bits");
205 unsigned dupIClass;
206 switch (HMB.getOpcode()) {
207 case Hexagon::DuplexIClass0:
208 dupIClass = 0;
209 break;
210 case Hexagon::DuplexIClass1:
211 dupIClass = 1;
212 break;
213 case Hexagon::DuplexIClass2:
214 dupIClass = 2;
215 break;
216 case Hexagon::DuplexIClass3:
217 dupIClass = 3;
218 break;
219 case Hexagon::DuplexIClass4:
220 dupIClass = 4;
221 break;
222 case Hexagon::DuplexIClass5:
223 dupIClass = 5;
224 break;
225 case Hexagon::DuplexIClass6:
226 dupIClass = 6;
227 break;
228 case Hexagon::DuplexIClass7:
229 dupIClass = 7;
230 break;
231 case Hexagon::DuplexIClass8:
232 dupIClass = 8;
233 break;
234 case Hexagon::DuplexIClass9:
235 dupIClass = 9;
236 break;
237 case Hexagon::DuplexIClassA:
238 dupIClass = 10;
239 break;
240 case Hexagon::DuplexIClassB:
241 dupIClass = 11;
242 break;
243 case Hexagon::DuplexIClassC:
244 dupIClass = 12;
245 break;
246 case Hexagon::DuplexIClassD:
247 dupIClass = 13;
248 break;
249 case Hexagon::DuplexIClassE:
250 dupIClass = 14;
251 break;
252 case Hexagon::DuplexIClassF:
253 dupIClass = 15;
254 break;
255 default:
256 llvm_unreachable("Unimplemented DuplexIClass");
257 break;
258 }
259 // 29 is the bit position.
260 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
261 // Last bit is moved to bit position 13
262 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
263
264 const MCInst *subInst0 = HMB.getOperand(0).getInst();
265 const MCInst *subInst1 = HMB.getOperand(1).getInst();
266
267 // get subinstruction slot 0
268 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
269 // get subinstruction slot 1
270 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
271
272 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
273 }
274 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
275 ++MCNumEmitted;
276 }
277
278 namespace {
raise_relocation_error(unsigned bits,unsigned kind)279 void raise_relocation_error(unsigned bits, unsigned kind) {
280 std::string Text;
281 {
282 llvm::raw_string_ostream Stream(Text);
283 Stream << "Unrecognized relocation combination bits: " << bits
284 << " kind: " << kind;
285 }
286 report_fatal_error(Text);
287 }
288 }
289
290 /// getFixupNoBits - Some insns are not extended and thus have no
291 /// bits. These cases require a more brute force method for determining
292 /// the correct relocation.
293 namespace {
getFixupNoBits(MCInstrInfo const & MCII,const MCInst & MI,const MCOperand & MO,const MCSymbolRefExpr::VariantKind kind)294 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
295 const MCOperand &MO,
296 const MCSymbolRefExpr::VariantKind kind) {
297 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
298 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
299
300 if (insnType == HexagonII::TypePREFIX) {
301 switch (kind) {
302 case MCSymbolRefExpr::VK_GOTREL:
303 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
304 case MCSymbolRefExpr::VK_GOT:
305 return Hexagon::fixup_Hexagon_GOT_32_6_X;
306 case MCSymbolRefExpr::VK_TPREL:
307 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
308 case MCSymbolRefExpr::VK_DTPREL:
309 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
310 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
311 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
312 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
313 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
314 case MCSymbolRefExpr::VK_Hexagon_IE:
315 return Hexagon::fixup_Hexagon_IE_32_6_X;
316 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
317 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
318 case MCSymbolRefExpr::VK_Hexagon_PCREL:
319 case MCSymbolRefExpr::VK_None:
320 if (MCID.isBranch())
321 return Hexagon::fixup_Hexagon_B32_PCREL_X;
322 else
323 return Hexagon::fixup_Hexagon_32_6_X;
324 default:
325 raise_relocation_error(0, kind);
326 }
327 } else if (MCID.isBranch())
328 return Hexagon::fixup_Hexagon_B13_PCREL;
329
330 switch (MCID.getOpcode()) {
331 case Hexagon::HI:
332 case Hexagon::A2_tfrih:
333 switch (kind) {
334 case MCSymbolRefExpr::VK_GOT:
335 return Hexagon::fixup_Hexagon_GOT_HI16;
336 case MCSymbolRefExpr::VK_GOTREL:
337 return Hexagon::fixup_Hexagon_GOTREL_HI16;
338 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
339 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
340 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
341 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
342 case MCSymbolRefExpr::VK_Hexagon_IE:
343 return Hexagon::fixup_Hexagon_IE_HI16;
344 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
345 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
346 case MCSymbolRefExpr::VK_TPREL:
347 return Hexagon::fixup_Hexagon_TPREL_HI16;
348 case MCSymbolRefExpr::VK_DTPREL:
349 return Hexagon::fixup_Hexagon_DTPREL_HI16;
350 case MCSymbolRefExpr::VK_None:
351 return Hexagon::fixup_Hexagon_HI16;
352 default:
353 raise_relocation_error(0, kind);
354 }
355
356 case Hexagon::LO:
357 case Hexagon::A2_tfril:
358 switch (kind) {
359 case MCSymbolRefExpr::VK_GOT:
360 return Hexagon::fixup_Hexagon_GOT_LO16;
361 case MCSymbolRefExpr::VK_GOTREL:
362 return Hexagon::fixup_Hexagon_GOTREL_LO16;
363 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
364 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
365 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
366 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
367 case MCSymbolRefExpr::VK_Hexagon_IE:
368 return Hexagon::fixup_Hexagon_IE_LO16;
369 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
370 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
371 case MCSymbolRefExpr::VK_TPREL:
372 return Hexagon::fixup_Hexagon_TPREL_LO16;
373 case MCSymbolRefExpr::VK_DTPREL:
374 return Hexagon::fixup_Hexagon_DTPREL_LO16;
375 case MCSymbolRefExpr::VK_None:
376 return Hexagon::fixup_Hexagon_LO16;
377 default:
378 raise_relocation_error(0, kind);
379 }
380
381 // The only relocs left should be GP relative:
382 default:
383 if (MCID.mayStore() || MCID.mayLoad()) {
384 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
385 ++ImpUses) {
386 if (*ImpUses != Hexagon::GP)
387 continue;
388 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
389 case HexagonII::MemAccessSize::ByteAccess:
390 return fixup_Hexagon_GPREL16_0;
391 case HexagonII::MemAccessSize::HalfWordAccess:
392 return fixup_Hexagon_GPREL16_1;
393 case HexagonII::MemAccessSize::WordAccess:
394 return fixup_Hexagon_GPREL16_2;
395 case HexagonII::MemAccessSize::DoubleWordAccess:
396 return fixup_Hexagon_GPREL16_3;
397 default:
398 raise_relocation_error(0, kind);
399 }
400 }
401 }
402 raise_relocation_error(0, kind);
403 }
404 llvm_unreachable("Relocation exit not taken");
405 }
406 }
407
408 namespace llvm {
409 extern const MCInstrDesc HexagonInsts[];
410 }
411
412 namespace {
isPCRel(unsigned Kind)413 bool isPCRel (unsigned Kind) {
414 switch(Kind){
415 case fixup_Hexagon_B22_PCREL:
416 case fixup_Hexagon_B15_PCREL:
417 case fixup_Hexagon_B7_PCREL:
418 case fixup_Hexagon_B13_PCREL:
419 case fixup_Hexagon_B9_PCREL:
420 case fixup_Hexagon_B32_PCREL_X:
421 case fixup_Hexagon_B22_PCREL_X:
422 case fixup_Hexagon_B15_PCREL_X:
423 case fixup_Hexagon_B13_PCREL_X:
424 case fixup_Hexagon_B9_PCREL_X:
425 case fixup_Hexagon_B7_PCREL_X:
426 case fixup_Hexagon_32_PCREL:
427 case fixup_Hexagon_PLT_B22_PCREL:
428 case fixup_Hexagon_GD_PLT_B22_PCREL:
429 case fixup_Hexagon_LD_PLT_B22_PCREL:
430 case fixup_Hexagon_6_PCREL_X:
431 return true;
432 default:
433 return false;
434 }
435 }
436 }
437
getExprOpValue(const MCInst & MI,const MCOperand & MO,const MCExpr * ME,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const438 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
439 const MCOperand &MO,
440 const MCExpr *ME,
441 SmallVectorImpl<MCFixup> &Fixups,
442 const MCSubtargetInfo &STI) const
443
444 {
445 if (isa<HexagonMCExpr>(ME))
446 ME = &HexagonMCInstrInfo::getExpr(*ME);
447 int64_t Value;
448 if (ME->evaluateAsAbsolute(Value))
449 return Value;
450 assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary);
451 if (ME->getKind() == MCExpr::Binary) {
452 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
453 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
454 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
455 return 0;
456 }
457 Hexagon::Fixups FixupKind =
458 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
459 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
460 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
461 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
462 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
463 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
464
465 DEBUG(dbgs() << "----------------------------------------\n");
466 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
467 << "\n");
468 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
469 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
470 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
471 DEBUG(dbgs() << "----------------------------------------\n");
472
473 switch (bits) {
474 default:
475 raise_relocation_error(bits, kind);
476 case 32:
477 switch (kind) {
478 case MCSymbolRefExpr::VK_DTPREL:
479 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
480 : Hexagon::fixup_Hexagon_DTPREL_32;
481 break;
482 case MCSymbolRefExpr::VK_GOT:
483 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
484 : Hexagon::fixup_Hexagon_GOT_32;
485 break;
486 case MCSymbolRefExpr::VK_GOTREL:
487 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
488 : Hexagon::fixup_Hexagon_GOTREL_32;
489 break;
490 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
491 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
492 : Hexagon::fixup_Hexagon_GD_GOT_32;
493 break;
494 case MCSymbolRefExpr::VK_Hexagon_IE:
495 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
496 : Hexagon::fixup_Hexagon_IE_32;
497 break;
498 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
499 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
500 : Hexagon::fixup_Hexagon_IE_GOT_32;
501 break;
502 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
503 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
504 : Hexagon::fixup_Hexagon_LD_GOT_32;
505 break;
506 case MCSymbolRefExpr::VK_Hexagon_PCREL:
507 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
508 break;
509 case MCSymbolRefExpr::VK_None:
510 FixupKind =
511 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
512 break;
513 case MCSymbolRefExpr::VK_TPREL:
514 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
515 : Hexagon::fixup_Hexagon_TPREL_32;
516 break;
517 default:
518 raise_relocation_error(bits, kind);
519 }
520 break;
521
522 case 22:
523 switch (kind) {
524 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
525 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
526 break;
527 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
528 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
529 break;
530 case MCSymbolRefExpr::VK_None:
531 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
532 : Hexagon::fixup_Hexagon_B22_PCREL;
533 break;
534 case MCSymbolRefExpr::VK_PLT:
535 FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL;
536 break;
537 default:
538 raise_relocation_error(bits, kind);
539 }
540 break;
541
542 case 16:
543 if (*Extended) {
544 switch (kind) {
545 case MCSymbolRefExpr::VK_DTPREL:
546 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
547 break;
548 case MCSymbolRefExpr::VK_GOT:
549 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
550 break;
551 case MCSymbolRefExpr::VK_GOTREL:
552 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
553 break;
554 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
555 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
556 break;
557 case MCSymbolRefExpr::VK_Hexagon_IE:
558 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
559 break;
560 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
561 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
562 break;
563 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
564 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
565 break;
566 case MCSymbolRefExpr::VK_None:
567 FixupKind = Hexagon::fixup_Hexagon_16_X;
568 break;
569 case MCSymbolRefExpr::VK_TPREL:
570 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
571 break;
572 default:
573 raise_relocation_error(bits, kind);
574 }
575 } else
576 switch (kind) {
577 case MCSymbolRefExpr::VK_None: {
578 if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr()))
579 FixupKind = Hexagon::fixup_Hexagon_23_REG;
580 else
581 raise_relocation_error(bits, kind);
582 break;
583 }
584 case MCSymbolRefExpr::VK_DTPREL:
585 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
586 break;
587 case MCSymbolRefExpr::VK_GOTREL:
588 if (MCID.getOpcode() == Hexagon::HI)
589 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
590 else
591 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
592 break;
593 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
594 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
595 break;
596 case MCSymbolRefExpr::VK_Hexagon_GPREL:
597 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
598 break;
599 case MCSymbolRefExpr::VK_Hexagon_HI16:
600 FixupKind = Hexagon::fixup_Hexagon_HI16;
601 break;
602 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
603 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
604 break;
605 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
606 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
607 break;
608 case MCSymbolRefExpr::VK_Hexagon_LO16:
609 FixupKind = Hexagon::fixup_Hexagon_LO16;
610 break;
611 case MCSymbolRefExpr::VK_TPREL:
612 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
613 break;
614 default:
615 raise_relocation_error(bits, kind);
616 }
617 break;
618
619 case 15:
620 switch (kind) {
621 case MCSymbolRefExpr::VK_None:
622 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
623 : Hexagon::fixup_Hexagon_B15_PCREL;
624 break;
625 default:
626 raise_relocation_error(bits, kind);
627 }
628 break;
629
630 case 13:
631 switch (kind) {
632 case MCSymbolRefExpr::VK_None:
633 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
634 break;
635 default:
636 raise_relocation_error(bits, kind);
637 }
638 break;
639
640 case 12:
641 if (*Extended)
642 switch (kind) {
643 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
644 case MCSymbolRefExpr::VK_GOT:
645 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
646 break;
647 case MCSymbolRefExpr::VK_GOTREL:
648 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
649 break;
650 case MCSymbolRefExpr::VK_None:
651 FixupKind = Hexagon::fixup_Hexagon_12_X;
652 break;
653 default:
654 raise_relocation_error(bits, kind);
655 }
656 else
657 raise_relocation_error(bits, kind);
658 break;
659
660 case 11:
661 if (*Extended)
662 switch (kind) {
663 case MCSymbolRefExpr::VK_DTPREL:
664 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
665 break;
666 case MCSymbolRefExpr::VK_GOT:
667 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
668 break;
669 case MCSymbolRefExpr::VK_GOTREL:
670 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
671 break;
672 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
673 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
674 break;
675 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
676 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
677 break;
678 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
679 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
680 break;
681 case MCSymbolRefExpr::VK_None:
682 FixupKind = Hexagon::fixup_Hexagon_11_X;
683 break;
684 case MCSymbolRefExpr::VK_TPREL:
685 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
686 break;
687 default:
688 raise_relocation_error(bits, kind);
689 }
690 else {
691 switch (kind) {
692 case MCSymbolRefExpr::VK_TPREL:
693 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
694 break;
695 default:
696 raise_relocation_error(bits, kind);
697 }
698 }
699 break;
700
701 case 10:
702 if (*Extended) {
703 switch (kind) {
704 case MCSymbolRefExpr::VK_None:
705 FixupKind = Hexagon::fixup_Hexagon_10_X;
706 break;
707 default:
708 raise_relocation_error(bits, kind);
709 }
710 } else
711 raise_relocation_error(bits, kind);
712 break;
713
714 case 9:
715 if (MCID.isBranch() ||
716 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
717 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
718 : Hexagon::fixup_Hexagon_B9_PCREL;
719 else if (*Extended)
720 FixupKind = Hexagon::fixup_Hexagon_9_X;
721 else
722 raise_relocation_error(bits, kind);
723 break;
724
725 case 8:
726 if (*Extended)
727 FixupKind = Hexagon::fixup_Hexagon_8_X;
728 else
729 raise_relocation_error(bits, kind);
730 break;
731
732 case 7:
733 if (MCID.isBranch() ||
734 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
735 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
736 : Hexagon::fixup_Hexagon_B7_PCREL;
737 else if (*Extended)
738 FixupKind = Hexagon::fixup_Hexagon_7_X;
739 else
740 raise_relocation_error(bits, kind);
741 break;
742
743 case 6:
744 if (*Extended) {
745 switch (kind) {
746 case MCSymbolRefExpr::VK_DTPREL:
747 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
748 break;
749 // This is part of an extender, GOT_11 is a
750 // Word32_U6 unsigned/truncated reloc.
751 case MCSymbolRefExpr::VK_GOT:
752 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
753 break;
754 case MCSymbolRefExpr::VK_GOTREL:
755 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
756 break;
757 case MCSymbolRefExpr::VK_Hexagon_PCREL:
758 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
759 break;
760 case MCSymbolRefExpr::VK_TPREL:
761 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
762 break;
763 case MCSymbolRefExpr::VK_None:
764 FixupKind = Hexagon::fixup_Hexagon_6_X;
765 break;
766 default:
767 raise_relocation_error(bits, kind);
768 }
769 } else
770 raise_relocation_error(bits, kind);
771 break;
772
773 case 0:
774 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
775 break;
776 }
777
778 MCExpr const *FixupExpression =
779 (*Addend > 0 && isPCRel(FixupKind))
780 ? MCBinaryExpr::createAdd(MO.getExpr(),
781 MCConstantExpr::create(*Addend, MCT), MCT)
782 : MO.getExpr();
783
784 MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
785 MCFixupKind(FixupKind), MI.getLoc());
786 Fixups.push_back(fixup);
787 // All of the information is in the fixup.
788 return 0;
789 }
790
791 unsigned
getMachineOpValue(MCInst const & MI,MCOperand const & MO,SmallVectorImpl<MCFixup> & Fixups,MCSubtargetInfo const & STI) const792 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
793 SmallVectorImpl<MCFixup> &Fixups,
794 MCSubtargetInfo const &STI) const {
795 assert(!MO.isImm());
796 if (MO.isReg()) {
797 unsigned Reg = MO.getReg();
798 if (HexagonMCInstrInfo::isSubInstruction(MI))
799 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
800 switch(MI.getOpcode()){
801 case Hexagon::A2_tfrrcr:
802 case Hexagon::A2_tfrcrr:
803 if(Reg == Hexagon::M0)
804 Reg = Hexagon::C6;
805 if(Reg == Hexagon::M1)
806 Reg = Hexagon::C7;
807 }
808 return MCT.getRegisterInfo()->getEncodingValue(Reg);
809 }
810
811 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
812 }
813
createHexagonMCCodeEmitter(MCInstrInfo const & MII,MCRegisterInfo const & MRI,MCContext & MCT)814 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
815 MCRegisterInfo const &MRI,
816 MCContext &MCT) {
817 return new HexagonMCCodeEmitter(MII, MCT);
818 }
819
820 #include "HexagonGenMCCodeEmitter.inc"
821