1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include <stdbool.h>
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
42
43 #include "isl/isl.h"
44 #include "blorp/blorp.h"
45
46 #ifdef __cplusplus
47 extern "C" {
48 /* Evil hack for using libdrm in a c++ compiler. */
49 #define virtual virt
50 #endif
51
52 #include <intel_bufmgr.h>
53 #ifdef __cplusplus
54 #undef virtual
55 }
56 #endif
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
65
66 /* Glossary:
67 *
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
71 *
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
75 *
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
79 *
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
82 *
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
89 *
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
96 *
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
99 *
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
103 *
104 * Fixed function units:
105 *
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
108 * CURBEs.
109 *
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
115 *
116 * HS - Hull Shader (Tessellation Control Shader)
117 *
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
119 *
120 * DS - Domain Shader (Tessellation Evaluation Shader)
121 *
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
130 *
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
136 *
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
140 *
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
144 *
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
147 */
148
149 struct brw_context;
150 struct brw_inst;
151 struct brw_vs_prog_key;
152 struct brw_vue_prog_key;
153 struct brw_wm_prog_key;
154 struct brw_wm_prog_data;
155 struct brw_cs_prog_key;
156 struct brw_cs_prog_data;
157
158 enum brw_pipeline {
159 BRW_RENDER_PIPELINE,
160 BRW_COMPUTE_PIPELINE,
161
162 BRW_NUM_PIPELINES
163 };
164
165 enum brw_cache_id {
166 BRW_CACHE_FS_PROG,
167 BRW_CACHE_BLORP_PROG,
168 BRW_CACHE_SF_PROG,
169 BRW_CACHE_VS_PROG,
170 BRW_CACHE_FF_GS_PROG,
171 BRW_CACHE_GS_PROG,
172 BRW_CACHE_TCS_PROG,
173 BRW_CACHE_TES_PROG,
174 BRW_CACHE_CLIP_PROG,
175 BRW_CACHE_CS_PROG,
176
177 BRW_MAX_CACHE
178 };
179
180 enum brw_state_id {
181 /* brw_cache_ids must come first - see brw_program_cache.c */
182 BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
183 BRW_STATE_FRAGMENT_PROGRAM,
184 BRW_STATE_GEOMETRY_PROGRAM,
185 BRW_STATE_TESS_PROGRAMS,
186 BRW_STATE_VERTEX_PROGRAM,
187 BRW_STATE_CURBE_OFFSETS,
188 BRW_STATE_REDUCED_PRIMITIVE,
189 BRW_STATE_PATCH_PRIMITIVE,
190 BRW_STATE_PRIMITIVE,
191 BRW_STATE_CONTEXT,
192 BRW_STATE_PSP,
193 BRW_STATE_SURFACES,
194 BRW_STATE_BINDING_TABLE_POINTERS,
195 BRW_STATE_INDICES,
196 BRW_STATE_VERTICES,
197 BRW_STATE_DEFAULT_TESS_LEVELS,
198 BRW_STATE_BATCH,
199 BRW_STATE_INDEX_BUFFER,
200 BRW_STATE_VS_CONSTBUF,
201 BRW_STATE_TCS_CONSTBUF,
202 BRW_STATE_TES_CONSTBUF,
203 BRW_STATE_GS_CONSTBUF,
204 BRW_STATE_PROGRAM_CACHE,
205 BRW_STATE_STATE_BASE_ADDRESS,
206 BRW_STATE_VUE_MAP_GEOM_OUT,
207 BRW_STATE_TRANSFORM_FEEDBACK,
208 BRW_STATE_RASTERIZER_DISCARD,
209 BRW_STATE_STATS_WM,
210 BRW_STATE_UNIFORM_BUFFER,
211 BRW_STATE_ATOMIC_BUFFER,
212 BRW_STATE_IMAGE_UNITS,
213 BRW_STATE_META_IN_PROGRESS,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION,
215 BRW_STATE_NUM_SAMPLES,
216 BRW_STATE_TEXTURE_BUFFER,
217 BRW_STATE_GEN4_UNIT_STATE,
218 BRW_STATE_CC_VP,
219 BRW_STATE_SF_VP,
220 BRW_STATE_CLIP_VP,
221 BRW_STATE_SAMPLER_STATE_TABLE,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS,
223 BRW_STATE_COMPUTE_PROGRAM,
224 BRW_STATE_CS_WORK_GROUPS,
225 BRW_STATE_URB_SIZE,
226 BRW_STATE_CC_STATE,
227 BRW_STATE_BLORP,
228 BRW_STATE_VIEWPORT_COUNT,
229 BRW_STATE_CONSERVATIVE_RASTERIZATION,
230 BRW_NUM_STATE_BITS
231 };
232
233 /**
234 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
235 *
236 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
237 * When the currently bound shader program differs from the previous draw
238 * call, these will be flagged. They cover brw->{stage}_program and
239 * ctx->{Stage}Program->_Current.
240 *
241 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
242 * driver perspective. Even if the same shader is bound at the API level,
243 * we may need to switch between multiple versions of that shader to handle
244 * changes in non-orthagonal state.
245 *
246 * Additionally, multiple shader programs may have identical vertex shaders
247 * (for example), or compile down to the same code in the backend. We combine
248 * those into a single program cache entry.
249 *
250 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
251 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
252 */
253 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
254 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
255 * use the normal state upload paths), but the cache is still used. To avoid
256 * polluting the brw_program_cache code with special cases, we retain the
257 * dirty bit for now. It should eventually be removed.
258 */
259 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
260 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
261 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
262 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
263 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
264 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
265 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
266 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
267 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
268 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
269 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
270 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
271 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
272 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
273 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
274 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
275 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
276 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
277 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
278 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
279 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
280 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
281 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
282 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
283 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
284 /**
285 * Used for any batch entry with a relocated pointer that will be used
286 * by any 3D rendering.
287 */
288 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
289 /** \see brw.state.depth_region */
290 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
291 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
292 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
293 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
294 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
295 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
296 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
297 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
298 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
299 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
300 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
301 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
302 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
303 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
304 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
305 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
306 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
307 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
308 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
309 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
310 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
311 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
312 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
313 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
314 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
315 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
316 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
317 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
318 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
319 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
321
322 struct brw_state_flags {
323 /** State update flags signalled by mesa internals */
324 GLuint mesa;
325 /**
326 * State update flags signalled as the result of brw_tracked_state updates
327 */
328 uint64_t brw;
329 };
330
331
332 /** Subclass of Mesa program */
333 struct brw_program {
334 struct gl_program program;
335 GLuint id;
336
337 bool compiled_once;
338 };
339
340
341 /**
342 * Bitmask indicating which fragment shader inputs represent varyings (and
343 * hence have to be delivered to the fragment shader by the SF/SBE stage).
344 */
345 #define BRW_FS_VARYING_INPUT_MASK \
346 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
347 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
348
349
350 struct brw_sf_prog_data {
351 GLuint urb_read_length;
352 GLuint total_grf;
353
354 /* Each vertex may have upto 12 attributes, 4 components each,
355 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
356 * rows.
357 *
358 * Actually we use 4 for each, so call it 12 rows.
359 */
360 GLuint urb_entry_size;
361 };
362
363
364 /**
365 * We always program SF to start reading at an offset of 1 (2 varying slots)
366 * from the start of the vertex URB entry. This causes it to skip:
367 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
368 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
369 */
370 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
371
372
373 struct brw_clip_prog_data {
374 GLuint curb_read_length; /* user planes? */
375 GLuint clip_mode;
376 GLuint urb_read_length;
377 GLuint total_grf;
378 };
379
380 struct brw_ff_gs_prog_data {
381 GLuint urb_read_length;
382 GLuint total_grf;
383
384 /**
385 * Gen6 transform feedback: Amount by which the streaming vertex buffer
386 * indices should be incremented each time the GS is invoked.
387 */
388 unsigned svbi_postincrement_value;
389 };
390
391 /** Number of texture sampler units */
392 #define BRW_MAX_TEX_UNIT 32
393
394 /** Max number of render targets in a shader */
395 #define BRW_MAX_DRAW_BUFFERS 8
396
397 /** Max number of UBOs in a shader */
398 #define BRW_MAX_UBO 14
399
400 /** Max number of SSBOs in a shader */
401 #define BRW_MAX_SSBO 12
402
403 /** Max number of atomic counter buffer objects in a shader */
404 #define BRW_MAX_ABO 16
405
406 /** Max number of image uniforms in a shader */
407 #define BRW_MAX_IMAGES 32
408
409 /**
410 * Max number of binding table entries used for stream output.
411 *
412 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
413 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
414 *
415 * On Gen6, the size of transform feedback data is limited not by the number
416 * of components but by the number of binding table entries we set aside. We
417 * use one binding table entry for a float, one entry for a vector, and one
418 * entry per matrix column. Since the only way we can communicate our
419 * transform feedback capabilities to the client is via
420 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
421 * worst case, in which all the varyings are floats, so we use up one binding
422 * table entry per component. Therefore we need to set aside at least 64
423 * binding table entries for use by transform feedback.
424 *
425 * Note: since we don't currently pack varyings, it is currently impossible
426 * for the client to actually use up all of these binding table entries--if
427 * all of their varyings were floats, they would run out of varying slots and
428 * fail to link. But that's a bug, so it seems prudent to go ahead and
429 * allocate the number of binding table entries we will need once the bug is
430 * fixed.
431 */
432 #define BRW_MAX_SOL_BINDINGS 64
433
434 /** Maximum number of actual buffers used for stream output */
435 #define BRW_MAX_SOL_BUFFERS 4
436
437 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
438 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
439 BRW_MAX_UBO + \
440 BRW_MAX_SSBO + \
441 BRW_MAX_ABO + \
442 BRW_MAX_IMAGES + \
443 2 + /* shader time, pull constants */ \
444 1 /* cs num work groups */)
445
446 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
447
448 /**
449 * Stride in bytes between shader_time entries.
450 *
451 * We separate entries by a cacheline to reduce traffic between EUs writing to
452 * different entries.
453 */
454 #define SHADER_TIME_STRIDE 64
455
456 struct brw_cache {
457 struct brw_context *brw;
458
459 struct brw_cache_item **items;
460 drm_intel_bo *bo;
461 GLuint size, n_items;
462
463 uint32_t next_offset;
464 bool bo_used_by_gpu;
465 };
466
467
468 /* Considered adding a member to this struct to document which flags
469 * an update might raise so that ordering of the state atoms can be
470 * checked or derived at runtime. Dropped the idea in favor of having
471 * a debug mode where the state is monitored for flags which are
472 * raised that have already been tested against.
473 */
474 struct brw_tracked_state {
475 struct brw_state_flags dirty;
476 void (*emit)( struct brw_context *brw );
477 };
478
479 enum shader_time_shader_type {
480 ST_NONE,
481 ST_VS,
482 ST_TCS,
483 ST_TES,
484 ST_GS,
485 ST_FS8,
486 ST_FS16,
487 ST_CS,
488 };
489
490 struct brw_vertex_buffer {
491 /** Buffer object containing the uploaded vertex data */
492 drm_intel_bo *bo;
493 uint32_t offset;
494 uint32_t size;
495 /** Byte stride between elements in the uploaded array */
496 GLuint stride;
497 GLuint step_rate;
498 };
499 struct brw_vertex_element {
500 const struct gl_vertex_array *glarray;
501
502 int buffer;
503 bool is_dual_slot;
504 /** Offset of the first element within the buffer object */
505 unsigned int offset;
506 };
507
508 struct brw_query_object {
509 struct gl_query_object Base;
510
511 /** Last query BO associated with this query. */
512 drm_intel_bo *bo;
513
514 /** Last index in bo with query data for this object. */
515 int last_index;
516
517 /** True if we know the batch has been flushed since we ended the query. */
518 bool flushed;
519 };
520
521 enum brw_gpu_ring {
522 UNKNOWN_RING,
523 RENDER_RING,
524 BLT_RING,
525 };
526
527 struct intel_batchbuffer {
528 /** Current batchbuffer being queued up. */
529 drm_intel_bo *bo;
530 /** Last BO submitted to the hardware. Used for glFinish(). */
531 drm_intel_bo *last_bo;
532
533 #ifdef DEBUG
534 uint16_t emit, total;
535 #endif
536 uint16_t reserved_space;
537 uint32_t *map_next;
538 uint32_t *map;
539 uint32_t *cpu_map;
540 #define BATCH_SZ (8192*sizeof(uint32_t))
541
542 uint32_t state_batch_offset;
543 enum brw_gpu_ring ring;
544 bool needs_sol_reset;
545 bool state_base_address_emitted;
546
547 struct {
548 uint32_t *map_next;
549 int reloc_count;
550 } saved;
551 };
552
553 #define MAX_GS_INPUT_VERTICES 6
554
555 #define BRW_MAX_XFB_STREAMS 4
556
557 struct brw_transform_feedback_object {
558 struct gl_transform_feedback_object base;
559
560 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
561 drm_intel_bo *offset_bo;
562
563 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
564 bool zero_offsets;
565
566 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
567 GLenum primitive_mode;
568
569 /**
570 * Count of primitives generated during this transform feedback operation.
571 * @{
572 */
573 uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
574 drm_intel_bo *prim_count_bo;
575 unsigned prim_count_buffer_index; /**< in number of uint64_t units */
576 /** @} */
577
578 /**
579 * Number of vertices written between last Begin/EndTransformFeedback().
580 *
581 * Used to implement DrawTransformFeedback().
582 */
583 uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
584 bool vertices_written_valid;
585 };
586
587 /**
588 * Data shared between each programmable stage in the pipeline (vs, gs, and
589 * wm).
590 */
591 struct brw_stage_state
592 {
593 gl_shader_stage stage;
594 struct brw_stage_prog_data *prog_data;
595
596 /**
597 * Optional scratch buffer used to store spilled register values and
598 * variably-indexed GRF arrays.
599 *
600 * The contents of this buffer are short-lived so the same memory can be
601 * re-used at will for multiple shader programs (executed by the same fixed
602 * function). However reusing a scratch BO for which shader invocations
603 * are still in flight with a per-thread scratch slot size other than the
604 * original can cause threads with different scratch slot size and FFTID
605 * (which may be executed in parallel depending on the shader stage and
606 * hardware generation) to map to an overlapping region of the scratch
607 * space, which can potentially lead to mutual scratch space corruption.
608 * For that reason if you borrow this scratch buffer you should only be
609 * using the slot size given by the \c per_thread_scratch member below,
610 * unless you're taking additional measures to synchronize thread execution
611 * across slot size changes.
612 */
613 drm_intel_bo *scratch_bo;
614
615 /**
616 * Scratch slot size allocated for each thread in the buffer object given
617 * by \c scratch_bo.
618 */
619 uint32_t per_thread_scratch;
620
621 /** Offset in the program cache to the program */
622 uint32_t prog_offset;
623
624 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
625 uint32_t state_offset;
626
627 uint32_t push_const_offset; /* Offset in the batchbuffer */
628 int push_const_size; /* in 256-bit register increments */
629
630 /* Binding table: pointers to SURFACE_STATE entries. */
631 uint32_t bind_bo_offset;
632 uint32_t surf_offset[BRW_MAX_SURFACES];
633
634 /** SAMPLER_STATE count and table offset */
635 uint32_t sampler_count;
636 uint32_t sampler_offset;
637 };
638
639 enum brw_predicate_state {
640 /* The first two states are used if we can determine whether to draw
641 * without having to look at the values in the query object buffer. This
642 * will happen if there is no conditional render in progress, if the query
643 * object is already completed or if something else has already added
644 * samples to the preliminary result such as via a BLT command.
645 */
646 BRW_PREDICATE_STATE_RENDER,
647 BRW_PREDICATE_STATE_DONT_RENDER,
648 /* In this case whether to draw or not depends on the result of an
649 * MI_PREDICATE command so the predicate enable bit needs to be checked.
650 */
651 BRW_PREDICATE_STATE_USE_BIT
652 };
653
654 struct shader_times;
655
656 struct gen_l3_config;
657
658 /**
659 * brw_context is derived from gl_context.
660 */
661 struct brw_context
662 {
663 struct gl_context ctx; /**< base class, must be first field */
664
665 struct
666 {
667 uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
668 struct gl_renderbuffer *rb,
669 uint32_t flags, unsigned unit,
670 uint32_t surf_index);
671 void (*emit_null_surface_state)(struct brw_context *brw,
672 unsigned width,
673 unsigned height,
674 unsigned samples,
675 uint32_t *out_offset);
676
677 /**
678 * Send the appropriate state packets to configure depth, stencil, and
679 * HiZ buffers (i965+ only)
680 */
681 void (*emit_depth_stencil_hiz)(struct brw_context *brw,
682 struct intel_mipmap_tree *depth_mt,
683 uint32_t depth_offset,
684 uint32_t depthbuffer_format,
685 uint32_t depth_surface_type,
686 struct intel_mipmap_tree *stencil_mt,
687 bool hiz, bool separate_stencil,
688 uint32_t width, uint32_t height,
689 uint32_t tile_x, uint32_t tile_y);
690
691 } vtbl;
692
693 dri_bufmgr *bufmgr;
694
695 drm_intel_context *hw_ctx;
696
697 /** BO for post-sync nonzero writes for gen6 workaround. */
698 drm_intel_bo *workaround_bo;
699 uint8_t pipe_controls_since_last_cs_stall;
700
701 /**
702 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
703 * and would need flushing before being used from another cache domain that
704 * isn't coherent with it (i.e. the sampler).
705 */
706 struct set *render_cache;
707
708 /**
709 * Number of resets observed in the system at context creation.
710 *
711 * This is tracked in the context so that we can determine that another
712 * reset has occurred.
713 */
714 uint32_t reset_count;
715
716 struct intel_batchbuffer batch;
717 bool no_batch_wrap;
718
719 struct {
720 drm_intel_bo *bo;
721 uint32_t next_offset;
722 } upload;
723
724 /**
725 * Set if rendering has occurred to the drawable's front buffer.
726 *
727 * This is used in the DRI2 case to detect that glFlush should also copy
728 * the contents of the fake front buffer to the real front buffer.
729 */
730 bool front_buffer_dirty;
731
732 /** Framerate throttling: @{ */
733 drm_intel_bo *throttle_batch[2];
734
735 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
736 * frame of rendering to complete. This gives a very precise cap to the
737 * latency between input and output such that rendering never gets more
738 * than a frame behind the user. (With the caveat that we technically are
739 * not using the SwapBuffers itself as a barrier but the first batch
740 * submitted afterwards, which may be immediately prior to the next
741 * SwapBuffers.)
742 */
743 bool need_swap_throttle;
744
745 /** General throttling, not caught by throttling between SwapBuffers */
746 bool need_flush_throttle;
747 /** @} */
748
749 GLuint stats_wm;
750
751 /**
752 * drirc options:
753 * @{
754 */
755 bool no_rast;
756 bool always_flush_batch;
757 bool always_flush_cache;
758 bool disable_throttling;
759 bool precompile;
760 bool dual_color_blend_by_location;
761
762 driOptionCache optionCache;
763 /** @} */
764
765 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
766
767 GLenum reduced_primitive;
768
769 /**
770 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
771 * variable is set, this is the flag indicating to do expensive work that
772 * might lead to a perf_debug() call.
773 */
774 bool perf_debug;
775
776 uint64_t max_gtt_map_object_size;
777
778 int gen;
779 int gt;
780
781 bool is_g4x;
782 bool is_baytrail;
783 bool is_haswell;
784 bool is_cherryview;
785 bool is_broxton;
786
787 bool has_hiz;
788 bool has_separate_stencil;
789 bool must_use_separate_stencil;
790 bool has_llc;
791 bool has_swizzling;
792 bool has_surface_tile_offset;
793 bool has_compr4;
794 bool has_negative_rhw_bug;
795 bool has_pln;
796 bool no_simd8;
797 bool use_rep_send;
798 bool use_resource_streamer;
799
800 /**
801 * Some versions of Gen hardware don't do centroid interpolation correctly
802 * on unlit pixels, causing incorrect values for derivatives near triangle
803 * edges. Enabling this flag causes the fragment shader to use
804 * non-centroid interpolation for unlit pixels, at the expense of two extra
805 * fragment shader instructions.
806 */
807 bool needs_unlit_centroid_workaround;
808
809 struct isl_device isl_dev;
810
811 struct blorp_context blorp;
812
813 GLuint NewGLState;
814 struct {
815 struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
816 } state;
817
818 enum brw_pipeline last_pipeline;
819
820 struct brw_cache cache;
821
822 /** IDs for meta stencil blit shader programs. */
823 struct gl_shader_program *meta_stencil_blit_programs[2];
824
825 /* Whether a meta-operation is in progress. */
826 bool meta_in_progress;
827
828 /* Whether the last depth/stencil packets were both NULL. */
829 bool no_depth_or_stencil;
830
831 /* The last PMA stall bits programmed. */
832 uint32_t pma_stall_bits;
833
834 struct {
835 struct {
836 /** The value of gl_BaseVertex for the current _mesa_prim. */
837 int gl_basevertex;
838
839 /** The value of gl_BaseInstance for the current _mesa_prim. */
840 int gl_baseinstance;
841 } params;
842
843 /**
844 * Buffer and offset used for GL_ARB_shader_draw_parameters
845 * (for now, only gl_BaseVertex).
846 */
847 drm_intel_bo *draw_params_bo;
848 uint32_t draw_params_offset;
849
850 /**
851 * The value of gl_DrawID for the current _mesa_prim. This always comes
852 * in from it's own vertex buffer since it's not part of the indirect
853 * draw parameters.
854 */
855 int gl_drawid;
856 drm_intel_bo *draw_id_bo;
857 uint32_t draw_id_offset;
858 } draw;
859
860 struct {
861 /**
862 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
863 * an indirect call, and num_work_groups_offset is valid. Otherwise,
864 * num_work_groups is set based on glDispatchCompute.
865 */
866 drm_intel_bo *num_work_groups_bo;
867 GLintptr num_work_groups_offset;
868 const GLuint *num_work_groups;
869 } compute;
870
871 struct {
872 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
873 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
874
875 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
876 GLuint nr_enabled;
877 GLuint nr_buffers;
878
879 /* Summary of size and varying of active arrays, so we can check
880 * for changes to this state:
881 */
882 bool index_bounds_valid;
883 unsigned int min_index, max_index;
884
885 /* Offset from start of vertex buffer so we can avoid redefining
886 * the same VB packed over and over again.
887 */
888 unsigned int start_vertex_bias;
889
890 /**
891 * Certain vertex attribute formats aren't natively handled by the
892 * hardware and require special VS code to fix up their values.
893 *
894 * These bitfields indicate which workarounds are needed.
895 */
896 uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
897 } vb;
898
899 struct {
900 /**
901 * Index buffer for this draw_prims call.
902 *
903 * Updates are signaled by BRW_NEW_INDICES.
904 */
905 const struct _mesa_index_buffer *ib;
906
907 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
908 drm_intel_bo *bo;
909 uint32_t size;
910 GLuint type;
911
912 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
913 * avoid re-uploading the IB packet over and over if we're actually
914 * referencing the same index buffer.
915 */
916 unsigned int start_vertex_offset;
917 } ib;
918
919 /* Active vertex program:
920 */
921 const struct gl_program *vertex_program;
922 const struct gl_program *geometry_program;
923 const struct gl_program *tess_ctrl_program;
924 const struct gl_program *tess_eval_program;
925 const struct gl_program *fragment_program;
926 const struct gl_program *compute_program;
927
928 /**
929 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
930 * that we don't have to reemit that state every time we change FBOs.
931 */
932 int num_samples;
933
934 /* BRW_NEW_URB_ALLOCATIONS:
935 */
936 struct {
937 GLuint vsize; /* vertex size plus header in urb registers */
938 GLuint gsize; /* GS output size in urb registers */
939 GLuint hsize; /* Tessellation control output size in urb registers */
940 GLuint dsize; /* Tessellation evaluation output size in urb registers */
941 GLuint csize; /* constant buffer size in urb registers */
942 GLuint sfsize; /* setup data size in urb registers */
943
944 bool constrained;
945
946 GLuint nr_vs_entries;
947 GLuint nr_hs_entries;
948 GLuint nr_ds_entries;
949 GLuint nr_gs_entries;
950 GLuint nr_clip_entries;
951 GLuint nr_sf_entries;
952 GLuint nr_cs_entries;
953
954 GLuint vs_start;
955 GLuint hs_start;
956 GLuint ds_start;
957 GLuint gs_start;
958 GLuint clip_start;
959 GLuint sf_start;
960 GLuint cs_start;
961 /**
962 * URB size in the current configuration. The units this is expressed
963 * in are somewhat inconsistent, see gen_device_info::urb::size.
964 *
965 * FINISHME: Represent the URB size consistently in KB on all platforms.
966 */
967 GLuint size;
968
969 /* True if the most recently sent _3DSTATE_URB message allocated
970 * URB space for the GS.
971 */
972 bool gs_present;
973
974 /* True if the most recently sent _3DSTATE_URB message allocated
975 * URB space for the HS and DS.
976 */
977 bool tess_present;
978 } urb;
979
980
981 /* BRW_NEW_CURBE_OFFSETS:
982 */
983 struct {
984 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
985 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
986 GLuint clip_start;
987 GLuint clip_size;
988 GLuint vs_start;
989 GLuint vs_size;
990 GLuint total_size;
991
992 /**
993 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
994 * for upload to the CURBE.
995 */
996 drm_intel_bo *curbe_bo;
997 /** Offset within curbe_bo of space for current curbe entry */
998 GLuint curbe_offset;
999 } curbe;
1000
1001 /**
1002 * Layout of vertex data exiting the geometry portion of the pipleine.
1003 * This comes from the last enabled shader stage (GS, DS, or VS).
1004 *
1005 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1006 */
1007 struct brw_vue_map vue_map_geom_out;
1008
1009 struct {
1010 struct brw_stage_state base;
1011 } vs;
1012
1013 struct {
1014 struct brw_stage_state base;
1015
1016 /**
1017 * True if the 3DSTATE_HS command most recently emitted to the 3D
1018 * pipeline enabled the HS; false otherwise.
1019 */
1020 bool enabled;
1021 } tcs;
1022
1023 struct {
1024 struct brw_stage_state base;
1025
1026 /**
1027 * True if the 3DSTATE_DS command most recently emitted to the 3D
1028 * pipeline enabled the DS; false otherwise.
1029 */
1030 bool enabled;
1031 } tes;
1032
1033 struct {
1034 struct brw_stage_state base;
1035
1036 /**
1037 * True if the 3DSTATE_GS command most recently emitted to the 3D
1038 * pipeline enabled the GS; false otherwise.
1039 */
1040 bool enabled;
1041 } gs;
1042
1043 struct {
1044 struct brw_ff_gs_prog_data *prog_data;
1045
1046 bool prog_active;
1047 /** Offset in the program cache to the CLIP program pre-gen6 */
1048 uint32_t prog_offset;
1049 uint32_t state_offset;
1050
1051 uint32_t bind_bo_offset;
1052 /**
1053 * Surface offsets for the binding table. We only need surfaces to
1054 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1055 * need in this case.
1056 */
1057 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS];
1058 } ff_gs;
1059
1060 struct {
1061 struct brw_clip_prog_data *prog_data;
1062
1063 /** Offset in the program cache to the CLIP program pre-gen6 */
1064 uint32_t prog_offset;
1065
1066 /* Offset in the batch to the CLIP state on pre-gen6. */
1067 uint32_t state_offset;
1068
1069 /* As of gen6, this is the offset in the batch to the CLIP VP,
1070 * instead of vp_bo.
1071 */
1072 uint32_t vp_offset;
1073
1074 /**
1075 * The number of viewports to use. If gl_ViewportIndex is written,
1076 * we can have up to ctx->Const.MaxViewports viewports. If not,
1077 * the viewport index is always 0, so we can only emit one.
1078 */
1079 uint8_t viewport_count;
1080 } clip;
1081
1082
1083 struct {
1084 struct brw_sf_prog_data *prog_data;
1085
1086 /** Offset in the program cache to the CLIP program pre-gen6 */
1087 uint32_t prog_offset;
1088 uint32_t state_offset;
1089 uint32_t vp_offset;
1090 bool viewport_transform_enable;
1091 } sf;
1092
1093 struct {
1094 struct brw_stage_state base;
1095
1096 GLuint render_surf;
1097
1098 /**
1099 * Buffer object used in place of multisampled null render targets on
1100 * Gen6. See brw_emit_null_surface_state().
1101 */
1102 drm_intel_bo *multisampled_null_render_target_bo;
1103 uint32_t fast_clear_op;
1104
1105 float offset_clamp;
1106 } wm;
1107
1108 struct {
1109 struct brw_stage_state base;
1110 } cs;
1111
1112 /* RS hardware binding table */
1113 struct {
1114 drm_intel_bo *bo;
1115 uint32_t next_offset;
1116 } hw_bt_pool;
1117
1118 struct {
1119 uint32_t state_offset;
1120 uint32_t blend_state_offset;
1121 uint32_t depth_stencil_state_offset;
1122 uint32_t vp_offset;
1123 } cc;
1124
1125 struct {
1126 struct brw_query_object *obj;
1127 bool begin_emitted;
1128 } query;
1129
1130 struct {
1131 enum brw_predicate_state state;
1132 bool supported;
1133 } predicate;
1134
1135 int num_atoms[BRW_NUM_PIPELINES];
1136 const struct brw_tracked_state render_atoms[76];
1137 const struct brw_tracked_state compute_atoms[11];
1138
1139 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1140 struct {
1141 uint32_t offset;
1142 uint32_t size;
1143 enum aub_state_struct_type type;
1144 int index;
1145 } *state_batch_list;
1146 int state_batch_count;
1147
1148 uint32_t render_target_format[MESA_FORMAT_COUNT];
1149 bool format_supported_as_render_target[MESA_FORMAT_COUNT];
1150
1151 /* PrimitiveRestart */
1152 struct {
1153 bool in_progress;
1154 bool enable_cut_index;
1155 } prim_restart;
1156
1157 /** Computed depth/stencil/hiz state from the current attached
1158 * renderbuffers, valid only during the drawing state upload loop after
1159 * brw_workaround_depthstencil_alignment().
1160 */
1161 struct {
1162 struct intel_mipmap_tree *depth_mt;
1163 struct intel_mipmap_tree *stencil_mt;
1164
1165 /* Inter-tile (page-aligned) byte offsets. */
1166 uint32_t depth_offset, hiz_offset, stencil_offset;
1167 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1168 uint32_t tile_x, tile_y;
1169 } depthstencil;
1170
1171 uint32_t num_instances;
1172 int basevertex;
1173 int baseinstance;
1174
1175 struct {
1176 const struct gen_l3_config *config;
1177 } l3;
1178
1179 struct {
1180 drm_intel_bo *bo;
1181 const char **names;
1182 int *ids;
1183 enum shader_time_shader_type *types;
1184 struct shader_times *cumulative;
1185 int num_entries;
1186 int max_entries;
1187 double report_time;
1188 } shader_time;
1189
1190 struct brw_fast_clear_state *fast_clear_state;
1191
1192 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1193 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1194 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1195 * disabled.
1196 * This is needed in case the same underlying buffer is also configured
1197 * to be sampled but with a format that the sampling engine can't treat
1198 * compressed or fast cleared.
1199 */
1200 bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
1201
1202 __DRIcontext *driContext;
1203 struct intel_screen *screen;
1204 };
1205
1206 /* brw_clear.c */
1207 extern void intelInitClearFuncs(struct dd_function_table *functions);
1208
1209 /*======================================================================
1210 * brw_context.c
1211 */
1212 extern const char *const brw_vendor_string;
1213
1214 extern const char *
1215 brw_get_renderer_string(const struct intel_screen *screen);
1216
1217 enum {
1218 DRI_CONF_BO_REUSE_DISABLED,
1219 DRI_CONF_BO_REUSE_ALL
1220 };
1221
1222 void intel_update_renderbuffers(__DRIcontext *context,
1223 __DRIdrawable *drawable);
1224 void intel_prepare_render(struct brw_context *brw);
1225
1226 void intel_resolve_for_dri2_flush(struct brw_context *brw,
1227 __DRIdrawable *drawable);
1228
1229 GLboolean brwCreateContext(gl_api api,
1230 const struct gl_config *mesaVis,
1231 __DRIcontext *driContextPriv,
1232 unsigned major_version,
1233 unsigned minor_version,
1234 uint32_t flags,
1235 bool notify_reset,
1236 unsigned *error,
1237 void *sharedContextPrivate);
1238
1239 /*======================================================================
1240 * brw_misc_state.c
1241 */
1242 void
1243 brw_meta_resolve_color(struct brw_context *brw,
1244 struct intel_mipmap_tree *mt);
1245
1246 /*======================================================================
1247 * brw_misc_state.c
1248 */
1249 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
1250 uint32_t depth_level,
1251 uint32_t depth_layer,
1252 struct intel_mipmap_tree *stencil_mt,
1253 uint32_t *out_tile_mask_x,
1254 uint32_t *out_tile_mask_y);
1255 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1256 GLbitfield clear_mask);
1257
1258 /* brw_object_purgeable.c */
1259 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1260
1261 /*======================================================================
1262 * brw_queryobj.c
1263 */
1264 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1265 void gen4_init_queryobj_functions(struct dd_function_table *functions);
1266 void brw_emit_query_begin(struct brw_context *brw);
1267 void brw_emit_query_end(struct brw_context *brw);
1268 void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q);
1269 bool brw_is_query_pipelined(struct brw_query_object *query);
1270
1271 /** gen6_queryobj.c */
1272 void gen6_init_queryobj_functions(struct dd_function_table *functions);
1273 void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
1274 void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
1275
1276 /** hsw_queryobj.c */
1277 void hsw_init_queryobj_functions(struct dd_function_table *functions);
1278
1279 /** brw_conditional_render.c */
1280 void brw_init_conditional_render_functions(struct dd_function_table *functions);
1281 bool brw_check_conditional_render(struct brw_context *brw);
1282
1283 /** intel_batchbuffer.c */
1284 void brw_load_register_mem(struct brw_context *brw,
1285 uint32_t reg,
1286 drm_intel_bo *bo,
1287 uint32_t read_domains, uint32_t write_domain,
1288 uint32_t offset);
1289 void brw_load_register_mem64(struct brw_context *brw,
1290 uint32_t reg,
1291 drm_intel_bo *bo,
1292 uint32_t read_domains, uint32_t write_domain,
1293 uint32_t offset);
1294 void brw_store_register_mem32(struct brw_context *brw,
1295 drm_intel_bo *bo, uint32_t reg, uint32_t offset);
1296 void brw_store_register_mem64(struct brw_context *brw,
1297 drm_intel_bo *bo, uint32_t reg, uint32_t offset);
1298 void brw_load_register_imm32(struct brw_context *brw,
1299 uint32_t reg, uint32_t imm);
1300 void brw_load_register_imm64(struct brw_context *brw,
1301 uint32_t reg, uint64_t imm);
1302 void brw_load_register_reg(struct brw_context *brw, uint32_t src,
1303 uint32_t dest);
1304 void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
1305 uint32_t dest);
1306 void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
1307 uint32_t offset, uint32_t imm);
1308 void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
1309 uint32_t offset, uint64_t imm);
1310
1311 /*======================================================================
1312 * brw_state_dump.c
1313 */
1314 void brw_debug_batch(struct brw_context *brw);
1315 void brw_annotate_aub(struct brw_context *brw);
1316
1317 /*======================================================================
1318 * intel_tex_validate.c
1319 */
1320 void brw_validate_textures( struct brw_context *brw );
1321
1322
1323 /*======================================================================
1324 * brw_program.c
1325 */
1326 static inline bool
key_debug(struct brw_context * brw,const char * name,int a,int b)1327 key_debug(struct brw_context *brw, const char *name, int a, int b)
1328 {
1329 if (a != b) {
1330 perf_debug(" %s %d->%d\n", name, a, b);
1331 return true;
1332 }
1333 return false;
1334 }
1335
1336 void brwInitFragProgFuncs( struct dd_function_table *functions );
1337
1338 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1339 static inline int
brw_get_scratch_size(int size)1340 brw_get_scratch_size(int size)
1341 {
1342 return MAX2(1024, util_next_power_of_two(size));
1343 }
1344 void brw_get_scratch_bo(struct brw_context *brw,
1345 drm_intel_bo **scratch_bo, int size);
1346 void brw_alloc_stage_scratch(struct brw_context *brw,
1347 struct brw_stage_state *stage_state,
1348 unsigned per_thread_size,
1349 unsigned thread_count);
1350 void brw_init_shader_time(struct brw_context *brw);
1351 int brw_get_shader_time_index(struct brw_context *brw,
1352 struct gl_program *prog,
1353 enum shader_time_shader_type type,
1354 bool is_glsl_sh);
1355 void brw_collect_and_report_shader_time(struct brw_context *brw);
1356 void brw_destroy_shader_time(struct brw_context *brw);
1357
1358 /* brw_urb.c
1359 */
1360 void brw_upload_urb_fence(struct brw_context *brw);
1361
1362 /* brw_curbe.c
1363 */
1364 void brw_upload_cs_urb_state(struct brw_context *brw);
1365
1366 /* brw_fs_reg_allocate.cpp
1367 */
1368 void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
1369
1370 /* brw_vec4_reg_allocate.cpp */
1371 void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
1372
1373 /* brw_disasm.c */
1374 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
1375 struct brw_inst *inst, bool is_compacted);
1376
1377 /* brw_vs.c */
1378 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1379
1380 /* brw_draw_upload.c */
1381 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1382 const struct gl_vertex_array *glarray);
1383
1384 static inline unsigned
brw_get_index_type(GLenum type)1385 brw_get_index_type(GLenum type)
1386 {
1387 assert((type == GL_UNSIGNED_BYTE)
1388 || (type == GL_UNSIGNED_SHORT)
1389 || (type == GL_UNSIGNED_INT));
1390
1391 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1392 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1393 * to map to scale factors of 0, 1, and 2, respectively. These scale
1394 * factors are then left-shfited by 8 to be in the correct position in the
1395 * CMD_INDEX_BUFFER packet.
1396 *
1397 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1398 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1399 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1400 */
1401 return (type - 0x1401) << 7;
1402 }
1403
1404 void brw_prepare_vertices(struct brw_context *brw);
1405
1406 /* brw_wm_surface_state.c */
1407 void brw_init_surface_formats(struct brw_context *brw);
1408 void brw_create_constant_surface(struct brw_context *brw,
1409 drm_intel_bo *bo,
1410 uint32_t offset,
1411 uint32_t size,
1412 uint32_t *out_offset);
1413 void brw_create_buffer_surface(struct brw_context *brw,
1414 drm_intel_bo *bo,
1415 uint32_t offset,
1416 uint32_t size,
1417 uint32_t *out_offset);
1418 void brw_update_buffer_texture_surface(struct gl_context *ctx,
1419 unsigned unit,
1420 uint32_t *surf_offset);
1421 void
1422 brw_update_sol_surface(struct brw_context *brw,
1423 struct gl_buffer_object *buffer_obj,
1424 uint32_t *out_offset, unsigned num_vector_components,
1425 unsigned stride_dwords, unsigned offset_dwords);
1426 void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
1427 struct brw_stage_state *stage_state,
1428 struct brw_stage_prog_data *prog_data);
1429 void brw_upload_abo_surfaces(struct brw_context *brw,
1430 const struct gl_program *prog,
1431 struct brw_stage_state *stage_state,
1432 struct brw_stage_prog_data *prog_data);
1433 void brw_upload_image_surfaces(struct brw_context *brw,
1434 const struct gl_program *prog,
1435 struct brw_stage_state *stage_state,
1436 struct brw_stage_prog_data *prog_data);
1437
1438 /* brw_surface_formats.c */
1439 bool brw_render_target_supported(struct brw_context *brw,
1440 struct gl_renderbuffer *rb);
1441 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
1442
1443 /* intel_buffer_objects.c */
1444 int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
1445 const char *bo_name);
1446 int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
1447 const char *bo_name);
1448
1449 /* intel_extensions.c */
1450 extern void intelInitExtensions(struct gl_context *ctx);
1451
1452 /* intel_state.c */
1453 extern int intel_translate_shadow_compare_func(GLenum func);
1454 extern int intel_translate_compare_func(GLenum func);
1455 extern int intel_translate_stencil_op(GLenum op);
1456 extern int intel_translate_logic_op(GLenum opcode);
1457
1458 /* brw_sync.c */
1459 void brw_init_syncobj_functions(struct dd_function_table *functions);
1460
1461 /* gen6_sol.c */
1462 struct gl_transform_feedback_object *
1463 brw_new_transform_feedback(struct gl_context *ctx, GLuint name);
1464 void
1465 brw_delete_transform_feedback(struct gl_context *ctx,
1466 struct gl_transform_feedback_object *obj);
1467 void
1468 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1469 struct gl_transform_feedback_object *obj);
1470 void
1471 brw_end_transform_feedback(struct gl_context *ctx,
1472 struct gl_transform_feedback_object *obj);
1473 GLsizei
1474 brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
1475 struct gl_transform_feedback_object *obj,
1476 GLuint stream);
1477
1478 /* gen7_sol_state.c */
1479 void
1480 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1481 struct gl_transform_feedback_object *obj);
1482 void
1483 gen7_end_transform_feedback(struct gl_context *ctx,
1484 struct gl_transform_feedback_object *obj);
1485 void
1486 gen7_pause_transform_feedback(struct gl_context *ctx,
1487 struct gl_transform_feedback_object *obj);
1488 void
1489 gen7_resume_transform_feedback(struct gl_context *ctx,
1490 struct gl_transform_feedback_object *obj);
1491
1492 /* hsw_sol.c */
1493 void
1494 hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1495 struct gl_transform_feedback_object *obj);
1496 void
1497 hsw_end_transform_feedback(struct gl_context *ctx,
1498 struct gl_transform_feedback_object *obj);
1499 void
1500 hsw_pause_transform_feedback(struct gl_context *ctx,
1501 struct gl_transform_feedback_object *obj);
1502 void
1503 hsw_resume_transform_feedback(struct gl_context *ctx,
1504 struct gl_transform_feedback_object *obj);
1505
1506 /* brw_blorp_blit.cpp */
1507 GLbitfield
1508 brw_blorp_framebuffer(struct brw_context *brw,
1509 struct gl_framebuffer *readFb,
1510 struct gl_framebuffer *drawFb,
1511 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1512 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1513 GLbitfield mask, GLenum filter);
1514
1515 bool
1516 brw_blorp_copytexsubimage(struct brw_context *brw,
1517 struct gl_renderbuffer *src_rb,
1518 struct gl_texture_image *dst_image,
1519 int slice,
1520 int srcX0, int srcY0,
1521 int dstX0, int dstY0,
1522 int width, int height);
1523
1524 /* gen6_multisample_state.c */
1525 unsigned
1526 gen6_determine_sample_mask(struct brw_context *brw);
1527
1528 void
1529 gen6_emit_3dstate_multisample(struct brw_context *brw,
1530 unsigned num_samples);
1531 void
1532 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
1533 void
1534 gen6_get_sample_position(struct gl_context *ctx,
1535 struct gl_framebuffer *fb,
1536 GLuint index,
1537 GLfloat *result);
1538 void
1539 gen6_set_sample_maps(struct gl_context *ctx);
1540
1541 /* gen8_multisample_state.c */
1542 void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
1543 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
1544
1545 /* gen7_urb.c */
1546 void
1547 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
1548 unsigned hs_size, unsigned ds_size,
1549 unsigned gs_size, unsigned fs_size);
1550
1551 void
1552 gen6_upload_urb(struct brw_context *brw, unsigned vs_size,
1553 bool gs_present, unsigned gs_size);
1554 void
1555 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
1556 bool gs_present, bool tess_present);
1557
1558 /* brw_reset.c */
1559 extern GLenum
1560 brw_get_graphics_reset_status(struct gl_context *ctx);
1561 void
1562 brw_check_for_reset(struct brw_context *brw);
1563
1564 /* brw_compute.c */
1565 extern void
1566 brw_init_compute_functions(struct dd_function_table *functions);
1567
1568 /*======================================================================
1569 * Inline conversion functions. These are better-typed than the
1570 * macros used previously:
1571 */
1572 static inline struct brw_context *
brw_context(struct gl_context * ctx)1573 brw_context( struct gl_context *ctx )
1574 {
1575 return (struct brw_context *)ctx;
1576 }
1577
1578 static inline struct brw_program *
brw_program(struct gl_program * p)1579 brw_program(struct gl_program *p)
1580 {
1581 return (struct brw_program *) p;
1582 }
1583
1584 static inline const struct brw_program *
brw_program_const(const struct gl_program * p)1585 brw_program_const(const struct gl_program *p)
1586 {
1587 return (const struct brw_program *) p;
1588 }
1589
1590 /**
1591 * Pre-gen6, the register file of the EUs was shared between threads,
1592 * and each thread used some subset allocated on a 16-register block
1593 * granularity. The unit states wanted these block counts.
1594 */
1595 static inline int
brw_register_blocks(int reg_count)1596 brw_register_blocks(int reg_count)
1597 {
1598 return ALIGN(reg_count, 16) / 16 - 1;
1599 }
1600
1601 static inline uint32_t
brw_program_reloc(struct brw_context * brw,uint32_t state_offset,uint32_t prog_offset)1602 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1603 uint32_t prog_offset)
1604 {
1605 if (brw->gen >= 5) {
1606 /* Using state base address. */
1607 return prog_offset;
1608 }
1609
1610 drm_intel_bo_emit_reloc(brw->batch.bo,
1611 state_offset,
1612 brw->cache.bo,
1613 prog_offset,
1614 I915_GEM_DOMAIN_INSTRUCTION, 0);
1615
1616 return brw->cache.bo->offset64 + prog_offset;
1617 }
1618
1619 bool brw_do_cubemap_normalize(struct exec_list *instructions);
1620
1621 extern const char * const conditional_modifier[16];
1622 extern const char *const pred_ctrl_align16[16];
1623
1624 static inline bool
brw_depth_writes_enabled(const struct brw_context * brw)1625 brw_depth_writes_enabled(const struct brw_context *brw)
1626 {
1627 const struct gl_context *ctx = &brw->ctx;
1628
1629 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1630 * because it would just overwrite the existing depth value with itself.
1631 *
1632 * These bonus depth writes not only use bandwidth, but they also can
1633 * prevent early depth processing. For example, if the pixel shader
1634 * discards, the hardware must invoke the to determine whether or not
1635 * to do the depth write. If writes are disabled, we may still be able
1636 * to do the depth test before the shader, and skip the shader execution.
1637 *
1638 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1639 * a programming note saying to disable depth writes for EQUAL.
1640 */
1641 return ctx->Depth.Test && ctx->Depth.Mask && ctx->Depth.Func != GL_EQUAL;
1642 }
1643
1644 void
1645 brw_emit_depthbuffer(struct brw_context *brw);
1646
1647 void
1648 brw_emit_depth_stencil_hiz(struct brw_context *brw,
1649 struct intel_mipmap_tree *depth_mt,
1650 uint32_t depth_offset, uint32_t depthbuffer_format,
1651 uint32_t depth_surface_type,
1652 struct intel_mipmap_tree *stencil_mt,
1653 bool hiz, bool separate_stencil,
1654 uint32_t width, uint32_t height,
1655 uint32_t tile_x, uint32_t tile_y);
1656
1657 void
1658 gen6_emit_depth_stencil_hiz(struct brw_context *brw,
1659 struct intel_mipmap_tree *depth_mt,
1660 uint32_t depth_offset, uint32_t depthbuffer_format,
1661 uint32_t depth_surface_type,
1662 struct intel_mipmap_tree *stencil_mt,
1663 bool hiz, bool separate_stencil,
1664 uint32_t width, uint32_t height,
1665 uint32_t tile_x, uint32_t tile_y);
1666
1667 void
1668 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
1669 struct intel_mipmap_tree *depth_mt,
1670 uint32_t depth_offset, uint32_t depthbuffer_format,
1671 uint32_t depth_surface_type,
1672 struct intel_mipmap_tree *stencil_mt,
1673 bool hiz, bool separate_stencil,
1674 uint32_t width, uint32_t height,
1675 uint32_t tile_x, uint32_t tile_y);
1676 void
1677 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
1678 struct intel_mipmap_tree *depth_mt,
1679 uint32_t depth_offset, uint32_t depthbuffer_format,
1680 uint32_t depth_surface_type,
1681 struct intel_mipmap_tree *stencil_mt,
1682 bool hiz, bool separate_stencil,
1683 uint32_t width, uint32_t height,
1684 uint32_t tile_x, uint32_t tile_y);
1685
1686 void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
1687 unsigned int level, unsigned int layer, enum blorp_hiz_op op);
1688
1689 uint32_t get_hw_prim_for_gl_prim(int mode);
1690
1691 void
1692 gen6_upload_push_constants(struct brw_context *brw,
1693 const struct gl_program *prog,
1694 const struct brw_stage_prog_data *prog_data,
1695 struct brw_stage_state *stage_state,
1696 enum aub_state_struct_type type);
1697
1698 bool
1699 gen9_use_linear_1d_layout(const struct brw_context *brw,
1700 const struct intel_mipmap_tree *mt);
1701
1702 /* brw_pipe_control.c */
1703 int brw_init_pipe_control(struct brw_context *brw,
1704 const struct gen_device_info *info);
1705 void brw_fini_pipe_control(struct brw_context *brw);
1706
1707 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
1708 void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
1709 drm_intel_bo *bo, uint32_t offset,
1710 uint32_t imm_lower, uint32_t imm_upper);
1711 void brw_emit_mi_flush(struct brw_context *brw);
1712 void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
1713 void brw_emit_depth_stall_flushes(struct brw_context *brw);
1714 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
1715 void gen7_emit_cs_stall_flush(struct brw_context *brw);
1716
1717 /* brw_queryformat.c */
1718 void brw_query_internal_format(struct gl_context *ctx, GLenum target,
1719 GLenum internalFormat, GLenum pname,
1720 GLint *params);
1721
1722 #ifdef __cplusplus
1723 }
1724 #endif
1725
1726 #endif
1727