1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
28
29 #include "common/gen_l3_config.h"
30
31 /**
32 * This file implements some lightweight memcpy/memset operations on the GPU
33 * using a vertex buffer and streamout.
34 */
35
36 /**
37 * Returns the greatest common divisor of a and b that is a power of two.
38 */
39 static inline uint64_t
gcd_pow2_u64(uint64_t a,uint64_t b)40 gcd_pow2_u64(uint64_t a, uint64_t b)
41 {
42 assert(a > 0 || b > 0);
43
44 unsigned a_log2 = ffsll(a) - 1;
45 unsigned b_log2 = ffsll(b) - 1;
46
47 /* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which
48 * case, the MIN2() will take the other one. If both are 0 then we will
49 * hit the assert above.
50 */
51 return 1 << MIN2(a_log2, b_log2);
52 }
53
54 void
genX(cmd_buffer_gpu_memcpy)55 genX(cmd_buffer_gpu_memcpy)(struct anv_cmd_buffer *cmd_buffer,
56 struct anv_bo *dst, uint32_t dst_offset,
57 struct anv_bo *src, uint32_t src_offset,
58 uint32_t size)
59 {
60 if (size == 0)
61 return;
62
63 assert(dst_offset + size <= dst->size);
64 assert(src_offset + size <= src->size);
65
66 /* The maximum copy block size is 4 32-bit components at a time. */
67 unsigned bs = 16;
68 bs = gcd_pow2_u64(bs, src_offset);
69 bs = gcd_pow2_u64(bs, dst_offset);
70 bs = gcd_pow2_u64(bs, size);
71
72 enum isl_format format;
73 switch (bs) {
74 case 4: format = ISL_FORMAT_R32_UINT; break;
75 case 8: format = ISL_FORMAT_R32G32_UINT; break;
76 case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
77 default:
78 unreachable("Invalid size");
79 }
80
81 if (!cmd_buffer->state.current_l3_config) {
82 const struct gen_l3_config *cfg =
83 gen_get_default_l3_config(&cmd_buffer->device->info);
84 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
85 }
86
87 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
88
89 genX(flush_pipeline_select_3d)(cmd_buffer);
90
91 uint32_t *dw;
92 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
93 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
94 &(struct GENX(VERTEX_BUFFER_STATE)) {
95 .VertexBufferIndex = 32, /* Reserved for this */
96 .AddressModifyEnable = true,
97 .BufferStartingAddress = { src, src_offset },
98 .BufferPitch = bs,
99 #if (GEN_GEN >= 8)
100 .MemoryObjectControlState = GENX(MOCS),
101 .BufferSize = size,
102 #else
103 .VertexBufferMemoryObjectControlState = GENX(MOCS),
104 .EndAddress = { src, src_offset + size - 1 },
105 #endif
106 });
107
108 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
109 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
110 &(struct GENX(VERTEX_ELEMENT_STATE)) {
111 .VertexBufferIndex = 32,
112 .Valid = true,
113 .SourceElementFormat = format,
114 .SourceElementOffset = 0,
115 .Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
116 .Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
117 .Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
118 .Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
119 });
120
121 #if GEN_GEN >= 8
122 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
123 #endif
124
125 /* Disable all shader stages */
126 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
127 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
128 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te);
129 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
130 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs);
131 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs);
132
133 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SBE), sbe) {
134 sbe.VertexURBEntryReadOffset = 1;
135 sbe.NumberofSFOutputAttributes = 1;
136 sbe.VertexURBEntryReadLength = 1;
137 #if GEN_GEN >= 8
138 sbe.ForceVertexURBEntryReadLength = true;
139 sbe.ForceVertexURBEntryReadOffset = true;
140 #endif
141
142 #if GEN_GEN >= 9
143 for (unsigned i = 0; i < 32; i++)
144 sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
145 #endif
146 }
147
148 /* Emit URB setup. We tell it that the VS is active because we want it to
149 * allocate space for the VS. Even though one isn't run, we need VUEs to
150 * store the data that VF is going to pass to SOL.
151 */
152 const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
153
154 genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch,
155 cmd_buffer->state.current_l3_config,
156 VK_SHADER_STAGE_VERTEX_BIT, entry_size);
157
158 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
159 sob.SOBufferIndex = 0;
160 sob.SOBufferObjectControlState = GENX(MOCS);
161 sob.SurfaceBaseAddress = (struct anv_address) { dst, dst_offset };
162
163 #if GEN_GEN >= 8
164 sob.SOBufferEnable = true;
165 sob.SurfaceSize = size - 1;
166 #else
167 sob.SurfacePitch = bs;
168 sob.SurfaceEndAddress = sob.SurfaceBaseAddress;
169 sob.SurfaceEndAddress.offset += size;
170 #endif
171
172 #if GEN_GEN >= 8
173 /* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with
174 * the end position of the stream. We need to reset this value to 0 at
175 * the beginning of the run or else SOL will start at the offset from
176 * the previous draw.
177 */
178 sob.StreamOffsetWriteEnable = true;
179 sob.StreamOffset = 0;
180 #endif
181 }
182
183 #if GEN_GEN <= 7
184 /* The hardware can do this for us on BDW+ (see above) */
185 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
186 load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);
187 load.DataDWord = 0;
188 }
189 #endif
190
191 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),
192 .StreamtoBufferSelects0 = (1 << 0),
193 .NumEntries0 = 1);
194 GENX(SO_DECL_ENTRY_pack)(&cmd_buffer->batch, dw + 3,
195 &(struct GENX(SO_DECL_ENTRY)) {
196 .Stream0Decl = {
197 .OutputBufferSlot = 0,
198 .RegisterIndex = 0,
199 .ComponentMask = (1 << (bs / 4)) - 1,
200 },
201 });
202
203 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT), so) {
204 so.SOFunctionEnable = true;
205 so.RenderingDisable = true;
206 so.Stream0VertexReadOffset = 0;
207 so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64);
208 #if GEN_GEN >= 8
209 so.Buffer0SurfacePitch = bs;
210 #else
211 so.SOBufferEnable0 = true;
212 #endif
213 }
214
215 #if GEN_GEN >= 8
216 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
217 topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
218 }
219 #endif
220
221 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
222 prim.VertexAccessType = SEQUENTIAL;
223 prim.PrimitiveTopologyType = _3DPRIM_POINTLIST;
224 prim.VertexCountPerInstance = size / bs;
225 prim.StartVertexLocation = 0;
226 prim.InstanceCount = 1;
227 prim.StartInstanceLocation = 0;
228 prim.BaseVertexLocation = 0;
229 }
230
231 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
232 }
233