1/* 2 * dts file for Hisilicon Hi6220 SoC 3 * 4 * Copyright (C) 2015, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi6220-clock.h> 9#include <dt-bindings/pinctrl/hisi.h> 10#include <dt-bindings/thermal/thermal.h> 11#include <dt-bindings/reset/hisi,hi6220-resets.h> 12 13/ { 14 compatible = "hisilicon,hi6220"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 psci { 20 compatible = "arm,psci-0.2"; 21 method = "smc"; 22 }; 23 24 cpus { 25 #address-cells = <2>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 core1 { 34 cpu = <&cpu1>; 35 }; 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 core3 { 40 cpu = <&cpu3>; 41 }; 42 }; 43 cluster1 { 44 core0 { 45 cpu = <&cpu4>; 46 }; 47 core1 { 48 cpu = <&cpu5>; 49 }; 50 core2 { 51 cpu = <&cpu6>; 52 }; 53 core3 { 54 cpu = <&cpu7>; 55 }; 56 }; 57 }; 58 59 idle-states { 60 entry-method = "psci"; 61 62 CPU_SLEEP: cpu-sleep { 63 compatible = "arm,idle-state"; 64 local-timer-stop; 65 arm,psci-suspend-param = <0x0010000>; 66 entry-latency-us = <700>; 67 exit-latency-us = <250>; 68 min-residency-us = <1000>; 69 }; 70 71 CLUSTER_SLEEP: cluster-sleep { 72 compatible = "arm,idle-state"; 73 local-timer-stop; 74 arm,psci-suspend-param = <0x1010000>; 75 entry-latency-us = <1000>; 76 exit-latency-us = <700>; 77 min-residency-us = <2700>; 78 wakeup-latency-us = <1500>; 79 }; 80 }; 81 82 cpu0: cpu@0 { 83 compatible = "arm,cortex-a53", "arm,armv8"; 84 device_type = "cpu"; 85 reg = <0x0 0x0>; 86 enable-method = "psci"; 87 next-level-cache = <&CLUSTER0_L2>; 88 clocks = <&stub_clock 0>; 89 operating-points-v2 = <&cpu_opp_table>; 90 cooling-min-level = <4>; 91 cooling-max-level = <0>; 92 #cooling-cells = <2>; /* min followed by max */ 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 94 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 95 dynamic-power-coefficient = <311>; 96 }; 97 98 cpu1: cpu@1 { 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <0x0 0x1>; 102 enable-method = "psci"; 103 next-level-cache = <&CLUSTER0_L2>; 104 operating-points-v2 = <&cpu_opp_table>; 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 106 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 107 }; 108 109 cpu2: cpu@2 { 110 compatible = "arm,cortex-a53", "arm,armv8"; 111 device_type = "cpu"; 112 reg = <0x0 0x2>; 113 enable-method = "psci"; 114 next-level-cache = <&CLUSTER0_L2>; 115 operating-points-v2 = <&cpu_opp_table>; 116 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 117 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 118 }; 119 120 cpu3: cpu@3 { 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 device_type = "cpu"; 123 reg = <0x0 0x3>; 124 enable-method = "psci"; 125 next-level-cache = <&CLUSTER0_L2>; 126 operating-points-v2 = <&cpu_opp_table>; 127 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 128 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 129 }; 130 131 cpu4: cpu@100 { 132 compatible = "arm,cortex-a53", "arm,armv8"; 133 device_type = "cpu"; 134 reg = <0x0 0x100>; 135 enable-method = "psci"; 136 next-level-cache = <&CLUSTER1_L2>; 137 operating-points-v2 = <&cpu_opp_table>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 140 }; 141 142 cpu5: cpu@101 { 143 compatible = "arm,cortex-a53", "arm,armv8"; 144 device_type = "cpu"; 145 reg = <0x0 0x101>; 146 enable-method = "psci"; 147 next-level-cache = <&CLUSTER1_L2>; 148 operating-points-v2 = <&cpu_opp_table>; 149 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 150 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 151 }; 152 153 cpu6: cpu@102 { 154 compatible = "arm,cortex-a53", "arm,armv8"; 155 device_type = "cpu"; 156 reg = <0x0 0x102>; 157 enable-method = "psci"; 158 next-level-cache = <&CLUSTER1_L2>; 159 operating-points-v2 = <&cpu_opp_table>; 160 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 161 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 162 }; 163 164 cpu7: cpu@103 { 165 compatible = "arm,cortex-a53", "arm,armv8"; 166 device_type = "cpu"; 167 reg = <0x0 0x103>; 168 enable-method = "psci"; 169 next-level-cache = <&CLUSTER1_L2>; 170 operating-points-v2 = <&cpu_opp_table>; 171 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 172 sched-energy-costs = <&CPU_COST &CLUSTER_COST>; 173 }; 174 175 CLUSTER0_L2: l2-cache0 { 176 compatible = "cache"; 177 }; 178 179 CLUSTER1_L2: l2-cache1 { 180 compatible = "cache"; 181 }; 182 183 /include/ "hi6220-sched-energy.dtsi" 184 }; 185 186 cpu_opp_table: cpu_opp_table { 187 compatible = "operating-points-v2"; 188 opp-shared; 189 190 opp00 { 191 opp-hz = /bits/ 64 <208000000>; 192 opp-microvolt = <1040000>; 193 clock-latency-ns = <500000>; 194 }; 195 opp01 { 196 opp-hz = /bits/ 64 <432000000>; 197 opp-microvolt = <1040000>; 198 clock-latency-ns = <500000>; 199 }; 200 opp02 { 201 opp-hz = /bits/ 64 <729000000>; 202 opp-microvolt = <1090000>; 203 clock-latency-ns = <500000>; 204 }; 205 opp03 { 206 opp-hz = /bits/ 64 <960000000>; 207 opp-microvolt = <1180000>; 208 clock-latency-ns = <500000>; 209 }; 210 opp04 { 211 opp-hz = /bits/ 64 <1200000000>; 212 opp-microvolt = <1330000>; 213 clock-latency-ns = <500000>; 214 }; 215 }; 216 217 gic: interrupt-controller@f6801000 { 218 compatible = "arm,gic-400"; 219 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 220 <0x0 0xf6802000 0 0x2000>, /* GICC */ 221 <0x0 0xf6804000 0 0x2000>, /* GICH */ 222 <0x0 0xf6806000 0 0x2000>; /* GICV */ 223 #address-cells = <0>; 224 #interrupt-cells = <3>; 225 interrupt-controller; 226 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 227 }; 228 229 timer { 230 compatible = "arm,armv8-timer"; 231 interrupt-parent = <&gic>; 232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 236 }; 237 238 soc { 239 compatible = "simple-bus"; 240 #address-cells = <2>; 241 #size-cells = <2>; 242 #sound-dai-cells = <0>; 243 interrupt-parent = <&gic>; 244 ranges; 245 246 sram: sram@fff80000 { 247 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 248 reg = <0x0 0xfff80000 0x0 0x12000>; 249 }; 250 251 ao_ctrl: ao_ctrl@f7800000 { 252 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 253 reg = <0x0 0xf7800000 0x0 0x2000>; 254 #clock-cells = <1>; 255 }; 256 257 sys_ctrl: sys_ctrl@f7030000 { 258 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 259 reg = <0x0 0xf7030000 0x0 0x2000>; 260 #clock-cells = <1>; 261 #reset-cells = <1>; 262 }; 263 264 media_ctrl: media_ctrl@f4410000 { 265 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 266 reg = <0x0 0xf4410000 0x0 0x1000>; 267 #clock-cells = <1>; 268 #reset-cells = <1>; 269 }; 270 271 pm_ctrl: pm_ctrl@f7032000 { 272 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 273 reg = <0x0 0xf7032000 0x0 0x1000>; 274 #clock-cells = <1>; 275 }; 276 277 stub_clock: stub_clock { 278 compatible = "hisilicon,hi6220-stub-clk"; 279 hisilicon,hi6220-clk-sram = <&sram>; 280 #clock-cells = <1>; 281 mbox-names = "mbox-tx"; 282 mboxes = <&mailbox 1 0 11>; 283 }; 284 285 medianoc_ade: medianoc_ade@f4520000 { 286 compatible = "syscon"; 287 reg = <0x0 0xf4520000 0x0 0x4000>; 288 }; 289 290 uart0: uart@f8015000 { /* console */ 291 compatible = "arm,pl011", "arm,primecell"; 292 reg = <0x0 0xf8015000 0x0 0x1000>; 293 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 295 <&ao_ctrl HI6220_UART0_PCLK>; 296 clock-names = "uartclk", "apb_pclk"; 297 }; 298 299 uart1: uart@f7111000 { 300 compatible = "arm,pl011", "arm,primecell"; 301 reg = <0x0 0xf7111000 0x0 0x1000>; 302 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 304 <&sys_ctrl HI6220_UART1_PCLK>; 305 clock-names = "uartclk", "apb_pclk"; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 308 status = "disabled"; 309 }; 310 311 uart2: uart@f7112000 { 312 compatible = "arm,pl011", "arm,primecell"; 313 reg = <0x0 0xf7112000 0x0 0x1000>; 314 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 316 <&sys_ctrl HI6220_UART2_PCLK>; 317 clock-names = "uartclk", "apb_pclk"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 320 status = "disabled"; 321 }; 322 323 uart3: uart@f7113000 { 324 compatible = "arm,pl011", "arm,primecell"; 325 reg = <0x0 0xf7113000 0x0 0x1000>; 326 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 328 <&sys_ctrl HI6220_UART3_PCLK>; 329 clock-names = "uartclk", "apb_pclk"; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 332 status = "disabled"; 333 }; 334 335 uart4: uart@f7114000 { 336 compatible = "arm,pl011", "arm,primecell"; 337 reg = <0x0 0xf7114000 0x0 0x1000>; 338 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 340 <&sys_ctrl HI6220_UART4_PCLK>; 341 clock-names = "uartclk", "apb_pclk"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 344 status = "disabled"; 345 }; 346 347 dma0: dma@f7370000 { 348 compatible = "hisilicon,k3-dma-1.0"; 349 reg = <0x0 0xf7370000 0x0 0x1000>; 350 #dma-cells = <1>; 351 dma-channels = <15>; 352 dma-requests = <32>; 353 interrupts = <0 84 4>; 354 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 355 dma-no-cci; 356 dma-type = "hi6220_dma"; 357 status = "ok"; 358 }; 359 360 dual_timer0: dual_timer@f8008000 { 361 compatible = "arm,sp804", "arm,primecell"; 362 reg = <0x0 0xf8008000 0x0 0x1000>; 363 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&ao_ctrl 27>; 366 clock-names = "apb_pclk"; 367 }; 368 369 rtc0: rtc@170000 { 370 compatible = "arm,pl031", "arm,primecell"; 371 reg = <0x0 0xf8003000 0x0 0x1000>; 372 interrupts = <0 12 4>; 373 clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 374 clock-names = "apb_pclk"; 375 }; 376 377 pmx0: pinmux@f7010000 { 378 compatible = "pinctrl-single"; 379 reg = <0x0 0xf7010000 0x0 0x27c>; 380 #address-cells = <1>; 381 #size-cells = <1>; 382 #gpio-range-cells = <3>; 383 pinctrl-single,register-width = <32>; 384 pinctrl-single,function-mask = <7>; 385 pinctrl-single,gpio-range = < 386 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 387 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 388 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 389 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 390 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 391 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 392 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 393 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 394 &range 0 1 MUX_M1 /* gpio 10: [0] */ 395 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 396 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 397 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 398 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 399 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 400 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 401 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 402 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 403 &range 122 1 MUX_M1 /* gpio 15: [6] */ 404 &range 126 1 MUX_M1 /* gpio 15: [7] */ 405 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 406 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 407 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 408 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 409 >; 410 range: gpio-range { 411 #pinctrl-single,gpio-range-cells = <3>; 412 }; 413 }; 414 415 pmx1: pinmux@f7010800 { 416 compatible = "pinconf-single"; 417 reg = <0x0 0xf7010800 0x0 0x28c>; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 pinctrl-single,register-width = <32>; 421 }; 422 423 pmx2: pinmux@f8001800 { 424 compatible = "pinconf-single"; 425 reg = <0x0 0xf8001800 0x0 0x78>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 pinctrl-single,register-width = <32>; 429 }; 430 431 gpio0: gpio@f8011000 { 432 compatible = "arm,pl061", "arm,primecell"; 433 reg = <0x0 0xf8011000 0x0 0x1000>; 434 interrupts = <0 52 0x4>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 clocks = <&ao_ctrl 2>; 440 clock-names = "apb_pclk"; 441 status = "ok"; 442 }; 443 444 gpio1: gpio@f8012000 { 445 compatible = "arm,pl061", "arm,primecell"; 446 reg = <0x0 0xf8012000 0x0 0x1000>; 447 interrupts = <0 53 0x4>; 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 clocks = <&ao_ctrl 2>; 453 clock-names = "apb_pclk"; 454 status = "ok"; 455 }; 456 457 gpio2: gpio@f8013000 { 458 compatible = "arm,pl061", "arm,primecell"; 459 reg = <0x0 0xf8013000 0x0 0x1000>; 460 interrupts = <0 54 0x4>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 clocks = <&ao_ctrl 2>; 466 clock-names = "apb_pclk"; 467 status = "ok"; 468 }; 469 470 gpio3: gpio@f8014000 { 471 compatible = "arm,pl061", "arm,primecell"; 472 reg = <0x0 0xf8014000 0x0 0x1000>; 473 interrupts = <0 55 0x4>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 gpio-ranges = <&pmx0 0 80 8>; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 clocks = <&ao_ctrl 2>; 480 clock-names = "apb_pclk"; 481 status = "ok"; 482 }; 483 484 gpio4: gpio@f7020000 { 485 compatible = "arm,pl061", "arm,primecell"; 486 reg = <0x0 0xf7020000 0x0 0x1000>; 487 interrupts = <0 56 0x4>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 gpio-ranges = <&pmx0 0 88 8>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 clocks = <&ao_ctrl 2>; 494 clock-names = "apb_pclk"; 495 status = "ok"; 496 }; 497 498 gpio5: gpio@f7021000 { 499 compatible = "arm,pl061", "arm,primecell"; 500 reg = <0x0 0xf7021000 0x0 0x1000>; 501 interrupts = <0 57 0x4>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 gpio-ranges = <&pmx0 0 96 8>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 clocks = <&ao_ctrl 2>; 508 clock-names = "apb_pclk"; 509 status = "ok"; 510 }; 511 512 gpio6: gpio@f7022000 { 513 compatible = "arm,pl061", "arm,primecell"; 514 reg = <0x0 0xf7022000 0x0 0x1000>; 515 interrupts = <0 58 0x4>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 gpio-ranges = <&pmx0 0 104 8>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 clocks = <&ao_ctrl 2>; 522 clock-names = "apb_pclk"; 523 status = "ok"; 524 }; 525 526 gpio7: gpio@f7023000 { 527 compatible = "arm,pl061", "arm,primecell"; 528 reg = <0x0 0xf7023000 0x0 0x1000>; 529 interrupts = <0 59 0x4>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 gpio-ranges = <&pmx0 0 112 8>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 clocks = <&ao_ctrl 2>; 536 clock-names = "apb_pclk"; 537 status = "ok"; 538 }; 539 540 gpio8: gpio@f7024000 { 541 compatible = "arm,pl061", "arm,primecell"; 542 reg = <0x0 0xf7024000 0x0 0x1000>; 543 interrupts = <0 60 0x4>; 544 gpio-controller; 545 #gpio-cells = <2>; 546 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 clocks = <&ao_ctrl 2>; 550 clock-names = "apb_pclk"; 551 status = "ok"; 552 }; 553 554 gpio9: gpio@f7025000 { 555 compatible = "arm,pl061", "arm,primecell"; 556 reg = <0x0 0xf7025000 0x0 0x1000>; 557 interrupts = <0 61 0x4>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 gpio-ranges = <&pmx0 0 8 8>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 clocks = <&ao_ctrl 2>; 564 clock-names = "apb_pclk"; 565 status = "ok"; 566 }; 567 568 gpio10: gpio@f7026000 { 569 compatible = "arm,pl061", "arm,primecell"; 570 reg = <0x0 0xf7026000 0x0 0x1000>; 571 interrupts = <0 62 0x4>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 clocks = <&ao_ctrl 2>; 578 clock-names = "apb_pclk"; 579 status = "ok"; 580 }; 581 582 gpio11: gpio@f7027000 { 583 compatible = "arm,pl061", "arm,primecell"; 584 reg = <0x0 0xf7027000 0x0 0x1000>; 585 interrupts = <0 63 0x4>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 clocks = <&ao_ctrl 2>; 592 clock-names = "apb_pclk"; 593 status = "ok"; 594 }; 595 596 gpio12: gpio@f7028000 { 597 compatible = "arm,pl061", "arm,primecell"; 598 reg = <0x0 0xf7028000 0x0 0x1000>; 599 interrupts = <0 64 0x4>; 600 gpio-controller; 601 #gpio-cells = <2>; 602 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 clocks = <&ao_ctrl 2>; 606 clock-names = "apb_pclk"; 607 status = "ok"; 608 }; 609 610 gpio13: gpio@f7029000 { 611 compatible = "arm,pl061", "arm,primecell"; 612 reg = <0x0 0xf7029000 0x0 0x1000>; 613 interrupts = <0 65 0x4>; 614 gpio-controller; 615 #gpio-cells = <2>; 616 gpio-ranges = <&pmx0 0 48 8>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 clocks = <&ao_ctrl 2>; 620 clock-names = "apb_pclk"; 621 status = "ok"; 622 }; 623 624 gpio14: gpio@f702a000 { 625 compatible = "arm,pl061", "arm,primecell"; 626 reg = <0x0 0xf702a000 0x0 0x1000>; 627 interrupts = <0 66 0x4>; 628 gpio-controller; 629 #gpio-cells = <2>; 630 gpio-ranges = <&pmx0 0 56 8>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 clocks = <&ao_ctrl 2>; 634 clock-names = "apb_pclk"; 635 status = "ok"; 636 }; 637 638 gpio15: gpio@f702b000 { 639 compatible = "arm,pl061", "arm,primecell"; 640 reg = <0x0 0xf702b000 0x0 0x1000>; 641 interrupts = <0 67 0x4>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 gpio-ranges = < 645 &pmx0 0 74 6 646 &pmx0 6 122 1 647 &pmx0 7 126 1 648 >; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 clocks = <&ao_ctrl 2>; 652 clock-names = "apb_pclk"; 653 status = "ok"; 654 }; 655 656 gpio16: gpio@f702c000 { 657 compatible = "arm,pl061", "arm,primecell"; 658 reg = <0x0 0xf702c000 0x0 0x1000>; 659 interrupts = <0 68 0x4>; 660 gpio-controller; 661 #gpio-cells = <2>; 662 gpio-ranges = <&pmx0 0 127 8>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 clocks = <&ao_ctrl 2>; 666 clock-names = "apb_pclk"; 667 status = "ok"; 668 }; 669 670 gpio17: gpio@f702d000 { 671 compatible = "arm,pl061", "arm,primecell"; 672 reg = <0x0 0xf702d000 0x0 0x1000>; 673 interrupts = <0 69 0x4>; 674 gpio-controller; 675 #gpio-cells = <2>; 676 gpio-ranges = <&pmx0 0 135 8>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 clocks = <&ao_ctrl 2>; 680 clock-names = "apb_pclk"; 681 status = "ok"; 682 }; 683 684 gpio18: gpio@f702e000 { 685 compatible = "arm,pl061", "arm,primecell"; 686 reg = <0x0 0xf702e000 0x0 0x1000>; 687 interrupts = <0 70 0x4>; 688 gpio-controller; 689 #gpio-cells = <2>; 690 gpio-ranges = <&pmx0 0 143 8>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 clocks = <&ao_ctrl 2>; 694 clock-names = "apb_pclk"; 695 status = "ok"; 696 }; 697 698 gpio19: gpio@f702f000 { 699 compatible = "arm,pl061", "arm,primecell"; 700 reg = <0x0 0xf702f000 0x0 0x1000>; 701 interrupts = <0 71 0x4>; 702 gpio-controller; 703 #gpio-cells = <2>; 704 gpio-ranges = <&pmx0 0 151 8>; 705 interrupt-controller; 706 #interrupt-cells = <2>; 707 clocks = <&ao_ctrl 2>; 708 clock-names = "apb_pclk"; 709 status = "ok"; 710 }; 711 712 spi0: spi@f7106000 { 713 compatible = "arm,pl022", "arm,primecell"; 714 reg = <0x0 0xf7106000 0x0 0x1000>; 715 interrupts = <0 50 4>; 716 bus-id = <0>; 717 enable-dma = <0>; 718 clocks = <&sys_ctrl HI6220_SPI_CLK>; 719 clock-names = "apb_pclk"; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 722 num-cs = <1>; 723 cs-gpios = <&gpio6 2 0>; 724 status = "disabled"; 725 }; 726 727 i2c0: i2c@f7100000 { 728 compatible = "snps,designware-i2c"; 729 reg = <0x0 0xf7100000 0x0 0x1000>; 730 interrupts = <0 44 4>; 731 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 732 i2c-sda-hold-time-ns = <300>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 735 status = "disabled"; 736 }; 737 738 i2c1: i2c@f7101000 { 739 compatible = "snps,designware-i2c"; 740 reg = <0x0 0xf7101000 0x0 0x1000>; 741 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 742 interrupts = <0 45 4>; 743 i2c-sda-hold-time-ns = <300>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 746 status = "disabled"; 747 }; 748 749 i2c2: i2c@f7102000 { 750 compatible = "snps,designware-i2c"; 751 reg = <0x0 0xf7102000 0x0 0x1000>; 752 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 753 interrupts = <0 46 4>; 754 i2c-sda-hold-time-ns = <300>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 757 status = "disabled"; 758 }; 759 760 fixed_5v_hub: regulator@0 { 761 compatible = "regulator-fixed"; 762 regulator-name = "fixed_5v_hub"; 763 regulator-min-microvolt = <5000000>; 764 regulator-max-microvolt = <5000000>; 765 regulator-boot-on; 766 gpio = <&gpio0 7 0>; 767 regulator-always-on; 768 }; 769 770 usb_phy: usbphy { 771 compatible = "hisilicon,hi6220-usb-phy"; 772 #phy-cells = <0>; 773 phy-supply = <&fixed_5v_hub>; 774 hisilicon,peripheral-syscon = <&sys_ctrl>; 775 }; 776 777 usb: usb@f72c0000 { 778 compatible = "hisilicon,hi6220-usb"; 779 reg = <0x0 0xf72c0000 0x0 0x40000>; 780 phys = <&usb_phy>; 781 phy-names = "usb2-phy"; 782 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 783 clock-names = "otg"; 784 dr_mode = "otg"; 785 g-use-dma; 786 g-rx-fifo-size = <512>; 787 g-np-tx-fifo-size = <128>; 788 g-tx-fifo-size = <128 128 128 128 128 128>; 789 interrupts = <0 77 0x4>; 790 }; 791 792 mailbox: mailbox@f7510000 { 793 compatible = "hisilicon,hi6220-mbox"; 794 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 795 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 796 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 797 #mbox-cells = <3>; 798 }; 799 800 dwmmc_0: dwmmc0@f723d000 { 801 compatible = "hisilicon,hi6220-dw-mshc"; 802 num-slots = <0x1>; 803 cap-mmc-highspeed; 804 non-removable; 805 reg = <0x0 0xf723d000 0x0 0x1000>; 806 interrupts = <0x0 0x48 0x4>; 807 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 808 clock-names = "ciu", "biu"; 809 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 810 bus-width = <0x8>; 811 vmmc-supply = <&ldo19>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 814 &emmc_cfg_func &emmc_rst_cfg_func>; 815 }; 816 817 dwmmc_1: dwmmc1@f723e000 { 818 compatible = "hisilicon,hi6220-dw-mshc"; 819 num-slots = <0x1>; 820 card-detect-delay = <200>; 821 hisilicon,peripheral-syscon = <&ao_ctrl>; 822 cap-sd-highspeed; 823 sd-uhs-sdr12; 824 sd-uhs-sdr25; 825 sd-uhs-sdr50; 826 reg = <0x0 0xf723e000 0x0 0x1000>; 827 interrupts = <0x0 0x49 0x4>; 828 #address-cells = <0x1>; 829 #size-cells = <0x0>; 830 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 831 clock-names = "ciu", "biu"; 832 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 833 vqmmc-supply = <&ldo7>; 834 vmmc-supply = <&ldo10>; 835 bus-width = <0x4>; 836 disable-wp; 837 cd-gpios = <&gpio1 0 1>; 838 pinctrl-names = "default", "idle"; 839 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 840 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 841 }; 842 843 dwmmc_2: dwmmc2@f723f000 { 844 compatible = "hisilicon,hi6220-dw-mshc"; 845 status = "okay"; 846 num-slots = <0x1>; 847 reg = <0x0 0xf723f000 0x0 0x1000>; 848 interrupts = <0x0 0x4a 0x4>; 849 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 850 clock-names = "ciu", "biu"; 851 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 852 bus-width = <0x4>; 853 broken-cd; 854 pinctrl-names = "default", "idle"; 855 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 856 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 857 }; 858 859 tsensor: tsensor@0,f7030700 { 860 compatible = "hisilicon,tsensor"; 861 reg = <0x0 0xf7030700 0x0 0x1000>; 862 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&sys_ctrl 22>; 864 clock-names = "thermal_clk"; 865 #thermal-sensor-cells = <1>; 866 }; 867 868 thermal-zones { 869 870 cls0: cls0 { 871 polling-delay = <1000>; 872 polling-delay-passive = <100>; 873 sustainable-power = <3326>; 874 875 /* sensor ID */ 876 thermal-sensors = <&tsensor 2>; 877 878 trips { 879 threshold: trip-point@0 { 880 temperature = <65000>; 881 hysteresis = <1000>; 882 type = "passive"; 883 }; 884 885 target: trip-point@1 { 886 temperature = <75000>; 887 hysteresis = <1000>; 888 type = "passive"; 889 }; 890 }; 891 892 cooling-maps { 893 map0 { 894 trip = <&target>; 895 contribution = <1024>; 896 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 897 }; 898 }; 899 }; 900 }; 901 902 mtcmos { 903 compatible = "hisilicon,hi6220-mtcmos-driver"; 904 hisilicon,mtcmos-steady-us = <10>; 905 hisilicon,mtcmos-sc-on-base = <0xf7800000>; 906 hisilicon,mtcmos-acpu-on-base = <0xf65a0000>; 907 908 g3d_vdd: regulator@a1{ 909 regulator-name = "G3D_PD_VDD"; 910 regulator-compatible = "mtcmos1"; 911 hisilicon,ctrl-regs = <0x830 0x834 0x83c>; 912 hisilicon,ctrl-data = <1 0x1>; 913 }; 914 915 soc_med: regulator@a2{ 916 regulator-name = "SOC_MED"; 917 regulator-compatible = "mtcmos2"; 918 hisilicon,ctrl-regs = <0x830 0x834 0x83c>; 919 hisilicon,ctrl-data = <2 0x1>; 920 }; 921 }; 922 923 ade: ade@f4100000 { 924 compatible = "hisilicon,hi6220-ade"; 925 reg = <0x0 0xf4100000 0x0 0x7800>; 926 reg-names = "ade_base"; 927 hisilicon,noc-syscon = <&medianoc_ade>; 928 resets = <&media_ctrl MEDIA_ADE>; 929 interrupts = <0 115 4>; /* ldi interrupt */ 930 931 clocks = <&media_ctrl HI6220_ADE_CORE>, 932 <&media_ctrl HI6220_CODEC_JPEG>, 933 <&media_ctrl HI6220_ADE_PIX_SRC>; 934 /*clock name*/ 935 clock-names = "clk_ade_core", 936 "clk_codec_jpeg", 937 "clk_ade_pix"; 938 939 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 940 <&media_ctrl HI6220_CODEC_JPEG>; 941 assigned-clock-rates = <360000000>, <288000000>; 942 status = "disabled"; 943 944 port { 945 ade_out: endpoint { 946 remote-endpoint = <&dsi_in>; 947 }; 948 }; 949 }; 950 951 dsi: dsi@f4107800 { 952 compatible = "hisilicon,hi6220-dsi"; 953 reg = <0x0 0xf4107800 0x0 0x100>; 954 clocks = <&media_ctrl HI6220_DSI_PCLK>; 955 clock-names = "pclk"; 956 status = "disabled"; 957 958 ports { 959 #address-cells = <1>; 960 #size-cells = <0>; 961 962 /* 0 for input port */ 963 port@0 { 964 reg = <0>; 965 dsi_in: endpoint { 966 remote-endpoint = <&ade_out>; 967 }; 968 }; 969 }; 970 }; 971 972 mali:mali@f4080000 { 973 compatible = "arm,mali-450", "arm,mali-utgard"; 974 reg = <0x0 0x3f100000 0x0 0x00708000>; 975 clocks = <&media_ctrl HI6220_G3D_CLK>, 976 <&media_ctrl HI6220_G3D_PCLK>; 977 clock-names = "clk_g3d", "pclk_g3d"; 978 G3D_PD_VDD-supply = <&g3d_vdd>; 979 mali_def_freq = <500>; 980 pclk_freq = <144>; 981 dfs_steps = <2>; 982 dfs_lockprf = <1>; 983 dfs_limit_max_prf = <1>; 984 dfs_profile_num = <2>; 985 dfs_profiles = <250 3 0>, <500 1 0>; 986 mali_type = <2>; 987 988 interrupt-parent = <&gic>; 989 interrupts = <1 126 4>, /*gp*/ 990 <1 126 4>, /*gp mmu*/ 991 <1 126 4>, /*pp bc*/ 992 <1 126 4>, /*pmu*/ 993 <1 126 4>, /*pp0*/ 994 <1 126 4>, 995 <1 126 4>, /*pp1*/ 996 <1 126 4>, 997 <1 126 4>, /*pp2*/ 998 <1 126 4>, 999 <1 126 4>, /*pp4*/ 1000 <1 126 4>, 1001 <1 126 4>, /*pp5*/ 1002 <1 126 4>, 1003 <1 126 4>, /*pp6*/ 1004 <1 126 4>; 1005 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU", 1006 "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", 1007 "IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4", 1008 "IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6"; 1009 }; 1010 1011 i2s0: hi6210_i2s { 1012 compatible = "hisilicon,hi6210-i2s"; 1013 reg = <0x0 0xf7118000 0x0 0x8000>, /* i2s unit */ 1014 <0x0 0xf7030000 0x0 0x400>, /* syscon */ 1015 <0x0 0xf7032000 0x0 0x400>; /* pmctrl */ 1016 interrupts = <0 123 0x4>; /* 155 "DigACodec_intr" - 32 */ 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&bt_pmx_func &bt_cfg_func>; 1019 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 1020 <&sys_ctrl HI6220_BBPPLL0_DIV>; 1021 clock-names = "dacodec", "i2s-base"; 1022 dmas = <&dma0 15 &dma0 14>; 1023 dma-names = "rx", "tx"; 1024 }; 1025 1026 hi6210_hdmi_card: hi6210_hdmi_card { 1027 compatible = "hisilicon,hi6210-hdmi-audio-card"; 1028 reg = <0 0 0 0>; 1029 sound-dai = <&i2s0>; 1030 }; 1031 }; 1032}; 1033