1 /* 2 * Copyright 2011 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __NV50_IR_DRIVER_H__ 24 #define __NV50_IR_DRIVER_H__ 25 26 #include "pipe/p_shader_tokens.h" 27 28 #include "tgsi/tgsi_util.h" 29 #include "tgsi/tgsi_parse.h" 30 #include "tgsi/tgsi_scan.h" 31 32 /* 33 * This struct constitutes linkage information in TGSI terminology. 34 * 35 * It is created by the code generator and handed to the pipe driver 36 * for input/output slot assignment. 37 */ 38 struct nv50_ir_varying 39 { 40 uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */ 41 42 unsigned mask : 4; /* vec4 mask */ 43 unsigned linear : 1; /* linearly interpolated if true (and not flat) */ 44 unsigned flat : 1; 45 unsigned sc : 1; /* special colour interpolation mode (SHADE_MODEL) */ 46 unsigned centroid : 1; 47 unsigned patch : 1; /* patch constant value */ 48 unsigned regular : 1; /* driver-specific meaning (e.g. input in sreg) */ 49 unsigned input : 1; /* indicates direction of system values */ 50 unsigned oread : 1; /* true if output is read from parallel TCP */ 51 52 ubyte id; /* TGSI register index */ 53 ubyte sn; /* TGSI semantic name */ 54 ubyte si; /* TGSI semantic index */ 55 }; 56 57 #define NV50_PROGRAM_IR_TGSI 0 58 #define NV50_PROGRAM_IR_SM4 1 59 #define NV50_PROGRAM_IR_GLSL 2 60 #define NV50_PROGRAM_IR_LLVM 3 61 62 #ifdef DEBUG 63 # define NV50_IR_DEBUG_BASIC (1 << 0) 64 # define NV50_IR_DEBUG_VERBOSE (2 << 0) 65 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2) 66 #else 67 # define NV50_IR_DEBUG_BASIC 0 68 # define NV50_IR_DEBUG_VERBOSE 0 69 # define NV50_IR_DEBUG_REG_ALLOC 0 70 #endif 71 72 struct nv50_ir_prog_symbol 73 { 74 uint32_t label; 75 uint32_t offset; 76 }; 77 78 #define NVISA_GK104_CHIPSET 0xe0 79 #define NVISA_GK20A_CHIPSET 0xea 80 #define NVISA_GM107_CHIPSET 0x110 81 82 struct nv50_ir_prog_info 83 { 84 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 85 86 uint8_t type; /* PIPE_SHADER */ 87 88 uint8_t optLevel; /* optimization level (0 to 3) */ 89 uint8_t dbgFlags; 90 91 struct { 92 int16_t maxGPR; /* may be -1 if none used */ 93 int16_t maxOutput; 94 uint32_t tlsSpace; /* required local memory per thread */ 95 uint32_t *code; 96 uint32_t codeSize; 97 uint32_t instructions; 98 uint8_t sourceRep; /* NV50_PROGRAM_IR */ 99 const void *source; 100 void *relocData; 101 void *fixupData; 102 struct nv50_ir_prog_symbol *syms; 103 uint16_t numSyms; 104 } bin; 105 106 struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS]; 107 struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS]; 108 struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS]; 109 uint8_t numInputs; 110 uint8_t numOutputs; 111 uint8_t numPatchConstants; /* also included in numInputs/numOutputs */ 112 uint8_t numSysVals; 113 114 struct { 115 uint32_t *buf; /* for IMMEDIATE_ARRAY */ 116 uint16_t bufSize; /* size of immediate array */ 117 uint16_t count; /* count of inline immediates */ 118 uint32_t *data; /* inline immediate data */ 119 uint8_t *type; /* for each vec4 (128 bit) */ 120 } immd; 121 122 union { 123 struct { 124 uint32_t inputMask[4]; /* mask of attributes read (1 bit per scalar) */ 125 bool usesDrawParameters; 126 } vp; 127 struct { 128 uint8_t inputPatchSize; 129 uint8_t outputPatchSize; 130 uint8_t partitioning; /* PIPE_TESS_PART */ 131 int8_t winding; /* +1 (clockwise) / -1 (counter-clockwise) */ 132 uint8_t domain; /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */ 133 uint8_t outputPrim; /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */ 134 } tp; 135 struct { 136 uint8_t inputPrim; 137 uint8_t outputPrim; 138 unsigned instanceCount; 139 unsigned maxVertices; 140 } gp; 141 struct { 142 unsigned numColourResults; 143 bool writesDepth; 144 bool earlyFragTests; 145 bool separateFragData; 146 bool usesDiscard; 147 bool persampleInvocation; 148 bool usesSampleMaskIn; 149 bool readsFramebuffer; 150 } fp; 151 struct { 152 uint32_t inputOffset; /* base address for user args */ 153 uint32_t sharedOffset; /* reserved space in s[] */ 154 uint32_t gridInfoBase; /* base address for NTID,NCTAID */ 155 uint32_t numThreads; /* max number of threads */ 156 } cp; 157 } prop; 158 159 uint8_t numBarriers; 160 161 struct { 162 uint8_t clipDistances; /* number of clip distance outputs */ 163 uint8_t cullDistances; /* number of cull distance outputs */ 164 int8_t genUserClip; /* request user clip planes for ClipVertex */ 165 uint8_t auxCBSlot; /* driver constant buffer slot */ 166 uint16_t ucpBase; /* base address for UCPs */ 167 uint16_t drawInfoBase; /* base address for draw parameters */ 168 uint16_t alphaRefBase; /* base address for alpha test values */ 169 uint8_t pointSize; /* output index for PointSize */ 170 uint8_t instanceId; /* system value index of InstanceID */ 171 uint8_t vertexId; /* system value index of VertexID */ 172 uint8_t edgeFlagIn; 173 uint8_t edgeFlagOut; 174 int8_t viewportId; /* output index of ViewportIndex */ 175 uint8_t fragDepth; /* output index of FragDepth */ 176 uint8_t sampleMask; /* output index of SampleMask */ 177 uint8_t backFaceColor[2]; /* input/output indices of back face colour */ 178 uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */ 179 bool fp64; /* program uses fp64 math */ 180 bool nv50styleSurfaces; /* generate gX[] access for raw buffers */ 181 uint16_t texBindBase; /* base address for tex handles (nve4) */ 182 uint16_t fbtexBindBase; /* base address for fbtex handle (nve4) */ 183 uint16_t suInfoBase; /* base address for surface info (nve4) */ 184 uint16_t bufInfoBase; /* base address for buffer info */ 185 uint16_t sampleInfoBase; /* base address for sample positions */ 186 uint8_t msInfoCBSlot; /* cX[] used for multisample info */ 187 uint16_t msInfoBase; /* base address for multisample info */ 188 uint16_t uboInfoBase; /* base address for compute UBOs (gk104+) */ 189 } io; 190 191 /* driver callback to assign input/output locations */ 192 int (*assignSlots)(struct nv50_ir_prog_info *); 193 194 void *driverPriv; 195 }; 196 197 #ifdef __cplusplus 198 extern "C" { 199 #endif 200 201 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *); 202 203 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code, 204 uint32_t codePos, 205 uint32_t libPos, 206 uint32_t dataPos); 207 208 extern void 209 nv50_ir_apply_fixups(void *fixupData, uint32_t *code, 210 bool force_per_sample, bool flatshade, 211 uint8_t alphatest); 212 213 /* obtain code that will be shared among programs */ 214 extern void nv50_ir_get_target_library(uint32_t chipset, 215 const uint32_t **code, uint32_t *size); 216 217 #ifdef __cplusplus 218 } 219 #endif 220 221 #endif // __NV50_IR_DRIVER_H__ 222