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1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbolELF.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/FormattedStream.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33     "mips-round-section-sizes", cl::init(false),
34     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
MipsTargetStreamer(MCStreamer & S)37 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
38     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
39   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
40 }
emitDirectiveSetMicroMips()41 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
emitDirectiveSetNoMicroMips()42 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
setUsesMicroMips()43 void MipsTargetStreamer::setUsesMicroMips() {}
emitDirectiveSetMips16()44 void MipsTargetStreamer::emitDirectiveSetMips16() {}
emitDirectiveSetNoMips16()45 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
emitDirectiveSetReorder()46 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
emitDirectiveSetNoReorder()47 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
emitDirectiveSetMacro()48 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
emitDirectiveSetNoMacro()49 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
emitDirectiveSetMsa()50 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
emitDirectiveSetNoMsa()51 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
emitDirectiveSetAt()52 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
emitDirectiveSetAtWithArg(unsigned RegNo)53 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
54   forbidModuleDirective();
55 }
emitDirectiveSetNoAt()56 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
emitDirectiveEnd(StringRef Name)57 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
emitDirectiveEnt(const MCSymbol & Symbol)58 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
emitDirectiveAbiCalls()59 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
emitDirectiveNaN2008()60 void MipsTargetStreamer::emitDirectiveNaN2008() {}
emitDirectiveNaNLegacy()61 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
emitDirectiveOptionPic0()62 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
emitDirectiveOptionPic2()63 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
emitDirectiveInsn()64 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg)65 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
66                                    unsigned ReturnReg) {}
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)67 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)68 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
69 }
emitDirectiveSetArch(StringRef Arch)70 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
71   forbidModuleDirective();
72 }
emitDirectiveSetMips0()73 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
emitDirectiveSetMips1()74 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
emitDirectiveSetMips2()75 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
emitDirectiveSetMips3()76 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
emitDirectiveSetMips4()77 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
emitDirectiveSetMips5()78 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
emitDirectiveSetMips32()79 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
emitDirectiveSetMips32R2()80 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
emitDirectiveSetMips32R3()81 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
emitDirectiveSetMips32R5()82 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
emitDirectiveSetMips32R6()83 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
emitDirectiveSetMips64()84 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
emitDirectiveSetMips64R2()85 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
emitDirectiveSetMips64R3()86 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
emitDirectiveSetMips64R5()87 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
emitDirectiveSetMips64R6()88 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
emitDirectiveSetPop()89 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
emitDirectiveSetPush()90 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
emitDirectiveSetSoftFloat()91 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
92   forbidModuleDirective();
93 }
emitDirectiveSetHardFloat()94 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
95   forbidModuleDirective();
96 }
emitDirectiveSetDsp()97 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
emitDirectiveSetNoDsp()98 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
emitDirectiveCpLoad(unsigned RegNo)99 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)100 bool MipsTargetStreamer::emitDirectiveCpRestore(
101     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
102     const MCSubtargetInfo *STI) {
103   forbidModuleDirective();
104   return true;
105 }
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)106 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
107                                               const MCSymbol &Sym, bool IsReg) {
108 }
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)109 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
110                                                bool SaveLocationIsRegister) {}
111 
emitDirectiveModuleFP()112 void MipsTargetStreamer::emitDirectiveModuleFP() {}
113 
emitDirectiveModuleOddSPReg()114 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
115   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
116     report_fatal_error("+nooddspreg is only valid for O32");
117 }
emitDirectiveModuleSoftFloat()118 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
emitDirectiveModuleHardFloat()119 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)120 void MipsTargetStreamer::emitDirectiveSetFp(
121     MipsABIFlagsSection::FpABIKind Value) {
122   forbidModuleDirective();
123 }
emitDirectiveSetOddSPReg()124 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
emitDirectiveSetNoOddSPReg()125 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
126   forbidModuleDirective();
127 }
128 
emitR(unsigned Opcode,unsigned Reg0,SMLoc IDLoc,const MCSubtargetInfo * STI)129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
130                                const MCSubtargetInfo *STI) {
131   MCInst TmpInst;
132   TmpInst.setOpcode(Opcode);
133   TmpInst.addOperand(MCOperand::createReg(Reg0));
134   TmpInst.setLoc(IDLoc);
135   getStreamer().EmitInstruction(TmpInst, *STI);
136 }
137 
emitRX(unsigned Opcode,unsigned Reg0,MCOperand Op1,SMLoc IDLoc,const MCSubtargetInfo * STI)138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
139                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
140   MCInst TmpInst;
141   TmpInst.setOpcode(Opcode);
142   TmpInst.addOperand(MCOperand::createReg(Reg0));
143   TmpInst.addOperand(Op1);
144   TmpInst.setLoc(IDLoc);
145   getStreamer().EmitInstruction(TmpInst, *STI);
146 }
147 
emitRI(unsigned Opcode,unsigned Reg0,int32_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI)148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
149                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
150   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
151 }
152 
emitRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,SMLoc IDLoc,const MCSubtargetInfo * STI)153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
154                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
155   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
156 }
157 
emitII(unsigned Opcode,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI)158 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
159                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
160   MCInst TmpInst;
161   TmpInst.setOpcode(Opcode);
162   TmpInst.addOperand(MCOperand::createImm(Imm1));
163   TmpInst.addOperand(MCOperand::createImm(Imm2));
164   TmpInst.setLoc(IDLoc);
165   getStreamer().EmitInstruction(TmpInst, *STI);
166 }
167 
emitRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,MCOperand Op2,SMLoc IDLoc,const MCSubtargetInfo * STI)168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
169                                  MCOperand Op2, SMLoc IDLoc,
170                                  const MCSubtargetInfo *STI) {
171   MCInst TmpInst;
172   TmpInst.setOpcode(Opcode);
173   TmpInst.addOperand(MCOperand::createReg(Reg0));
174   TmpInst.addOperand(MCOperand::createReg(Reg1));
175   TmpInst.addOperand(Op2);
176   TmpInst.setLoc(IDLoc);
177   getStreamer().EmitInstruction(TmpInst, *STI);
178 }
179 
emitRRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,SMLoc IDLoc,const MCSubtargetInfo * STI)180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
181                                  unsigned Reg2, SMLoc IDLoc,
182                                  const MCSubtargetInfo *STI) {
183   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
184 }
185 
emitRRI(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI)186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
187                                  int16_t Imm, SMLoc IDLoc,
188                                  const MCSubtargetInfo *STI) {
189   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
190 }
191 
emitAddu(unsigned DstReg,unsigned SrcReg,unsigned TrgReg,bool Is64Bit,const MCSubtargetInfo * STI)192 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
193                                   unsigned TrgReg, bool Is64Bit,
194                                   const MCSubtargetInfo *STI) {
195   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
196           STI);
197 }
198 
emitDSLL(unsigned DstReg,unsigned SrcReg,int16_t ShiftAmount,SMLoc IDLoc,const MCSubtargetInfo * STI)199 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
200                                   int16_t ShiftAmount, SMLoc IDLoc,
201                                   const MCSubtargetInfo *STI) {
202   if (ShiftAmount >= 32) {
203     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
204     return;
205   }
206 
207   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
208 }
209 
emitEmptyDelaySlot(bool hasShortDelaySlot,SMLoc IDLoc,const MCSubtargetInfo * STI)210 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
211                                             const MCSubtargetInfo *STI) {
212   if (hasShortDelaySlot)
213     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
214   else
215     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
216 }
217 
emitNop(SMLoc IDLoc,const MCSubtargetInfo * STI)218 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
219   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
220 }
221 
222 /// Emit the $gp restore operation for .cprestore.
emitGPRestore(int Offset,SMLoc IDLoc,const MCSubtargetInfo * STI)223 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
224                                        const MCSubtargetInfo *STI) {
225   emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
226                         STI);
227 }
228 
229 /// Emit a store instruction with an immediate offset.
emitStoreWithImmOffset(unsigned Opcode,unsigned SrcReg,unsigned BaseReg,int64_t Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)230 void MipsTargetStreamer::emitStoreWithImmOffset(
231     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
232     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
233     const MCSubtargetInfo *STI) {
234   if (isInt<16>(Offset)) {
235     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
236     return;
237   }
238 
239   // sw $8, offset($8) => lui $at, %hi(offset)
240   //                      add $at, $at, $8
241   //                      sw $8, %lo(offset)($at)
242 
243   unsigned ATReg = GetATReg();
244   if (!ATReg)
245     return;
246 
247   unsigned LoOffset = Offset & 0x0000ffff;
248   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
249 
250   // If msb of LoOffset is 1(negative number) we must increment HiOffset
251   // to account for the sign-extension of the low part.
252   if (LoOffset & 0x8000)
253     HiOffset++;
254 
255   // Generate the base address in ATReg.
256   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
257   if (BaseReg != Mips::ZERO)
258     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
259   // Emit the store with the adjusted base and offset.
260   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
261 }
262 
263 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
264 /// out of range for a simm16 will be expanded to appropriate instructions.
emitStoreWithSymOffset(unsigned Opcode,unsigned SrcReg,unsigned BaseReg,MCOperand & HiOperand,MCOperand & LoOperand,unsigned ATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)265 void MipsTargetStreamer::emitStoreWithSymOffset(
266     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
267     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
268     const MCSubtargetInfo *STI) {
269   // sw $8, sym => lui $at, %hi(sym)
270   //               sw $8, %lo(sym)($at)
271 
272   // Generate the base address in ATReg.
273   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
274   if (BaseReg != Mips::ZERO)
275     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
276   // Emit the store with the adjusted base and offset.
277   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
278 }
279 
280 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
281 /// permitted to be the same register iff DstReg is distinct from BaseReg and
282 /// DstReg is a GPR. It is the callers responsibility to identify such cases
283 /// and pass the appropriate register in TmpReg.
emitLoadWithImmOffset(unsigned Opcode,unsigned DstReg,unsigned BaseReg,int64_t Offset,unsigned TmpReg,SMLoc IDLoc,const MCSubtargetInfo * STI)284 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
285                                                unsigned BaseReg, int64_t Offset,
286                                                unsigned TmpReg, SMLoc IDLoc,
287                                                const MCSubtargetInfo *STI) {
288   if (isInt<16>(Offset)) {
289     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
290     return;
291   }
292 
293   // 1) lw $8, offset($9) => lui $8, %hi(offset)
294   //                         add $8, $8, $9
295   //                         lw $8, %lo(offset)($9)
296   // 2) lw $8, offset($8) => lui $at, %hi(offset)
297   //                         add $at, $at, $8
298   //                         lw $8, %lo(offset)($at)
299 
300   unsigned LoOffset = Offset & 0x0000ffff;
301   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
302 
303   // If msb of LoOffset is 1(negative number) we must increment HiOffset
304   // to account for the sign-extension of the low part.
305   if (LoOffset & 0x8000)
306     HiOffset++;
307 
308   // Generate the base address in TmpReg.
309   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
310   if (BaseReg != Mips::ZERO)
311     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
312   // Emit the load with the adjusted base and offset.
313   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
314 }
315 
316 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
317 /// out of range for a simm16 will be expanded to appropriate instructions.
318 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
319 /// GPR. It is the callers responsibility to identify such cases and pass the
320 /// appropriate register in TmpReg.
emitLoadWithSymOffset(unsigned Opcode,unsigned DstReg,unsigned BaseReg,MCOperand & HiOperand,MCOperand & LoOperand,unsigned TmpReg,SMLoc IDLoc,const MCSubtargetInfo * STI)321 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
322                                                unsigned BaseReg,
323                                                MCOperand &HiOperand,
324                                                MCOperand &LoOperand,
325                                                unsigned TmpReg, SMLoc IDLoc,
326                                                const MCSubtargetInfo *STI) {
327   // 1) lw $8, sym        => lui $8, %hi(sym)
328   //                         lw $8, %lo(sym)($8)
329   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
330   //                         ldc1 $f0, %lo(sym)($at)
331 
332   // Generate the base address in TmpReg.
333   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
334   if (BaseReg != Mips::ZERO)
335     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
336   // Emit the load with the adjusted base and offset.
337   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
338 }
339 
MipsTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)340 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
341                                              formatted_raw_ostream &OS)
342     : MipsTargetStreamer(S), OS(OS) {}
343 
emitDirectiveSetMicroMips()344 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
345   OS << "\t.set\tmicromips\n";
346   forbidModuleDirective();
347 }
348 
emitDirectiveSetNoMicroMips()349 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
350   OS << "\t.set\tnomicromips\n";
351   forbidModuleDirective();
352 }
353 
emitDirectiveSetMips16()354 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
355   OS << "\t.set\tmips16\n";
356   forbidModuleDirective();
357 }
358 
emitDirectiveSetNoMips16()359 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
360   OS << "\t.set\tnomips16\n";
361   MipsTargetStreamer::emitDirectiveSetNoMips16();
362 }
363 
emitDirectiveSetReorder()364 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
365   OS << "\t.set\treorder\n";
366   MipsTargetStreamer::emitDirectiveSetReorder();
367 }
368 
emitDirectiveSetNoReorder()369 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
370   OS << "\t.set\tnoreorder\n";
371   forbidModuleDirective();
372 }
373 
emitDirectiveSetMacro()374 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
375   OS << "\t.set\tmacro\n";
376   MipsTargetStreamer::emitDirectiveSetMacro();
377 }
378 
emitDirectiveSetNoMacro()379 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
380   OS << "\t.set\tnomacro\n";
381   MipsTargetStreamer::emitDirectiveSetNoMacro();
382 }
383 
emitDirectiveSetMsa()384 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
385   OS << "\t.set\tmsa\n";
386   MipsTargetStreamer::emitDirectiveSetMsa();
387 }
388 
emitDirectiveSetNoMsa()389 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
390   OS << "\t.set\tnomsa\n";
391   MipsTargetStreamer::emitDirectiveSetNoMsa();
392 }
393 
emitDirectiveSetAt()394 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
395   OS << "\t.set\tat\n";
396   MipsTargetStreamer::emitDirectiveSetAt();
397 }
398 
emitDirectiveSetAtWithArg(unsigned RegNo)399 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
400   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
401   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
402 }
403 
emitDirectiveSetNoAt()404 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
405   OS << "\t.set\tnoat\n";
406   MipsTargetStreamer::emitDirectiveSetNoAt();
407 }
408 
emitDirectiveEnd(StringRef Name)409 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
410   OS << "\t.end\t" << Name << '\n';
411 }
412 
emitDirectiveEnt(const MCSymbol & Symbol)413 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
414   OS << "\t.ent\t" << Symbol.getName() << '\n';
415 }
416 
emitDirectiveAbiCalls()417 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
418 
emitDirectiveNaN2008()419 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
420 
emitDirectiveNaNLegacy()421 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
422   OS << "\t.nan\tlegacy\n";
423 }
424 
emitDirectiveOptionPic0()425 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
426   OS << "\t.option\tpic0\n";
427 }
428 
emitDirectiveOptionPic2()429 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
430   OS << "\t.option\tpic2\n";
431 }
432 
emitDirectiveInsn()433 void MipsTargetAsmStreamer::emitDirectiveInsn() {
434   MipsTargetStreamer::emitDirectiveInsn();
435   OS << "\t.insn\n";
436 }
437 
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg)438 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
439                                       unsigned ReturnReg) {
440   OS << "\t.frame\t$"
441      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
442      << StackSize << ",$"
443      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
444 }
445 
emitDirectiveSetArch(StringRef Arch)446 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
447   OS << "\t.set arch=" << Arch << "\n";
448   MipsTargetStreamer::emitDirectiveSetArch(Arch);
449 }
450 
emitDirectiveSetMips0()451 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
452   OS << "\t.set\tmips0\n";
453   MipsTargetStreamer::emitDirectiveSetMips0();
454 }
455 
emitDirectiveSetMips1()456 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
457   OS << "\t.set\tmips1\n";
458   MipsTargetStreamer::emitDirectiveSetMips1();
459 }
460 
emitDirectiveSetMips2()461 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
462   OS << "\t.set\tmips2\n";
463   MipsTargetStreamer::emitDirectiveSetMips2();
464 }
465 
emitDirectiveSetMips3()466 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
467   OS << "\t.set\tmips3\n";
468   MipsTargetStreamer::emitDirectiveSetMips3();
469 }
470 
emitDirectiveSetMips4()471 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
472   OS << "\t.set\tmips4\n";
473   MipsTargetStreamer::emitDirectiveSetMips4();
474 }
475 
emitDirectiveSetMips5()476 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
477   OS << "\t.set\tmips5\n";
478   MipsTargetStreamer::emitDirectiveSetMips5();
479 }
480 
emitDirectiveSetMips32()481 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
482   OS << "\t.set\tmips32\n";
483   MipsTargetStreamer::emitDirectiveSetMips32();
484 }
485 
emitDirectiveSetMips32R2()486 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
487   OS << "\t.set\tmips32r2\n";
488   MipsTargetStreamer::emitDirectiveSetMips32R2();
489 }
490 
emitDirectiveSetMips32R3()491 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
492   OS << "\t.set\tmips32r3\n";
493   MipsTargetStreamer::emitDirectiveSetMips32R3();
494 }
495 
emitDirectiveSetMips32R5()496 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
497   OS << "\t.set\tmips32r5\n";
498   MipsTargetStreamer::emitDirectiveSetMips32R5();
499 }
500 
emitDirectiveSetMips32R6()501 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
502   OS << "\t.set\tmips32r6\n";
503   MipsTargetStreamer::emitDirectiveSetMips32R6();
504 }
505 
emitDirectiveSetMips64()506 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
507   OS << "\t.set\tmips64\n";
508   MipsTargetStreamer::emitDirectiveSetMips64();
509 }
510 
emitDirectiveSetMips64R2()511 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
512   OS << "\t.set\tmips64r2\n";
513   MipsTargetStreamer::emitDirectiveSetMips64R2();
514 }
515 
emitDirectiveSetMips64R3()516 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
517   OS << "\t.set\tmips64r3\n";
518   MipsTargetStreamer::emitDirectiveSetMips64R3();
519 }
520 
emitDirectiveSetMips64R5()521 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
522   OS << "\t.set\tmips64r5\n";
523   MipsTargetStreamer::emitDirectiveSetMips64R5();
524 }
525 
emitDirectiveSetMips64R6()526 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
527   OS << "\t.set\tmips64r6\n";
528   MipsTargetStreamer::emitDirectiveSetMips64R6();
529 }
530 
emitDirectiveSetDsp()531 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
532   OS << "\t.set\tdsp\n";
533   MipsTargetStreamer::emitDirectiveSetDsp();
534 }
535 
emitDirectiveSetNoDsp()536 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
537   OS << "\t.set\tnodsp\n";
538   MipsTargetStreamer::emitDirectiveSetNoDsp();
539 }
540 
emitDirectiveSetPop()541 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
542   OS << "\t.set\tpop\n";
543   MipsTargetStreamer::emitDirectiveSetPop();
544 }
545 
emitDirectiveSetPush()546 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
547  OS << "\t.set\tpush\n";
548  MipsTargetStreamer::emitDirectiveSetPush();
549 }
550 
emitDirectiveSetSoftFloat()551 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
552   OS << "\t.set\tsoftfloat\n";
553   MipsTargetStreamer::emitDirectiveSetSoftFloat();
554 }
555 
emitDirectiveSetHardFloat()556 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
557   OS << "\t.set\thardfloat\n";
558   MipsTargetStreamer::emitDirectiveSetHardFloat();
559 }
560 
561 // Print a 32 bit hex number with all numbers.
printHex32(unsigned Value,raw_ostream & OS)562 static void printHex32(unsigned Value, raw_ostream &OS) {
563   OS << "0x";
564   for (int i = 7; i >= 0; i--)
565     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
566 }
567 
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)568 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
569                                      int CPUTopSavedRegOff) {
570   OS << "\t.mask \t";
571   printHex32(CPUBitmask, OS);
572   OS << ',' << CPUTopSavedRegOff << '\n';
573 }
574 
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)575 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
576                                       int FPUTopSavedRegOff) {
577   OS << "\t.fmask\t";
578   printHex32(FPUBitmask, OS);
579   OS << "," << FPUTopSavedRegOff << '\n';
580 }
581 
emitDirectiveCpLoad(unsigned RegNo)582 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
583   OS << "\t.cpload\t$"
584      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
585   forbidModuleDirective();
586 }
587 
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)588 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
589     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
590     const MCSubtargetInfo *STI) {
591   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
592   OS << "\t.cprestore\t" << Offset << "\n";
593   return true;
594 }
595 
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)596 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
597                                                  int RegOrOffset,
598                                                  const MCSymbol &Sym,
599                                                  bool IsReg) {
600   OS << "\t.cpsetup\t$"
601      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
602 
603   if (IsReg)
604     OS << "$"
605        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
606   else
607     OS << RegOrOffset;
608 
609   OS << ", ";
610 
611   OS << Sym.getName();
612   forbidModuleDirective();
613 }
614 
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)615 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
616                                                   bool SaveLocationIsRegister) {
617   OS << "\t.cpreturn";
618   forbidModuleDirective();
619 }
620 
emitDirectiveModuleFP()621 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
622   OS << "\t.module\tfp=";
623   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
624 }
625 
emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)626 void MipsTargetAsmStreamer::emitDirectiveSetFp(
627     MipsABIFlagsSection::FpABIKind Value) {
628   MipsTargetStreamer::emitDirectiveSetFp(Value);
629 
630   OS << "\t.set\tfp=";
631   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
632 }
633 
emitDirectiveModuleOddSPReg()634 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
635   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
636 
637   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
638 }
639 
emitDirectiveSetOddSPReg()640 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
641   MipsTargetStreamer::emitDirectiveSetOddSPReg();
642   OS << "\t.set\toddspreg\n";
643 }
644 
emitDirectiveSetNoOddSPReg()645 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
646   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
647   OS << "\t.set\tnooddspreg\n";
648 }
649 
emitDirectiveModuleSoftFloat()650 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
651   OS << "\t.module\tsoftfloat\n";
652 }
653 
emitDirectiveModuleHardFloat()654 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
655   OS << "\t.module\thardfloat\n";
656 }
657 
658 // This part is for ELF object output.
MipsTargetELFStreamer(MCStreamer & S,const MCSubtargetInfo & STI)659 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
660                                              const MCSubtargetInfo &STI)
661     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
662   MCAssembler &MCA = getStreamer().getAssembler();
663 
664   // It's possible that MCObjectFileInfo isn't fully initialized at this point
665   // due to an initialization order problem where LLVMTargetMachine creates the
666   // target streamer before TargetLoweringObjectFile calls
667   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
668   // covers all cases so this statement covers most cases and direct object
669   // emission must call setPic() once MCObjectFileInfo has been initialized. The
670   // cases we don't handle here are covered by MipsAsmPrinter.
671   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
672 
673   const FeatureBitset &Features = STI.getFeatureBits();
674 
675   // Set the header flags that we can in the constructor.
676   // FIXME: This is a fairly terrible hack. We set the rest
677   // of these in the destructor. The problem here is two-fold:
678   //
679   // a: Some of the eflags can be set/reset by directives.
680   // b: There aren't any usage paths that initialize the ABI
681   //    pointer until after we initialize either an assembler
682   //    or the target machine.
683   // We can fix this by making the target streamer construct
684   // the ABI, but this is fraught with wide ranging dependency
685   // issues as well.
686   unsigned EFlags = MCA.getELFHeaderEFlags();
687 
688   // Architecture
689   if (Features[Mips::FeatureMips64r6])
690     EFlags |= ELF::EF_MIPS_ARCH_64R6;
691   else if (Features[Mips::FeatureMips64r2] ||
692            Features[Mips::FeatureMips64r3] ||
693            Features[Mips::FeatureMips64r5])
694     EFlags |= ELF::EF_MIPS_ARCH_64R2;
695   else if (Features[Mips::FeatureMips64])
696     EFlags |= ELF::EF_MIPS_ARCH_64;
697   else if (Features[Mips::FeatureMips5])
698     EFlags |= ELF::EF_MIPS_ARCH_5;
699   else if (Features[Mips::FeatureMips4])
700     EFlags |= ELF::EF_MIPS_ARCH_4;
701   else if (Features[Mips::FeatureMips3])
702     EFlags |= ELF::EF_MIPS_ARCH_3;
703   else if (Features[Mips::FeatureMips32r6])
704     EFlags |= ELF::EF_MIPS_ARCH_32R6;
705   else if (Features[Mips::FeatureMips32r2] ||
706            Features[Mips::FeatureMips32r3] ||
707            Features[Mips::FeatureMips32r5])
708     EFlags |= ELF::EF_MIPS_ARCH_32R2;
709   else if (Features[Mips::FeatureMips32])
710     EFlags |= ELF::EF_MIPS_ARCH_32;
711   else if (Features[Mips::FeatureMips2])
712     EFlags |= ELF::EF_MIPS_ARCH_2;
713   else
714     EFlags |= ELF::EF_MIPS_ARCH_1;
715 
716   // Machine
717   if (Features[Mips::FeatureCnMips])
718     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
719 
720   // Other options.
721   if (Features[Mips::FeatureNaN2008])
722     EFlags |= ELF::EF_MIPS_NAN2008;
723 
724   // -mabicalls and -mplt are not implemented but we should act as if they were
725   // given.
726   EFlags |= ELF::EF_MIPS_CPIC;
727 
728   MCA.setELFHeaderEFlags(EFlags);
729 }
730 
emitLabel(MCSymbol * S)731 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
732   auto *Symbol = cast<MCSymbolELF>(S);
733   if (!isMicroMipsEnabled())
734     return;
735   getStreamer().getAssembler().registerSymbol(*Symbol);
736   uint8_t Type = Symbol->getType();
737   if (Type != ELF::STT_FUNC)
738     return;
739 
740   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
741 }
742 
finish()743 void MipsTargetELFStreamer::finish() {
744   MCAssembler &MCA = getStreamer().getAssembler();
745   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
746 
747   // .bss, .text and .data are always at least 16-byte aligned.
748   MCSection &TextSection = *OFI.getTextSection();
749   MCA.registerSection(TextSection);
750   MCSection &DataSection = *OFI.getDataSection();
751   MCA.registerSection(DataSection);
752   MCSection &BSSSection = *OFI.getBSSSection();
753   MCA.registerSection(BSSSection);
754 
755   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
756   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
757   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
758 
759   if (RoundSectionSizes) {
760     // Make sections sizes a multiple of the alignment. This is useful for
761     // verifying the output of IAS against the output of other assemblers but
762     // it's not necessary to produce a correct object and increases section
763     // size.
764     MCStreamer &OS = getStreamer();
765     for (MCSection &S : MCA) {
766       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
767 
768       unsigned Alignment = Section.getAlignment();
769       if (Alignment) {
770         OS.SwitchSection(&Section);
771         if (Section.UseCodeAlign())
772           OS.EmitCodeAlignment(Alignment, Alignment);
773         else
774           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
775       }
776     }
777   }
778 
779   const FeatureBitset &Features = STI.getFeatureBits();
780 
781   // Update e_header flags. See the FIXME and comment above in
782   // the constructor for a full rundown on this.
783   unsigned EFlags = MCA.getELFHeaderEFlags();
784 
785   // ABI
786   // N64 does not require any ABI bits.
787   if (getABI().IsO32())
788     EFlags |= ELF::EF_MIPS_ABI_O32;
789   else if (getABI().IsN32())
790     EFlags |= ELF::EF_MIPS_ABI2;
791 
792   if (Features[Mips::FeatureGP64Bit]) {
793     if (getABI().IsO32())
794       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
795   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
796     EFlags |= ELF::EF_MIPS_32BITMODE;
797 
798   // If we've set the cpic eflag and we're n64, go ahead and set the pic
799   // one as well.
800   if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
801     EFlags |= ELF::EF_MIPS_PIC;
802 
803   MCA.setELFHeaderEFlags(EFlags);
804 
805   // Emit all the option records.
806   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
807   // .reginfo.
808   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
809   MEF.EmitMipsOptionRecords();
810 
811   emitMipsAbiFlags();
812 }
813 
emitAssignment(MCSymbol * S,const MCExpr * Value)814 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
815   auto *Symbol = cast<MCSymbolELF>(S);
816   // If on rhs is micromips symbol then mark Symbol as microMips.
817   if (Value->getKind() != MCExpr::SymbolRef)
818     return;
819   const auto &RhsSym = cast<MCSymbolELF>(
820       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
821 
822   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
823     return;
824 
825   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
826 }
827 
getStreamer()828 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
829   return static_cast<MCELFStreamer &>(Streamer);
830 }
831 
emitDirectiveSetMicroMips()832 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
833   MicroMipsEnabled = true;
834   forbidModuleDirective();
835 }
836 
emitDirectiveSetNoMicroMips()837 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
838   MicroMipsEnabled = false;
839   forbidModuleDirective();
840 }
841 
setUsesMicroMips()842 void MipsTargetELFStreamer::setUsesMicroMips() {
843   MCAssembler &MCA = getStreamer().getAssembler();
844   unsigned Flags = MCA.getELFHeaderEFlags();
845   Flags |= ELF::EF_MIPS_MICROMIPS;
846   MCA.setELFHeaderEFlags(Flags);
847 }
848 
emitDirectiveSetMips16()849 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
850   MCAssembler &MCA = getStreamer().getAssembler();
851   unsigned Flags = MCA.getELFHeaderEFlags();
852   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
853   MCA.setELFHeaderEFlags(Flags);
854   forbidModuleDirective();
855 }
856 
emitDirectiveSetNoReorder()857 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
858   MCAssembler &MCA = getStreamer().getAssembler();
859   unsigned Flags = MCA.getELFHeaderEFlags();
860   Flags |= ELF::EF_MIPS_NOREORDER;
861   MCA.setELFHeaderEFlags(Flags);
862   forbidModuleDirective();
863 }
864 
emitDirectiveEnd(StringRef Name)865 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
866   MCAssembler &MCA = getStreamer().getAssembler();
867   MCContext &Context = MCA.getContext();
868   MCStreamer &OS = getStreamer();
869 
870   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
871 
872   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
873   const MCSymbolRefExpr *ExprRef =
874       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
875 
876   MCA.registerSection(*Sec);
877   Sec->setAlignment(4);
878 
879   OS.PushSection();
880 
881   OS.SwitchSection(Sec);
882 
883   OS.EmitValueImpl(ExprRef, 4);
884 
885   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
886   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
887 
888   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
889   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
890 
891   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
892   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
893   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
894 
895   // The .end directive marks the end of a procedure. Invalidate
896   // the information gathered up until this point.
897   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
898 
899   OS.PopSection();
900 
901   // .end also implicitly sets the size.
902   MCSymbol *CurPCSym = Context.createTempSymbol();
903   OS.EmitLabel(CurPCSym);
904   const MCExpr *Size = MCBinaryExpr::createSub(
905       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
906       ExprRef, Context);
907   int64_t AbsSize;
908   if (!Size->evaluateAsAbsolute(AbsSize, MCA))
909     llvm_unreachable("Function size must be evaluatable as absolute");
910   Size = MCConstantExpr::create(AbsSize, Context);
911   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
912 }
913 
emitDirectiveEnt(const MCSymbol & Symbol)914 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
915   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
916 
917   // .ent also acts like an implicit '.type symbol, STT_FUNC'
918   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
919 }
920 
emitDirectiveAbiCalls()921 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
922   MCAssembler &MCA = getStreamer().getAssembler();
923   unsigned Flags = MCA.getELFHeaderEFlags();
924   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
925   MCA.setELFHeaderEFlags(Flags);
926 }
927 
emitDirectiveNaN2008()928 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
929   MCAssembler &MCA = getStreamer().getAssembler();
930   unsigned Flags = MCA.getELFHeaderEFlags();
931   Flags |= ELF::EF_MIPS_NAN2008;
932   MCA.setELFHeaderEFlags(Flags);
933 }
934 
emitDirectiveNaNLegacy()935 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
936   MCAssembler &MCA = getStreamer().getAssembler();
937   unsigned Flags = MCA.getELFHeaderEFlags();
938   Flags &= ~ELF::EF_MIPS_NAN2008;
939   MCA.setELFHeaderEFlags(Flags);
940 }
941 
emitDirectiveOptionPic0()942 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
943   MCAssembler &MCA = getStreamer().getAssembler();
944   unsigned Flags = MCA.getELFHeaderEFlags();
945   // This option overrides other PIC options like -KPIC.
946   Pic = false;
947   Flags &= ~ELF::EF_MIPS_PIC;
948   MCA.setELFHeaderEFlags(Flags);
949 }
950 
emitDirectiveOptionPic2()951 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
952   MCAssembler &MCA = getStreamer().getAssembler();
953   unsigned Flags = MCA.getELFHeaderEFlags();
954   Pic = true;
955   // NOTE: We are following the GAS behaviour here which means the directive
956   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
957   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
958   // EF_MIPS_CPIC to be mutually exclusive.
959   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
960   MCA.setELFHeaderEFlags(Flags);
961 }
962 
emitDirectiveInsn()963 void MipsTargetELFStreamer::emitDirectiveInsn() {
964   MipsTargetStreamer::emitDirectiveInsn();
965   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
966   MEF.createPendingLabelRelocs();
967 }
968 
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg_)969 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
970                                       unsigned ReturnReg_) {
971   MCContext &Context = getStreamer().getAssembler().getContext();
972   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
973 
974   FrameInfoSet = true;
975   FrameReg = RegInfo->getEncodingValue(StackReg);
976   FrameOffset = StackSize;
977   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
978 }
979 
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)980 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
981                                      int CPUTopSavedRegOff) {
982   GPRInfoSet = true;
983   GPRBitMask = CPUBitmask;
984   GPROffset = CPUTopSavedRegOff;
985 }
986 
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)987 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
988                                       int FPUTopSavedRegOff) {
989   FPRInfoSet = true;
990   FPRBitMask = FPUBitmask;
991   FPROffset = FPUTopSavedRegOff;
992 }
993 
emitDirectiveCpLoad(unsigned RegNo)994 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
995   // .cpload $reg
996   // This directive expands to:
997   // lui   $gp, %hi(_gp_disp)
998   // addui $gp, $gp, %lo(_gp_disp)
999   // addu  $gp, $gp, $reg
1000   // when support for position independent code is enabled.
1001   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1002     return;
1003 
1004   // There's a GNU extension controlled by -mno-shared that allows
1005   // locally-binding symbols to be accessed using absolute addresses.
1006   // This is currently not supported. When supported -mno-shared makes
1007   // .cpload expand to:
1008   //   lui     $gp, %hi(__gnu_local_gp)
1009   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1010 
1011   StringRef SymName("_gp_disp");
1012   MCAssembler &MCA = getStreamer().getAssembler();
1013   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1014   MCA.registerSymbol(*GP_Disp);
1015 
1016   MCInst TmpInst;
1017   TmpInst.setOpcode(Mips::LUi);
1018   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1019   const MCExpr *HiSym = MipsMCExpr::create(
1020       MipsMCExpr::MEK_HI,
1021       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1022                               MCA.getContext()),
1023       MCA.getContext());
1024   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1025   getStreamer().EmitInstruction(TmpInst, STI);
1026 
1027   TmpInst.clear();
1028 
1029   TmpInst.setOpcode(Mips::ADDiu);
1030   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1031   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1032   const MCExpr *LoSym = MipsMCExpr::create(
1033       MipsMCExpr::MEK_LO,
1034       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1035                               MCA.getContext()),
1036       MCA.getContext());
1037   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1038   getStreamer().EmitInstruction(TmpInst, STI);
1039 
1040   TmpInst.clear();
1041 
1042   TmpInst.setOpcode(Mips::ADDu);
1043   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1044   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1045   TmpInst.addOperand(MCOperand::createReg(RegNo));
1046   getStreamer().EmitInstruction(TmpInst, STI);
1047 
1048   forbidModuleDirective();
1049 }
1050 
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)1051 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1052     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1053     const MCSubtargetInfo *STI) {
1054   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1055   // .cprestore offset
1056   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1057   // to:
1058   //    sw $gp, offset($sp)
1059   // and adds a corresponding LW after every JAL.
1060 
1061   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1062   // is used in non-PIC mode.
1063   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1064     return true;
1065 
1066   // Store the $gp on the stack.
1067   emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1068                          STI);
1069   return true;
1070 }
1071 
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)1072 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1073                                                  int RegOrOffset,
1074                                                  const MCSymbol &Sym,
1075                                                  bool IsReg) {
1076   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1077   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1078     return;
1079 
1080   forbidModuleDirective();
1081 
1082   MCAssembler &MCA = getStreamer().getAssembler();
1083   MCInst Inst;
1084 
1085   // Either store the old $gp in a register or on the stack
1086   if (IsReg) {
1087     // move $save, $gpreg
1088     emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1089   } else {
1090     // sd $gpreg, offset($sp)
1091     emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1092   }
1093 
1094   if (getABI().IsN32()) {
1095     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1096     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1097         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1098         MCA.getContext());
1099     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1100         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1101         MCA.getContext());
1102 
1103     // lui $gp, %hi(__gnu_local_gp)
1104     emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1105 
1106     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1107     emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1108             SMLoc(), &STI);
1109 
1110     return;
1111   }
1112 
1113   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1114       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1115       MCA.getContext());
1116   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1117       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1118       MCA.getContext());
1119 
1120   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1121   emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1122 
1123   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1124   emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1125           SMLoc(), &STI);
1126 
1127   // daddu  $gp, $gp, $funcreg
1128   emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1129 }
1130 
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)1131 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1132                                                   bool SaveLocationIsRegister) {
1133   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1134   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1135     return;
1136 
1137   MCInst Inst;
1138   // Either restore the old $gp from a register or on the stack
1139   if (SaveLocationIsRegister) {
1140     Inst.setOpcode(Mips::OR);
1141     Inst.addOperand(MCOperand::createReg(Mips::GP));
1142     Inst.addOperand(MCOperand::createReg(SaveLocation));
1143     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1144   } else {
1145     Inst.setOpcode(Mips::LD);
1146     Inst.addOperand(MCOperand::createReg(Mips::GP));
1147     Inst.addOperand(MCOperand::createReg(Mips::SP));
1148     Inst.addOperand(MCOperand::createImm(SaveLocation));
1149   }
1150   getStreamer().EmitInstruction(Inst, STI);
1151 
1152   forbidModuleDirective();
1153 }
1154 
emitMipsAbiFlags()1155 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1156   MCAssembler &MCA = getStreamer().getAssembler();
1157   MCContext &Context = MCA.getContext();
1158   MCStreamer &OS = getStreamer();
1159   MCSectionELF *Sec = Context.getELFSection(
1160       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1161   MCA.registerSection(*Sec);
1162   Sec->setAlignment(8);
1163   OS.SwitchSection(Sec);
1164 
1165   OS << ABIFlagsSection;
1166 }
1167