1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
evergreen_array_mode(unsigned mode)35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
eg_num_banks(uint32_t nbanks)47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
eg_tile_split(unsigned tile_split)63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
eg_macro_tile_aspect(unsigned macro_tile_aspect)78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
eg_bank_wh(unsigned bankwh)90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
r600_translate_blend_function(int blend_func)102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
r600_translate_blend_factor(int blend_fact)123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
r600_tex_dim(unsigned dim,unsigned nr_samples)172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
173 {
174 switch (dim) {
175 default:
176 case PIPE_TEXTURE_1D:
177 return V_030000_SQ_TEX_DIM_1D;
178 case PIPE_TEXTURE_1D_ARRAY:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY;
180 case PIPE_TEXTURE_2D:
181 case PIPE_TEXTURE_RECT:
182 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
183 V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
186 V_030000_SQ_TEX_DIM_2D_ARRAY;
187 case PIPE_TEXTURE_3D:
188 return V_030000_SQ_TEX_DIM_3D;
189 case PIPE_TEXTURE_CUBE:
190 case PIPE_TEXTURE_CUBE_ARRAY:
191 return V_030000_SQ_TEX_DIM_CUBEMAP;
192 }
193 }
194
r600_translate_dbformat(enum pipe_format format)195 static uint32_t r600_translate_dbformat(enum pipe_format format)
196 {
197 switch (format) {
198 case PIPE_FORMAT_Z16_UNORM:
199 return V_028040_Z_16;
200 case PIPE_FORMAT_Z24X8_UNORM:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
202 case PIPE_FORMAT_X8Z24_UNORM:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
204 return V_028040_Z_24;
205 case PIPE_FORMAT_Z32_FLOAT:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
207 return V_028040_Z_32_FLOAT;
208 default:
209 return ~0U;
210 }
211 }
212
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
214 {
215 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
216 FALSE) != ~0U;
217 }
218
r600_is_colorbuffer_format_supported(enum chip_class chip,enum pipe_format format)219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
222 r600_translate_colorswap(format, FALSE) != ~0U;
223 }
224
r600_is_zs_format_supported(enum pipe_format format)225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
evergreen_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned usage)230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if ((usage & PIPE_BIND_LINEAR) &&
298 !util_format_is_compressed(format) &&
299 !(usage & PIPE_BIND_DEPTH_STENCIL))
300 retval |= PIPE_BIND_LINEAR;
301
302 return retval == usage;
303 }
304
evergreen_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
evergreen_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
evergreen_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
evergreen_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->scissor_enable = state->scissor;
471 rs->clip_halfz = state->clip_halfz;
472 rs->flatshade = state->flatshade;
473 rs->sprite_coord_enable = state->sprite_coord_enable;
474 rs->two_side = state->light_twoside;
475 rs->clip_plane_enable = state->clip_plane_enable;
476 rs->pa_sc_line_stipple = state->line_stipple_enable ?
477 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
478 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
479 rs->pa_cl_clip_cntl =
480 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
481 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
482 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
483 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
484 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
485 rs->multisample_enable = state->multisample;
486
487 /* offset */
488 rs->offset_units = state->offset_units;
489 rs->offset_scale = state->offset_scale * 16.0f;
490 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
491 rs->offset_units_unscaled = state->offset_units_unscaled;
492
493 if (state->point_size_per_vertex) {
494 psize_min = util_get_min_point_size(state);
495 psize_max = 8192;
496 } else {
497 /* Force the point size to be as if the vertex output was disabled. */
498 psize_min = state->point_size;
499 psize_max = state->point_size;
500 }
501
502 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
503 if (state->sprite_coord_enable) {
504 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
505 S_0286D4_PNT_SPRITE_OVRD_X(2) |
506 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
507 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
508 S_0286D4_PNT_SPRITE_OVRD_W(1);
509 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
510 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
511 }
512 }
513
514 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
515 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
516 tmp = r600_pack_float_12p4(state->point_size/2);
517 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
518 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
519 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
520 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
521 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
522 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
523 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
524
525 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
526 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
527 S_028A48_MSAA_ENABLE(state->multisample) |
528 S_028A48_VPORT_SCISSOR_ENABLE(1) |
529 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
530
531 if (rctx->b.chip_class == CAYMAN) {
532 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
533 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
534 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
535 } else {
536 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
537 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
539 }
540
541 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
542 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
543 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
544 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
545 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
546 S_028814_FACE(!state->front_ccw) |
547 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
548 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
549 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
550 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
551 state->fill_back != PIPE_POLYGON_MODE_FILL) |
552 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
553 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
554 return rs;
555 }
556
evergreen_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)557 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
558 const struct pipe_sampler_state *state)
559 {
560 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
561 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
562 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
563 : state->max_anisotropy;
564 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
565
566 if (!ss) {
567 return NULL;
568 }
569
570 ss->border_color_use = sampler_state_needs_border_color(state);
571
572 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
573 ss->tex_sampler_words[0] =
574 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
575 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
576 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
577 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
578 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
579 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
580 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
581 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
582 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
583 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
584 ss->tex_sampler_words[1] =
585 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
586 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
587 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
588 ss->tex_sampler_words[2] =
589 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
590 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
591 S_03C008_TYPE(1);
592
593 if (ss->border_color_use) {
594 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
595 }
596 return ss;
597 }
598
599 static struct pipe_sampler_view *
texture_buffer_sampler_view(struct r600_context * rctx,struct r600_pipe_sampler_view * view,unsigned width0,unsigned height0)600 texture_buffer_sampler_view(struct r600_context *rctx,
601 struct r600_pipe_sampler_view *view,
602 unsigned width0, unsigned height0)
603
604 {
605 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
606 uint64_t va;
607 int stride = util_format_get_blocksize(view->base.format);
608 unsigned format, num_format, format_comp, endian;
609 unsigned swizzle_res;
610 unsigned char swizzle[4];
611 const struct util_format_description *desc;
612 unsigned offset = view->base.u.buf.offset;
613 unsigned size = view->base.u.buf.size;
614
615 swizzle[0] = view->base.swizzle_r;
616 swizzle[1] = view->base.swizzle_g;
617 swizzle[2] = view->base.swizzle_b;
618 swizzle[3] = view->base.swizzle_a;
619
620 r600_vertex_data_type(view->base.format,
621 &format, &num_format, &format_comp,
622 &endian);
623
624 desc = util_format_description(view->base.format);
625
626 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
627
628 va = tmp->resource.gpu_address + offset;
629 view->tex_resource = &tmp->resource;
630
631 view->skip_mip_address_reloc = true;
632 view->tex_resource_words[0] = va;
633 view->tex_resource_words[1] = size - 1;
634 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
635 S_030008_STRIDE(stride) |
636 S_030008_DATA_FORMAT(format) |
637 S_030008_NUM_FORMAT_ALL(num_format) |
638 S_030008_FORMAT_COMP_ALL(format_comp) |
639 S_030008_ENDIAN_SWAP(endian);
640 view->tex_resource_words[3] = swizzle_res;
641 /*
642 * in theory dword 4 is for number of elements, for use with resinfo,
643 * but it seems to utterly fail to work, the amd gpu shader analyser
644 * uses a const buffer to store the element sizes for buffer txq
645 */
646 view->tex_resource_words[4] = 0;
647 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
648 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
649
650 if (tmp->resource.gpu_address)
651 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
652 return &view->base;
653 }
654
655 struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width0,unsigned height0,unsigned force_level)656 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
657 struct pipe_resource *texture,
658 const struct pipe_sampler_view *state,
659 unsigned width0, unsigned height0,
660 unsigned force_level)
661 {
662 struct r600_context *rctx = (struct r600_context*)ctx;
663 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
664 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
665 struct r600_texture *tmp = (struct r600_texture*)texture;
666 unsigned format, endian;
667 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
668 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
669 unsigned height, depth, width;
670 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
671 enum pipe_format pipe_format = state->format;
672 struct radeon_surf_level *surflevel;
673 unsigned base_level, first_level, last_level;
674 unsigned dim, last_layer;
675 uint64_t va;
676 bool do_endian_swap = FALSE;
677
678 if (!view)
679 return NULL;
680
681 /* initialize base object */
682 view->base = *state;
683 view->base.texture = NULL;
684 pipe_reference(NULL, &texture->reference);
685 view->base.texture = texture;
686 view->base.reference.count = 1;
687 view->base.context = ctx;
688
689 if (state->target == PIPE_BUFFER)
690 return texture_buffer_sampler_view(rctx, view, width0, height0);
691
692 swizzle[0] = state->swizzle_r;
693 swizzle[1] = state->swizzle_g;
694 swizzle[2] = state->swizzle_b;
695 swizzle[3] = state->swizzle_a;
696
697 tile_split = tmp->surface.tile_split;
698 surflevel = tmp->surface.level;
699
700 /* Texturing with separate depth and stencil. */
701 if (tmp->db_compatible) {
702 switch (pipe_format) {
703 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
704 pipe_format = PIPE_FORMAT_Z32_FLOAT;
705 break;
706 case PIPE_FORMAT_X8Z24_UNORM:
707 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
708 /* Z24 is always stored like this for DB
709 * compatibility.
710 */
711 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
712 break;
713 case PIPE_FORMAT_X24S8_UINT:
714 case PIPE_FORMAT_S8X24_UINT:
715 case PIPE_FORMAT_X32_S8X24_UINT:
716 pipe_format = PIPE_FORMAT_S8_UINT;
717 tile_split = tmp->surface.stencil_tile_split;
718 surflevel = tmp->surface.stencil_level;
719 break;
720 default:;
721 }
722 }
723
724 if (R600_BIG_ENDIAN)
725 do_endian_swap = !tmp->db_compatible;
726
727 format = r600_translate_texformat(ctx->screen, pipe_format,
728 swizzle,
729 &word4, &yuv_format, do_endian_swap);
730 assert(format != ~0);
731 if (format == ~0) {
732 FREE(view);
733 return NULL;
734 }
735
736 endian = r600_colorformat_endian_swap(format, do_endian_swap);
737
738 base_level = 0;
739 first_level = state->u.tex.first_level;
740 last_level = state->u.tex.last_level;
741 width = width0;
742 height = height0;
743 depth = texture->depth0;
744
745 if (force_level) {
746 base_level = force_level;
747 first_level = 0;
748 last_level = 0;
749 width = u_minify(width, force_level);
750 height = u_minify(height, force_level);
751 depth = u_minify(depth, force_level);
752 }
753
754 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
755 non_disp_tiling = tmp->non_disp_tiling;
756
757 switch (surflevel[base_level].mode) {
758 default:
759 case RADEON_SURF_MODE_LINEAR_ALIGNED:
760 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
761 break;
762 case RADEON_SURF_MODE_2D:
763 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
764 break;
765 case RADEON_SURF_MODE_1D:
766 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
767 break;
768 }
769 macro_aspect = tmp->surface.mtilea;
770 bankw = tmp->surface.bankw;
771 bankh = tmp->surface.bankh;
772 tile_split = eg_tile_split(tile_split);
773 macro_aspect = eg_macro_tile_aspect(macro_aspect);
774 bankw = eg_bank_wh(bankw);
775 bankh = eg_bank_wh(bankh);
776 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
777
778 /* 128 bit formats require tile type = 1 */
779 if (rscreen->b.chip_class == CAYMAN) {
780 if (util_format_get_blocksize(pipe_format) >= 16)
781 non_disp_tiling = 1;
782 }
783 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
784
785 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
786 height = 1;
787 depth = texture->array_size;
788 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
789 depth = texture->array_size;
790 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
791 depth = texture->array_size / 6;
792
793 va = tmp->resource.gpu_address;
794
795 if (state->format == PIPE_FORMAT_X24S8_UINT ||
796 state->format == PIPE_FORMAT_S8X24_UINT ||
797 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
798 state->format == PIPE_FORMAT_S8_UINT)
799 view->is_stencil_sampler = true;
800
801 view->tex_resource = &tmp->resource;
802
803 /* array type views and views into array types need to use layer offset */
804 dim = state->target;
805 if (state->target != PIPE_TEXTURE_CUBE)
806 dim = MAX2(state->target, texture->target);
807
808 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
809 S_030000_PITCH((pitch / 8) - 1) |
810 S_030000_TEX_WIDTH(width - 1));
811 if (rscreen->b.chip_class == CAYMAN)
812 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
813 else
814 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
815 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
816 S_030004_TEX_DEPTH(depth - 1) |
817 S_030004_ARRAY_MODE(array_mode));
818 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
819
820 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
821 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
822 if (tmp->is_depth) {
823 /* disable FMASK (0 = disabled) */
824 view->tex_resource_words[3] = 0;
825 view->skip_mip_address_reloc = true;
826 } else {
827 /* FMASK should be in MIP_ADDRESS for multisample textures */
828 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
829 }
830 } else if (last_level && texture->nr_samples <= 1) {
831 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
832 } else {
833 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
834 }
835
836 last_layer = state->u.tex.last_layer;
837 if (state->target != texture->target && depth == 1) {
838 last_layer = state->u.tex.first_layer;
839 }
840 view->tex_resource_words[4] = (word4 |
841 S_030010_ENDIAN_SWAP(endian));
842 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
843 S_030014_LAST_ARRAY(last_layer);
844 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
845
846 if (texture->nr_samples > 1) {
847 unsigned log_samples = util_logbase2(texture->nr_samples);
848 if (rscreen->b.chip_class == CAYMAN) {
849 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
850 }
851 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
852 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
853 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
854 } else {
855 bool no_mip = first_level == last_level;
856
857 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
858 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
859 /* aniso max 16 samples */
860 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
861 }
862
863 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
864 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
865 S_03001C_BANK_WIDTH(bankw) |
866 S_03001C_BANK_HEIGHT(bankh) |
867 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
868 S_03001C_NUM_BANKS(nbanks) |
869 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
870 return &view->base;
871 }
872
873 static struct pipe_sampler_view *
evergreen_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * tex,const struct pipe_sampler_view * state)874 evergreen_create_sampler_view(struct pipe_context *ctx,
875 struct pipe_resource *tex,
876 const struct pipe_sampler_view *state)
877 {
878 return evergreen_create_sampler_view_custom(ctx, tex, state,
879 tex->width0, tex->height0, 0);
880 }
881
evergreen_emit_config_state(struct r600_context * rctx,struct r600_atom * atom)882 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
883 {
884 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
885 struct r600_config_state *a = (struct r600_config_state*)atom;
886
887 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
888 if (a->dyn_gpr_enabled) {
889 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
890 radeon_emit(cs, 0);
891 radeon_emit(cs, 0);
892 } else {
893 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
894 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
895 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
896 }
897 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
898 if (a->dyn_gpr_enabled) {
899 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
900 S_028838_PS_GPRS(0x1e) |
901 S_028838_VS_GPRS(0x1e) |
902 S_028838_GS_GPRS(0x1e) |
903 S_028838_ES_GPRS(0x1e) |
904 S_028838_HS_GPRS(0x1e) |
905 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
906 }
907 }
908
evergreen_emit_clip_state(struct r600_context * rctx,struct r600_atom * atom)909 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
910 {
911 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
912 struct pipe_clip_state *state = &rctx->clip_state.state;
913
914 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
915 radeon_emit_array(cs, (unsigned*)state, 6*4);
916 }
917
evergreen_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)918 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
919 const struct pipe_poly_stipple *state)
920 {
921 }
922
evergreen_get_scissor_rect(struct r600_context * rctx,unsigned tl_x,unsigned tl_y,unsigned br_x,unsigned br_y,uint32_t * tl,uint32_t * br)923 static void evergreen_get_scissor_rect(struct r600_context *rctx,
924 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
925 uint32_t *tl, uint32_t *br)
926 {
927 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
928
929 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
930
931 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
932 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
933 }
934
935 /**
936 * This function intializes the CB* register values for RATs. It is meant
937 * to be used for 1D aligned buffers that do not have an associated
938 * radeon_surf.
939 */
evergreen_init_color_surface_rat(struct r600_context * rctx,struct r600_surface * surf)940 void evergreen_init_color_surface_rat(struct r600_context *rctx,
941 struct r600_surface *surf)
942 {
943 struct pipe_resource *pipe_buffer = surf->base.texture;
944 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
945 surf->base.format, FALSE);
946 unsigned endian = r600_colorformat_endian_swap(format, FALSE);
947 unsigned swap = r600_translate_colorswap(surf->base.format, FALSE);
948 unsigned block_size =
949 align(util_format_get_blocksize(pipe_buffer->format), 4);
950 unsigned pitch_alignment =
951 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
952 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
953
954 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
955
956 surf->cb_color_pitch = (pitch / 8) - 1;
957
958 surf->cb_color_slice = 0;
959
960 surf->cb_color_view = 0;
961
962 surf->cb_color_info =
963 S_028C70_ENDIAN(endian)
964 | S_028C70_FORMAT(format)
965 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
966 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
967 | S_028C70_COMP_SWAP(swap)
968 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
969 * are using NUMBER_UINT */
970 | S_028C70_RAT(1)
971 ;
972
973 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
974
975 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
976 * elements. */
977 surf->cb_color_dim = pipe_buffer->width0;
978
979 /* Set the buffer range the GPU will have access to: */
980 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
981 0, pipe_buffer->width0);
982
983 surf->cb_color_fmask = surf->cb_color_base;
984 surf->cb_color_fmask_slice = 0;
985 }
986
evergreen_init_color_surface(struct r600_context * rctx,struct r600_surface * surf)987 void evergreen_init_color_surface(struct r600_context *rctx,
988 struct r600_surface *surf)
989 {
990 struct r600_screen *rscreen = rctx->screen;
991 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
992 unsigned level = surf->base.u.tex.level;
993 unsigned pitch, slice;
994 unsigned color_info, color_attrib, color_dim = 0, color_view;
995 unsigned format, swap, ntype, endian;
996 uint64_t offset, base_offset;
997 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
998 const struct util_format_description *desc;
999 int i;
1000 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1001
1002 offset = rtex->surface.level[level].offset;
1003 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1004 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1005
1006 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1007 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1008 if (slice) {
1009 slice = slice - 1;
1010 }
1011 color_info = 0;
1012 switch (rtex->surface.level[level].mode) {
1013 default:
1014 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1015 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1016 non_disp_tiling = 1;
1017 break;
1018 case RADEON_SURF_MODE_1D:
1019 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1020 non_disp_tiling = rtex->non_disp_tiling;
1021 break;
1022 case RADEON_SURF_MODE_2D:
1023 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1024 non_disp_tiling = rtex->non_disp_tiling;
1025 break;
1026 }
1027 tile_split = rtex->surface.tile_split;
1028 macro_aspect = rtex->surface.mtilea;
1029 bankw = rtex->surface.bankw;
1030 bankh = rtex->surface.bankh;
1031 if (rtex->fmask.size)
1032 fmask_bankh = rtex->fmask.bank_height;
1033 else
1034 fmask_bankh = rtex->surface.bankh;
1035 tile_split = eg_tile_split(tile_split);
1036 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1037 bankw = eg_bank_wh(bankw);
1038 bankh = eg_bank_wh(bankh);
1039 fmask_bankh = eg_bank_wh(fmask_bankh);
1040
1041 /* 128 bit formats require tile type = 1 */
1042 if (rscreen->b.chip_class == CAYMAN) {
1043 if (util_format_get_blocksize(surf->base.format) >= 16)
1044 non_disp_tiling = 1;
1045 }
1046 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1047 desc = util_format_description(surf->base.format);
1048 for (i = 0; i < 4; i++) {
1049 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1050 break;
1051 }
1052 }
1053
1054 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1055 S_028C74_NUM_BANKS(nbanks) |
1056 S_028C74_BANK_WIDTH(bankw) |
1057 S_028C74_BANK_HEIGHT(bankh) |
1058 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1059 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1060 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1061
1062 if (rctx->b.chip_class == CAYMAN) {
1063 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1064 PIPE_SWIZZLE_1);
1065
1066 if (rtex->resource.b.b.nr_samples > 1) {
1067 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1068 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1069 S_028C74_NUM_FRAGMENTS(log_samples);
1070 }
1071 }
1072
1073 ntype = V_028C70_NUMBER_UNORM;
1074 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1075 ntype = V_028C70_NUMBER_SRGB;
1076 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1077 if (desc->channel[i].normalized)
1078 ntype = V_028C70_NUMBER_SNORM;
1079 else if (desc->channel[i].pure_integer)
1080 ntype = V_028C70_NUMBER_SINT;
1081 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1082 if (desc->channel[i].normalized)
1083 ntype = V_028C70_NUMBER_UNORM;
1084 else if (desc->channel[i].pure_integer)
1085 ntype = V_028C70_NUMBER_UINT;
1086 }
1087
1088 if (R600_BIG_ENDIAN)
1089 do_endian_swap = !rtex->db_compatible;
1090
1091 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
1092 do_endian_swap);
1093 assert(format != ~0);
1094
1095 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
1096 assert(swap != ~0);
1097
1098 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1099
1100 /* blend clamp should be set for all NORM/SRGB types */
1101 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1102 ntype == V_028C70_NUMBER_SRGB)
1103 blend_clamp = 1;
1104
1105 /* set blend bypass according to docs if SINT/UINT or
1106 8/24 COLOR variants */
1107 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1108 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1109 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1110 blend_clamp = 0;
1111 blend_bypass = 1;
1112 }
1113
1114 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1115
1116 color_info |= S_028C70_FORMAT(format) |
1117 S_028C70_COMP_SWAP(swap) |
1118 S_028C70_BLEND_CLAMP(blend_clamp) |
1119 S_028C70_BLEND_BYPASS(blend_bypass) |
1120 S_028C70_NUMBER_TYPE(ntype) |
1121 S_028C70_ENDIAN(endian);
1122
1123 /* EXPORT_NORM is an optimzation that can be enabled for better
1124 * performance in certain cases.
1125 * EXPORT_NORM can be enabled if:
1126 * - 11-bit or smaller UNORM/SNORM/SRGB
1127 * - 16-bit or smaller FLOAT
1128 */
1129 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1130 ((desc->channel[i].size < 12 &&
1131 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1132 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1133 (desc->channel[i].size < 17 &&
1134 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1135 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1136 surf->export_16bpc = true;
1137 }
1138
1139 if (rtex->fmask.size) {
1140 color_info |= S_028C70_COMPRESSION(1);
1141 }
1142
1143 base_offset = rtex->resource.gpu_address;
1144
1145 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1146 surf->cb_color_base = (base_offset + offset) >> 8;
1147 surf->cb_color_dim = color_dim;
1148 surf->cb_color_info = color_info;
1149 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1150 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1151 surf->cb_color_view = color_view;
1152 surf->cb_color_attrib = color_attrib;
1153 if (rtex->fmask.size) {
1154 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1155 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1156 } else {
1157 surf->cb_color_fmask = surf->cb_color_base;
1158 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1159 }
1160
1161 surf->color_initialized = true;
1162 }
1163
evergreen_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1164 static void evergreen_init_depth_surface(struct r600_context *rctx,
1165 struct r600_surface *surf)
1166 {
1167 struct r600_screen *rscreen = rctx->screen;
1168 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1169 unsigned level = surf->base.u.tex.level;
1170 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1171 uint64_t offset;
1172 unsigned format, array_mode;
1173 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1174
1175
1176 format = r600_translate_dbformat(surf->base.format);
1177 assert(format != ~0);
1178
1179 offset = rtex->resource.gpu_address;
1180 offset += rtex->surface.level[level].offset;
1181
1182 switch (rtex->surface.level[level].mode) {
1183 case RADEON_SURF_MODE_2D:
1184 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1185 break;
1186 case RADEON_SURF_MODE_1D:
1187 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1188 default:
1189 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1190 break;
1191 }
1192 tile_split = rtex->surface.tile_split;
1193 macro_aspect = rtex->surface.mtilea;
1194 bankw = rtex->surface.bankw;
1195 bankh = rtex->surface.bankh;
1196 tile_split = eg_tile_split(tile_split);
1197 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1198 bankw = eg_bank_wh(bankw);
1199 bankh = eg_bank_wh(bankh);
1200 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1201 offset >>= 8;
1202
1203 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1204 S_028040_FORMAT(format) |
1205 S_028040_TILE_SPLIT(tile_split)|
1206 S_028040_NUM_BANKS(nbanks) |
1207 S_028040_BANK_WIDTH(bankw) |
1208 S_028040_BANK_HEIGHT(bankh) |
1209 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1210 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1211 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1212 }
1213
1214 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1215
1216 surf->db_depth_base = offset;
1217 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1218 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1219 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1220 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1221 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1222 levelinfo->nblk_y / 64 - 1);
1223
1224 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1225 uint64_t stencil_offset;
1226 unsigned stile_split = rtex->surface.stencil_tile_split;
1227
1228 stile_split = eg_tile_split(stile_split);
1229
1230 stencil_offset = rtex->surface.stencil_level[level].offset;
1231 stencil_offset += rtex->resource.gpu_address;
1232
1233 surf->db_stencil_base = stencil_offset >> 8;
1234 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1235 S_028044_TILE_SPLIT(stile_split);
1236 } else {
1237 surf->db_stencil_base = offset;
1238 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1239 * Older kernels are out of luck. */
1240 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1241 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1242 S_028044_FORMAT(V_028044_STENCIL_8);
1243 }
1244
1245 /* use htile only for first level */
1246 if (rtex->htile_buffer && !level) {
1247 uint64_t va = rtex->htile_buffer->gpu_address;
1248 surf->db_htile_data_base = va >> 8;
1249 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1250 S_028ABC_HTILE_HEIGHT(1) |
1251 S_028ABC_FULL_CACHE(1);
1252 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1253 surf->db_preload_control = 0;
1254 }
1255
1256 surf->depth_initialized = true;
1257 }
1258
evergreen_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1259 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1260 const struct pipe_framebuffer_state *state)
1261 {
1262 struct r600_context *rctx = (struct r600_context *)ctx;
1263 struct r600_surface *surf;
1264 struct r600_texture *rtex;
1265 uint32_t i, log_samples;
1266
1267 /* Flush TC when changing the framebuffer state, because the only
1268 * client not using TC that can change textures is the framebuffer.
1269 * Other places don't typically have to flush TC.
1270 */
1271 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1272 R600_CONTEXT_FLUSH_AND_INV |
1273 R600_CONTEXT_FLUSH_AND_INV_CB |
1274 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1275 R600_CONTEXT_FLUSH_AND_INV_DB |
1276 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1277 R600_CONTEXT_INV_TEX_CACHE;
1278
1279 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1280
1281 /* Colorbuffers. */
1282 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1283 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1284 util_format_is_pure_integer(state->cbufs[0]->format);
1285 rctx->framebuffer.compressed_cb_mask = 0;
1286 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1287
1288 for (i = 0; i < state->nr_cbufs; i++) {
1289 surf = (struct r600_surface*)state->cbufs[i];
1290 if (!surf)
1291 continue;
1292
1293 rtex = (struct r600_texture*)surf->base.texture;
1294
1295 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1296
1297 if (!surf->color_initialized) {
1298 evergreen_init_color_surface(rctx, surf);
1299 }
1300
1301 if (!surf->export_16bpc) {
1302 rctx->framebuffer.export_16bpc = false;
1303 }
1304
1305 if (rtex->fmask.size) {
1306 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1307 }
1308 }
1309
1310 /* Update alpha-test state dependencies.
1311 * Alpha-test is done on the first colorbuffer only. */
1312 if (state->nr_cbufs) {
1313 bool alphatest_bypass = false;
1314 bool export_16bpc = true;
1315
1316 surf = (struct r600_surface*)state->cbufs[0];
1317 if (surf) {
1318 alphatest_bypass = surf->alphatest_bypass;
1319 export_16bpc = surf->export_16bpc;
1320 }
1321
1322 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1323 rctx->alphatest_state.bypass = alphatest_bypass;
1324 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1325 }
1326 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1327 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1328 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1329 }
1330 }
1331
1332 /* ZS buffer. */
1333 if (state->zsbuf) {
1334 surf = (struct r600_surface*)state->zsbuf;
1335
1336 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1337
1338 if (!surf->depth_initialized) {
1339 evergreen_init_depth_surface(rctx, surf);
1340 }
1341
1342 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1343 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1344 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1345 }
1346
1347 if (rctx->db_state.rsurf != surf) {
1348 rctx->db_state.rsurf = surf;
1349 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1350 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1351 }
1352 } else if (rctx->db_state.rsurf) {
1353 rctx->db_state.rsurf = NULL;
1354 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1355 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1356 }
1357
1358 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1359 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1360 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1361 }
1362
1363 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1364 rctx->alphatest_state.bypass = false;
1365 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1366 }
1367
1368 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1369 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1370 if ((rctx->b.chip_class == CAYMAN ||
1371 rctx->b.family == CHIP_RV770) &&
1372 rctx->db_misc_state.log_samples != log_samples) {
1373 rctx->db_misc_state.log_samples = log_samples;
1374 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1375 }
1376
1377
1378 /* Calculate the CS size. */
1379 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1380
1381 /* MSAA. */
1382 if (rctx->b.chip_class == EVERGREEN)
1383 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1384 else
1385 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1386
1387 /* Colorbuffers. */
1388 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1389 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1390 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1391
1392 /* ZS buffer. */
1393 if (state->zsbuf) {
1394 rctx->framebuffer.atom.num_dw += 24;
1395 rctx->framebuffer.atom.num_dw += 2;
1396 } else if (rctx->screen->b.info.drm_minor >= 18) {
1397 rctx->framebuffer.atom.num_dw += 4;
1398 }
1399
1400 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1401
1402 r600_set_sample_locations_constant_buffer(rctx);
1403 }
1404
evergreen_set_min_samples(struct pipe_context * ctx,unsigned min_samples)1405 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1406 {
1407 struct r600_context *rctx = (struct r600_context *)ctx;
1408
1409 if (rctx->ps_iter_samples == min_samples)
1410 return;
1411
1412 rctx->ps_iter_samples = min_samples;
1413 if (rctx->framebuffer.nr_samples > 1) {
1414 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1415 }
1416 }
1417
1418 /* 8xMSAA */
1419 static uint32_t sample_locs_8x[] = {
1420 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1421 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1422 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1423 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1424 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1425 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1426 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1427 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1428 };
1429 static unsigned max_dist_8x = 7;
1430
evergreen_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)1431 static void evergreen_get_sample_position(struct pipe_context *ctx,
1432 unsigned sample_count,
1433 unsigned sample_index,
1434 float *out_value)
1435 {
1436 int offset, index;
1437 struct {
1438 int idx:4;
1439 } val;
1440 switch (sample_count) {
1441 case 1:
1442 default:
1443 out_value[0] = out_value[1] = 0.5;
1444 break;
1445 case 2:
1446 offset = 4 * (sample_index * 2);
1447 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1448 out_value[0] = (float)(val.idx + 8) / 16.0f;
1449 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1450 out_value[1] = (float)(val.idx + 8) / 16.0f;
1451 break;
1452 case 4:
1453 offset = 4 * (sample_index * 2);
1454 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1455 out_value[0] = (float)(val.idx + 8) / 16.0f;
1456 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1457 out_value[1] = (float)(val.idx + 8) / 16.0f;
1458 break;
1459 case 8:
1460 offset = 4 * (sample_index % 4 * 2);
1461 index = (sample_index / 4);
1462 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1463 out_value[0] = (float)(val.idx + 8) / 16.0f;
1464 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1465 out_value[1] = (float)(val.idx + 8) / 16.0f;
1466 break;
1467 }
1468 }
1469
evergreen_emit_msaa_state(struct r600_context * rctx,int nr_samples,int ps_iter_samples)1470 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1471 {
1472
1473 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1474 unsigned max_dist = 0;
1475
1476 switch (nr_samples) {
1477 default:
1478 nr_samples = 0;
1479 break;
1480 case 2:
1481 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1482 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1483 max_dist = eg_max_dist_2x;
1484 break;
1485 case 4:
1486 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1487 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1488 max_dist = eg_max_dist_4x;
1489 break;
1490 case 8:
1491 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1492 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1493 max_dist = max_dist_8x;
1494 break;
1495 }
1496
1497 if (nr_samples > 1) {
1498 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1499 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1500 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1501 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1502 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1503 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1504 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1505 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1506 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1507 } else {
1508 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1509 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1510 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1511 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1512 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1513 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1514 }
1515 }
1516
evergreen_emit_framebuffer_state(struct r600_context * rctx,struct r600_atom * atom)1517 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1518 {
1519 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1520 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1521 unsigned nr_cbufs = state->nr_cbufs;
1522 unsigned i, tl, br;
1523 struct r600_texture *tex = NULL;
1524 struct r600_surface *cb = NULL;
1525
1526 /* XXX support more colorbuffers once we need them */
1527 assert(nr_cbufs <= 8);
1528 if (nr_cbufs > 8)
1529 nr_cbufs = 8;
1530
1531 /* Colorbuffers. */
1532 for (i = 0; i < nr_cbufs; i++) {
1533 unsigned reloc, cmask_reloc;
1534
1535 cb = (struct r600_surface*)state->cbufs[i];
1536 if (!cb) {
1537 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1538 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1539 continue;
1540 }
1541
1542 tex = (struct r600_texture *)cb->base.texture;
1543 reloc = radeon_add_to_buffer_list(&rctx->b,
1544 &rctx->b.gfx,
1545 (struct r600_resource*)cb->base.texture,
1546 RADEON_USAGE_READWRITE,
1547 tex->resource.b.b.nr_samples > 1 ?
1548 RADEON_PRIO_COLOR_BUFFER_MSAA :
1549 RADEON_PRIO_COLOR_BUFFER);
1550
1551 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1552 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1553 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1554 RADEON_PRIO_CMASK);
1555 } else {
1556 cmask_reloc = reloc;
1557 }
1558
1559 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1560 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1561 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1562 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1563 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1564 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1565 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1566 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1567 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1568 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1569 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1570 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1571 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1572 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1573
1574 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1575 radeon_emit(cs, reloc);
1576
1577 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1578 radeon_emit(cs, reloc);
1579
1580 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1581 radeon_emit(cs, cmask_reloc);
1582
1583 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1584 radeon_emit(cs, reloc);
1585 }
1586 /* set CB_COLOR1_INFO for possible dual-src blending */
1587 if (i == 1 && state->cbufs[0]) {
1588 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1589 cb->cb_color_info | tex->cb_color_info);
1590 i++;
1591 }
1592 for (; i < 8 ; i++)
1593 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1594 for (; i < 12; i++)
1595 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1596
1597 /* ZS buffer. */
1598 if (state->zsbuf) {
1599 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1600 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1601 &rctx->b.gfx,
1602 (struct r600_resource*)state->zsbuf->texture,
1603 RADEON_USAGE_READWRITE,
1604 zb->base.texture->nr_samples > 1 ?
1605 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1606 RADEON_PRIO_DEPTH_BUFFER);
1607
1608 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1609
1610 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1611 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1612 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1613 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1614 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1615 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1616 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1617 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1618 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1619
1620 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1621 radeon_emit(cs, reloc);
1622
1623 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1624 radeon_emit(cs, reloc);
1625
1626 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1627 radeon_emit(cs, reloc);
1628
1629 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1630 radeon_emit(cs, reloc);
1631 } else if (rctx->screen->b.info.drm_minor >= 18) {
1632 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1633 * Older kernels are out of luck. */
1634 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1635 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1636 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1637 }
1638
1639 /* Framebuffer dimensions. */
1640 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1641
1642 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1643 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1644 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1645
1646 if (rctx->b.chip_class == EVERGREEN) {
1647 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1648 } else {
1649 unsigned sc_mode_cntl_1 =
1650 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1651 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1652
1653 if (rctx->framebuffer.nr_samples > 1)
1654 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1655 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1656 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1657 }
1658 }
1659
evergreen_emit_polygon_offset(struct r600_context * rctx,struct r600_atom * a)1660 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1661 {
1662 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1663 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1664 float offset_units = state->offset_units;
1665 float offset_scale = state->offset_scale;
1666 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1667
1668 if (!state->offset_units_unscaled) {
1669 switch (state->zs_format) {
1670 case PIPE_FORMAT_Z24X8_UNORM:
1671 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1672 case PIPE_FORMAT_X8Z24_UNORM:
1673 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1674 offset_units *= 2.0f;
1675 pa_su_poly_offset_db_fmt_cntl =
1676 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1677 break;
1678 case PIPE_FORMAT_Z16_UNORM:
1679 offset_units *= 4.0f;
1680 pa_su_poly_offset_db_fmt_cntl =
1681 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1682 break;
1683 default:
1684 pa_su_poly_offset_db_fmt_cntl =
1685 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1686 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1687 }
1688 }
1689
1690 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1691 radeon_emit(cs, fui(offset_scale));
1692 radeon_emit(cs, fui(offset_units));
1693 radeon_emit(cs, fui(offset_scale));
1694 radeon_emit(cs, fui(offset_units));
1695
1696 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1697 pa_su_poly_offset_db_fmt_cntl);
1698 }
1699
evergreen_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)1700 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1701 {
1702 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1703 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1704 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1705 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1706
1707 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1708 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1709 /* This must match the used export instructions exactly.
1710 * Other values may lead to undefined behavior and hangs.
1711 */
1712 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1713 }
1714
evergreen_emit_db_state(struct r600_context * rctx,struct r600_atom * atom)1715 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1716 {
1717 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1718 struct r600_db_state *a = (struct r600_db_state*)atom;
1719
1720 if (a->rsurf && a->rsurf->db_htile_surface) {
1721 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1722 unsigned reloc_idx;
1723
1724 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1725 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1726 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1727 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1728 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1729 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1730 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1731 radeon_emit(cs, reloc_idx);
1732 } else {
1733 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1734 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1735 }
1736 }
1737
evergreen_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)1738 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1739 {
1740 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1741 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1742 unsigned db_render_control = 0;
1743 unsigned db_count_control = 0;
1744 unsigned db_render_override =
1745 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1746 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1747
1748 if (rctx->b.num_occlusion_queries > 0 &&
1749 !a->occlusion_queries_disabled) {
1750 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1751 if (rctx->b.chip_class == CAYMAN) {
1752 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1753 }
1754 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1755 } else {
1756 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1757 }
1758
1759 /* This is to fix a lockup when hyperz and alpha test are enabled at
1760 * the same time somehow GPU get confuse on which order to pick for
1761 * z test
1762 */
1763 if (rctx->alphatest_state.sx_alpha_test_control)
1764 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1765
1766 if (a->flush_depthstencil_through_cb) {
1767 assert(a->copy_depth || a->copy_stencil);
1768
1769 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1770 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1771 S_028000_COPY_CENTROID(1) |
1772 S_028000_COPY_SAMPLE(a->copy_sample);
1773 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1774 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1775 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1776 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1777 }
1778 if (a->htile_clear) {
1779 /* FIXME we might want to disable cliprect here */
1780 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1781 }
1782
1783 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1784 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1785 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1786 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1787 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1788 }
1789
evergreen_emit_vertex_buffers(struct r600_context * rctx,struct r600_vertexbuf_state * state,unsigned resource_offset,unsigned pkt_flags)1790 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1791 struct r600_vertexbuf_state *state,
1792 unsigned resource_offset,
1793 unsigned pkt_flags)
1794 {
1795 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1796 uint32_t dirty_mask = state->dirty_mask;
1797
1798 while (dirty_mask) {
1799 struct pipe_vertex_buffer *vb;
1800 struct r600_resource *rbuffer;
1801 uint64_t va;
1802 unsigned buffer_index = u_bit_scan(&dirty_mask);
1803
1804 vb = &state->vb[buffer_index];
1805 rbuffer = (struct r600_resource*)vb->buffer;
1806 assert(rbuffer);
1807
1808 va = rbuffer->gpu_address + vb->buffer_offset;
1809
1810 /* fetch resources start at index 992 */
1811 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1812 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1813 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1814 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1815 radeon_emit(cs, /* RESOURCEi_WORD2 */
1816 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1817 S_030008_STRIDE(vb->stride) |
1818 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1819 radeon_emit(cs, /* RESOURCEi_WORD3 */
1820 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1821 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1822 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1823 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1824 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1825 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1826 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1827 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1828
1829 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1830 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1831 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1832 }
1833 state->dirty_mask = 0;
1834 }
1835
evergreen_fs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1836 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1837 {
1838 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1839 }
1840
evergreen_cs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1841 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1842 {
1843 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1844 RADEON_CP_PACKET3_COMPUTE_MODE);
1845 }
1846
evergreen_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache,unsigned pkt_flags)1847 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1848 struct r600_constbuf_state *state,
1849 unsigned buffer_id_base,
1850 unsigned reg_alu_constbuf_size,
1851 unsigned reg_alu_const_cache,
1852 unsigned pkt_flags)
1853 {
1854 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1855 uint32_t dirty_mask = state->dirty_mask;
1856
1857 while (dirty_mask) {
1858 struct pipe_constant_buffer *cb;
1859 struct r600_resource *rbuffer;
1860 uint64_t va;
1861 unsigned buffer_index = ffs(dirty_mask) - 1;
1862 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1863
1864 cb = &state->cb[buffer_index];
1865 rbuffer = (struct r600_resource*)cb->buffer;
1866 assert(rbuffer);
1867
1868 va = rbuffer->gpu_address + cb->buffer_offset;
1869
1870 if (!gs_ring_buffer) {
1871 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1872 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1873 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1874 pkt_flags);
1875 }
1876
1877 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1878 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1879 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1880
1881 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1882 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1883 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1884 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1885 radeon_emit(cs, /* RESOURCEi_WORD2 */
1886 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1887 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1888 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1889 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1890 radeon_emit(cs, /* RESOURCEi_WORD3 */
1891 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1892 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1893 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1894 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1895 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1896 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1897 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1898 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1899 radeon_emit(cs, /* RESOURCEi_WORD7 */
1900 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1901
1902 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1903 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1904 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1905
1906 dirty_mask &= ~(1 << buffer_index);
1907 }
1908 state->dirty_mask = 0;
1909 }
1910
1911 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
evergreen_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1912 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1913 {
1914 if (rctx->vs_shader->current->shader.vs_as_ls) {
1915 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1916 EG_FETCH_CONSTANTS_OFFSET_LS,
1917 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1918 R_028F40_ALU_CONST_CACHE_LS_0,
1919 0 /* PKT3 flags */);
1920 } else {
1921 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1922 EG_FETCH_CONSTANTS_OFFSET_VS,
1923 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1924 R_028980_ALU_CONST_CACHE_VS_0,
1925 0 /* PKT3 flags */);
1926 }
1927 }
1928
evergreen_emit_gs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1929 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1930 {
1931 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1932 EG_FETCH_CONSTANTS_OFFSET_GS,
1933 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1934 R_0289C0_ALU_CONST_CACHE_GS_0,
1935 0 /* PKT3 flags */);
1936 }
1937
evergreen_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1938 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1939 {
1940 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1941 EG_FETCH_CONSTANTS_OFFSET_PS,
1942 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1943 R_028940_ALU_CONST_CACHE_PS_0,
1944 0 /* PKT3 flags */);
1945 }
1946
evergreen_emit_cs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1947 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1948 {
1949 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1950 EG_FETCH_CONSTANTS_OFFSET_CS,
1951 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1952 R_028F40_ALU_CONST_CACHE_LS_0,
1953 RADEON_CP_PACKET3_COMPUTE_MODE);
1954 }
1955
1956 /* tes constants can be emitted to VS or ES - which are common */
evergreen_emit_tes_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1957 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1958 {
1959 if (!rctx->tes_shader)
1960 return;
1961 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
1962 EG_FETCH_CONSTANTS_OFFSET_VS,
1963 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1964 R_028980_ALU_CONST_CACHE_VS_0,
1965 0);
1966 }
1967
evergreen_emit_tcs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1968 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1969 {
1970 if (!rctx->tes_shader)
1971 return;
1972 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
1973 EG_FETCH_CONSTANTS_OFFSET_HS,
1974 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
1975 R_028F00_ALU_CONST_CACHE_HS_0,
1976 0);
1977 }
1978
evergreen_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base,unsigned pkt_flags)1979 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1980 struct r600_samplerview_state *state,
1981 unsigned resource_id_base, unsigned pkt_flags)
1982 {
1983 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1984 uint32_t dirty_mask = state->dirty_mask;
1985
1986 while (dirty_mask) {
1987 struct r600_pipe_sampler_view *rview;
1988 unsigned resource_index = u_bit_scan(&dirty_mask);
1989 unsigned reloc;
1990
1991 rview = state->views[resource_index];
1992 assert(rview);
1993
1994 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1995 radeon_emit(cs, (resource_id_base + resource_index) * 8);
1996 radeon_emit_array(cs, rview->tex_resource_words, 8);
1997
1998 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1999 RADEON_USAGE_READ,
2000 r600_get_sampler_view_priority(rview->tex_resource));
2001 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2002 radeon_emit(cs, reloc);
2003
2004 if (!rview->skip_mip_address_reloc) {
2005 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2006 radeon_emit(cs, reloc);
2007 }
2008 }
2009 state->dirty_mask = 0;
2010 }
2011
evergreen_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2012 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2013 {
2014 if (rctx->vs_shader->current->shader.vs_as_ls) {
2015 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2016 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2017 } else {
2018 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2019 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2020 }
2021 }
2022
evergreen_emit_gs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2023 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2024 {
2025 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2026 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2027 }
2028
evergreen_emit_tcs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2029 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2030 {
2031 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2032 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2033 }
2034
evergreen_emit_tes_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2035 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2036 {
2037 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2038 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2039 }
2040
evergreen_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2041 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2042 {
2043 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2044 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2045 }
2046
evergreen_emit_cs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2047 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2048 {
2049 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2050 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2051 }
2052
evergreen_emit_sampler_states(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_index_reg,unsigned pkt_flags)2053 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2054 struct r600_textures_info *texinfo,
2055 unsigned resource_id_base,
2056 unsigned border_index_reg,
2057 unsigned pkt_flags)
2058 {
2059 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2060 uint32_t dirty_mask = texinfo->states.dirty_mask;
2061
2062 while (dirty_mask) {
2063 struct r600_pipe_sampler_state *rstate;
2064 unsigned i = u_bit_scan(&dirty_mask);
2065
2066 rstate = texinfo->states.states[i];
2067 assert(rstate);
2068
2069 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2070 radeon_emit(cs, (resource_id_base + i) * 3);
2071 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2072
2073 if (rstate->border_color_use) {
2074 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2075 radeon_emit(cs, i);
2076 radeon_emit_array(cs, rstate->border_color.ui, 4);
2077 }
2078 }
2079 texinfo->states.dirty_mask = 0;
2080 }
2081
evergreen_emit_vs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2082 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2083 {
2084 if (rctx->vs_shader->current->shader.vs_as_ls) {
2085 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2086 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2087 } else {
2088 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2089 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2090 }
2091 }
2092
evergreen_emit_gs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2093 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2094 {
2095 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2096 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2097 }
2098
evergreen_emit_tcs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2099 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2100 {
2101 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2102 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2103 }
2104
evergreen_emit_tes_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2105 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2106 {
2107 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2108 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2109 }
2110
evergreen_emit_ps_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2111 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2112 {
2113 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2114 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2115 }
2116
evergreen_emit_cs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2117 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2118 {
2119 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2120 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2121 RADEON_CP_PACKET3_COMPUTE_MODE);
2122 }
2123
evergreen_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2124 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2125 {
2126 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2127 uint8_t mask = s->sample_mask;
2128
2129 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2130 mask | (mask << 8) | (mask << 16) | (mask << 24));
2131 }
2132
cayman_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2133 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2134 {
2135 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2136 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2137 uint16_t mask = s->sample_mask;
2138
2139 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2140 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2141 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2142 }
2143
evergreen_emit_vertex_fetch_shader(struct r600_context * rctx,struct r600_atom * a)2144 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2145 {
2146 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2147 struct r600_cso_state *state = (struct r600_cso_state*)a;
2148 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2149
2150 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2151 (shader->buffer->gpu_address + shader->offset) >> 8);
2152 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2153 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2154 RADEON_USAGE_READ,
2155 RADEON_PRIO_SHADER_BINARY));
2156 }
2157
evergreen_emit_shader_stages(struct r600_context * rctx,struct r600_atom * a)2158 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2159 {
2160 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2161 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2162
2163 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2164
2165 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2166 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2167 primid = 1;
2168 }
2169
2170 if (state->geom_enable) {
2171 uint32_t cut_val;
2172
2173 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2174 cut_val = V_028A40_GS_CUT_128;
2175 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2176 cut_val = V_028A40_GS_CUT_256;
2177 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2178 cut_val = V_028A40_GS_CUT_512;
2179 else
2180 cut_val = V_028A40_GS_CUT_1024;
2181
2182 v = S_028B54_GS_EN(1) |
2183 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2184 if (!rctx->tes_shader)
2185 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2186
2187 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2188 S_028A40_CUT_MODE(cut_val);
2189
2190 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2191 primid = 1;
2192 }
2193
2194 if (rctx->tes_shader) {
2195 uint32_t type, partitioning, topology;
2196 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2197 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2198 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2199 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2200 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2201 switch (tes_prim_mode) {
2202 case PIPE_PRIM_LINES:
2203 type = V_028B6C_TESS_ISOLINE;
2204 break;
2205 case PIPE_PRIM_TRIANGLES:
2206 type = V_028B6C_TESS_TRIANGLE;
2207 break;
2208 case PIPE_PRIM_QUADS:
2209 type = V_028B6C_TESS_QUAD;
2210 break;
2211 default:
2212 assert(0);
2213 return;
2214 }
2215
2216 switch (tes_spacing) {
2217 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2218 partitioning = V_028B6C_PART_FRAC_ODD;
2219 break;
2220 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2221 partitioning = V_028B6C_PART_FRAC_EVEN;
2222 break;
2223 case PIPE_TESS_SPACING_EQUAL:
2224 partitioning = V_028B6C_PART_INTEGER;
2225 break;
2226 default:
2227 assert(0);
2228 return;
2229 }
2230
2231 if (tes_point_mode)
2232 topology = V_028B6C_OUTPUT_POINT;
2233 else if (tes_prim_mode == PIPE_PRIM_LINES)
2234 topology = V_028B6C_OUTPUT_LINE;
2235 else if (tes_vertex_order_cw)
2236 /* XXX follow radeonsi and invert */
2237 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2238 else
2239 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2240
2241 tf_param = S_028B6C_TYPE(type) |
2242 S_028B6C_PARTITIONING(partitioning) |
2243 S_028B6C_TOPOLOGY(topology);
2244 }
2245
2246 if (rctx->tes_shader) {
2247 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2248 S_028B54_HS_EN(1);
2249 if (!state->geom_enable)
2250 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2251 else
2252 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2253 }
2254
2255 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2256 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2257 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2258 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2259 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2260 }
2261
evergreen_emit_gs_rings(struct r600_context * rctx,struct r600_atom * a)2262 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2263 {
2264 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2265 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2266 struct r600_resource *rbuffer;
2267
2268 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2269 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2270 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2271
2272 if (state->enable) {
2273 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2274 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2275 rbuffer->gpu_address >> 8);
2276 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2277 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2278 RADEON_USAGE_READWRITE,
2279 RADEON_PRIO_SHADER_RINGS));
2280 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2281 state->esgs_ring.buffer_size >> 8);
2282
2283 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2284 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2285 rbuffer->gpu_address >> 8);
2286 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2287 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2288 RADEON_USAGE_READWRITE,
2289 RADEON_PRIO_SHADER_RINGS));
2290 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2291 state->gsvs_ring.buffer_size >> 8);
2292 } else {
2293 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2294 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2295 }
2296
2297 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2298 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2299 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2300 }
2301
cayman_init_common_regs(struct r600_command_buffer * cb,enum chip_class ctx_chip_class,enum radeon_family ctx_family,int ctx_drm_minor)2302 void cayman_init_common_regs(struct r600_command_buffer *cb,
2303 enum chip_class ctx_chip_class,
2304 enum radeon_family ctx_family,
2305 int ctx_drm_minor)
2306 {
2307 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2308 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2309 /* always set the temp clauses */
2310 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2311
2312 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2313 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2314 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2315
2316 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2317
2318 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2321
2322 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2323 }
2324
cayman_init_atom_start_cs(struct r600_context * rctx)2325 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2326 {
2327 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2328 int i;
2329
2330 r600_init_command_buffer(cb, 338);
2331
2332 /* This must be first. */
2333 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2334 r600_store_value(cb, 0x80000000);
2335 r600_store_value(cb, 0x80000000);
2336
2337 /* We're setting config registers here. */
2338 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2339 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2340
2341 /* This enables pipeline stat & streamout queries.
2342 * They are only disabled by blits.
2343 */
2344 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2345 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2346
2347 cayman_init_common_regs(cb, rctx->b.chip_class,
2348 rctx->b.family, rctx->screen->b.info.drm_minor);
2349
2350 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2351 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2352
2353 /* remove LS/HS from one SIMD for hw workaround */
2354 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2355 r600_store_value(cb, 0xffffffff);
2356 r600_store_value(cb, 0xffffffff);
2357 r600_store_value(cb, 0xfffffffe);
2358
2359 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2360 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2361 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2362 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2363 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2364 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2365 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2366
2367 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2368 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2369 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2370 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2371 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2372
2373 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2374 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2375 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2376 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2377 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2378 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2379 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2380 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2381 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2382 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2383 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2384 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2385 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2386 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2387
2388 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2389
2390 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2391
2392 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2393 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2394 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2395
2396 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2397 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2398 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2399
2400 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2401
2402 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2403 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2404 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2405
2406 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2407
2408 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2409
2410 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2411
2412 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2413 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2414 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2415 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2416
2417 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2418 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2419
2420 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2421 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2422
2423 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2424 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2425 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2426
2427 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2428 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2429 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2430
2431 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2432 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2433 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2434 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2435 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2436 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2437
2438 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2439
2440 /* to avoid GPU doing any preloading of constant from random address */
2441 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2442 for (i = 0; i < 16; i++)
2443 r600_store_value(cb, 0);
2444
2445 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2446 for (i = 0; i < 16; i++)
2447 r600_store_value(cb, 0);
2448
2449 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2450 for (i = 0; i < 16; i++)
2451 r600_store_value(cb, 0);
2452
2453 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2454 for (i = 0; i < 16; i++)
2455 r600_store_value(cb, 0);
2456
2457 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2458 for (i = 0; i < 16; i++)
2459 r600_store_value(cb, 0);
2460
2461 if (rctx->screen->b.has_streamout) {
2462 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2463 }
2464
2465 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2466 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2467 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2468 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2469 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2470 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2471
2472 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2473 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2474 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2475 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2476 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2477 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2478 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2479 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2480 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2481 }
2482
evergreen_init_common_regs(struct r600_context * rctx,struct r600_command_buffer * cb,enum chip_class ctx_chip_class,enum radeon_family ctx_family,int ctx_drm_minor)2483 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2484 enum chip_class ctx_chip_class,
2485 enum radeon_family ctx_family,
2486 int ctx_drm_minor)
2487 {
2488 int ps_prio;
2489 int vs_prio;
2490 int gs_prio;
2491 int es_prio;
2492
2493 int hs_prio;
2494 int cs_prio;
2495 int ls_prio;
2496
2497 unsigned tmp;
2498
2499 ps_prio = 0;
2500 vs_prio = 1;
2501 gs_prio = 2;
2502 es_prio = 3;
2503 hs_prio = 3;
2504 ls_prio = 3;
2505 cs_prio = 0;
2506
2507 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2508 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2509 rctx->r6xx_num_clause_temp_gprs = 4;
2510 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2511 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2512 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2513 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2514
2515 tmp = 0;
2516 switch (ctx_family) {
2517 case CHIP_CEDAR:
2518 case CHIP_PALM:
2519 case CHIP_SUMO:
2520 case CHIP_SUMO2:
2521 case CHIP_CAICOS:
2522 break;
2523 default:
2524 tmp |= S_008C00_VC_ENABLE(1);
2525 break;
2526 }
2527 tmp |= S_008C00_EXPORT_SRC_C(1);
2528 tmp |= S_008C00_CS_PRIO(cs_prio);
2529 tmp |= S_008C00_LS_PRIO(ls_prio);
2530 tmp |= S_008C00_HS_PRIO(hs_prio);
2531 tmp |= S_008C00_PS_PRIO(ps_prio);
2532 tmp |= S_008C00_VS_PRIO(vs_prio);
2533 tmp |= S_008C00_GS_PRIO(gs_prio);
2534 tmp |= S_008C00_ES_PRIO(es_prio);
2535
2536 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2537 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2538
2539 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2540 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2541 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2542
2543 /* The cs checker requires this register to be set. */
2544 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2545
2546 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2547 r600_store_value(cb, 0);
2548 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2549
2550 return;
2551 }
2552
evergreen_init_atom_start_cs(struct r600_context * rctx)2553 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2554 {
2555 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2556 int num_ps_threads;
2557 int num_vs_threads;
2558 int num_gs_threads;
2559 int num_es_threads;
2560 int num_hs_threads;
2561 int num_ls_threads;
2562
2563 int num_ps_stack_entries;
2564 int num_vs_stack_entries;
2565 int num_gs_stack_entries;
2566 int num_es_stack_entries;
2567 int num_hs_stack_entries;
2568 int num_ls_stack_entries;
2569 enum radeon_family family;
2570 unsigned tmp, i;
2571
2572 if (rctx->b.chip_class == CAYMAN) {
2573 cayman_init_atom_start_cs(rctx);
2574 return;
2575 }
2576
2577 r600_init_command_buffer(cb, 338);
2578
2579 /* This must be first. */
2580 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2581 r600_store_value(cb, 0x80000000);
2582 r600_store_value(cb, 0x80000000);
2583
2584 /* We're setting config registers here. */
2585 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2586 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2587
2588 /* This enables pipeline stat & streamout queries.
2589 * They are only disabled by blits.
2590 */
2591 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2592 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2593
2594 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2595 rctx->b.family, rctx->screen->b.info.drm_minor);
2596
2597 family = rctx->b.family;
2598 switch (family) {
2599 case CHIP_CEDAR:
2600 default:
2601 num_ps_threads = 96;
2602 num_vs_threads = 16;
2603 num_gs_threads = 16;
2604 num_es_threads = 16;
2605 num_hs_threads = 16;
2606 num_ls_threads = 16;
2607 num_ps_stack_entries = 42;
2608 num_vs_stack_entries = 42;
2609 num_gs_stack_entries = 42;
2610 num_es_stack_entries = 42;
2611 num_hs_stack_entries = 42;
2612 num_ls_stack_entries = 42;
2613 break;
2614 case CHIP_REDWOOD:
2615 num_ps_threads = 128;
2616 num_vs_threads = 20;
2617 num_gs_threads = 20;
2618 num_es_threads = 20;
2619 num_hs_threads = 20;
2620 num_ls_threads = 20;
2621 num_ps_stack_entries = 42;
2622 num_vs_stack_entries = 42;
2623 num_gs_stack_entries = 42;
2624 num_es_stack_entries = 42;
2625 num_hs_stack_entries = 42;
2626 num_ls_stack_entries = 42;
2627 break;
2628 case CHIP_JUNIPER:
2629 num_ps_threads = 128;
2630 num_vs_threads = 20;
2631 num_gs_threads = 20;
2632 num_es_threads = 20;
2633 num_hs_threads = 20;
2634 num_ls_threads = 20;
2635 num_ps_stack_entries = 85;
2636 num_vs_stack_entries = 85;
2637 num_gs_stack_entries = 85;
2638 num_es_stack_entries = 85;
2639 num_hs_stack_entries = 85;
2640 num_ls_stack_entries = 85;
2641 break;
2642 case CHIP_CYPRESS:
2643 case CHIP_HEMLOCK:
2644 num_ps_threads = 128;
2645 num_vs_threads = 20;
2646 num_gs_threads = 20;
2647 num_es_threads = 20;
2648 num_hs_threads = 20;
2649 num_ls_threads = 20;
2650 num_ps_stack_entries = 85;
2651 num_vs_stack_entries = 85;
2652 num_gs_stack_entries = 85;
2653 num_es_stack_entries = 85;
2654 num_hs_stack_entries = 85;
2655 num_ls_stack_entries = 85;
2656 break;
2657 case CHIP_PALM:
2658 num_ps_threads = 96;
2659 num_vs_threads = 16;
2660 num_gs_threads = 16;
2661 num_es_threads = 16;
2662 num_hs_threads = 16;
2663 num_ls_threads = 16;
2664 num_ps_stack_entries = 42;
2665 num_vs_stack_entries = 42;
2666 num_gs_stack_entries = 42;
2667 num_es_stack_entries = 42;
2668 num_hs_stack_entries = 42;
2669 num_ls_stack_entries = 42;
2670 break;
2671 case CHIP_SUMO:
2672 num_ps_threads = 96;
2673 num_vs_threads = 25;
2674 num_gs_threads = 25;
2675 num_es_threads = 25;
2676 num_hs_threads = 16;
2677 num_ls_threads = 16;
2678 num_ps_stack_entries = 42;
2679 num_vs_stack_entries = 42;
2680 num_gs_stack_entries = 42;
2681 num_es_stack_entries = 42;
2682 num_hs_stack_entries = 42;
2683 num_ls_stack_entries = 42;
2684 break;
2685 case CHIP_SUMO2:
2686 num_ps_threads = 96;
2687 num_vs_threads = 25;
2688 num_gs_threads = 25;
2689 num_es_threads = 25;
2690 num_hs_threads = 16;
2691 num_ls_threads = 16;
2692 num_ps_stack_entries = 85;
2693 num_vs_stack_entries = 85;
2694 num_gs_stack_entries = 85;
2695 num_es_stack_entries = 85;
2696 num_hs_stack_entries = 85;
2697 num_ls_stack_entries = 85;
2698 break;
2699 case CHIP_BARTS:
2700 num_ps_threads = 128;
2701 num_vs_threads = 20;
2702 num_gs_threads = 20;
2703 num_es_threads = 20;
2704 num_hs_threads = 20;
2705 num_ls_threads = 20;
2706 num_ps_stack_entries = 85;
2707 num_vs_stack_entries = 85;
2708 num_gs_stack_entries = 85;
2709 num_es_stack_entries = 85;
2710 num_hs_stack_entries = 85;
2711 num_ls_stack_entries = 85;
2712 break;
2713 case CHIP_TURKS:
2714 num_ps_threads = 128;
2715 num_vs_threads = 20;
2716 num_gs_threads = 20;
2717 num_es_threads = 20;
2718 num_hs_threads = 20;
2719 num_ls_threads = 20;
2720 num_ps_stack_entries = 42;
2721 num_vs_stack_entries = 42;
2722 num_gs_stack_entries = 42;
2723 num_es_stack_entries = 42;
2724 num_hs_stack_entries = 42;
2725 num_ls_stack_entries = 42;
2726 break;
2727 case CHIP_CAICOS:
2728 num_ps_threads = 96;
2729 num_vs_threads = 10;
2730 num_gs_threads = 10;
2731 num_es_threads = 10;
2732 num_hs_threads = 10;
2733 num_ls_threads = 10;
2734 num_ps_stack_entries = 42;
2735 num_vs_stack_entries = 42;
2736 num_gs_stack_entries = 42;
2737 num_es_stack_entries = 42;
2738 num_hs_stack_entries = 42;
2739 num_ls_stack_entries = 42;
2740 break;
2741 }
2742
2743 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2744 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2745 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2746 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2747
2748 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2749 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2750
2751 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2752 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2753 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2754
2755 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2756 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2757 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2758
2759 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2760 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2761 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2762
2763 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2764 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2765 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2766
2767 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2768 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2769
2770 /* remove LS/HS from one SIMD for hw workaround */
2771 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2772 r600_store_value(cb, 0xffffffff);
2773 r600_store_value(cb, 0xffffffff);
2774 r600_store_value(cb, 0xfffffffe);
2775
2776 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2777 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2778
2779 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2780 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2781 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2782 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2783 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2784 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2785 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2786
2787 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2788 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2789 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2790 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2791 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2792
2793 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2794 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2795 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2796 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2797 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2798 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2799 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2800 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2801 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2802 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2803 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2804 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2805 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2806 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2807
2808 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2809
2810 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2811
2812 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2813 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2814 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2815
2816 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2817
2818 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2819
2820 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2821 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2822 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2823
2824 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2825 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2826
2827 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2828 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2829 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2830 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2831
2832 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2833 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2834 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2835
2836 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2837 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2838 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2839
2840 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2841 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2842 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2843 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2844 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2845 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2846 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2847
2848 /* to avoid GPU doing any preloading of constant from random address */
2849 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2850 for (i = 0; i < 16; i++)
2851 r600_store_value(cb, 0);
2852
2853 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2854 for (i = 0; i < 16; i++)
2855 r600_store_value(cb, 0);
2856
2857 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2858 for (i = 0; i < 16; i++)
2859 r600_store_value(cb, 0);
2860
2861 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2862 for (i = 0; i < 16; i++)
2863 r600_store_value(cb, 0);
2864
2865 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2866 for (i = 0; i < 16; i++)
2867 r600_store_value(cb, 0);
2868
2869 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2870
2871 if (rctx->screen->b.has_streamout) {
2872 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2873 }
2874
2875 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2876 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2877 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2878 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2879 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2880 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2881
2882 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2883 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2884 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2885
2886 if (rctx->b.family == CHIP_CAICOS) {
2887 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2888 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2889 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2890 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2891 } else {
2892 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2893 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2894 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2895 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2896 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2897 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2898 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2899 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2900 }
2901
2902 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2903 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2904 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2905 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2906 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2907 }
2908
evergreen_update_ps_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2909 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2910 {
2911 struct r600_context *rctx = (struct r600_context *)ctx;
2912 struct r600_command_buffer *cb = &shader->command_buffer;
2913 struct r600_shader *rshader = &shader->shader;
2914 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2915 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2916 int ninterp = 0;
2917 boolean have_perspective = FALSE, have_linear = FALSE;
2918 static const unsigned spi_baryc_enable_bit[6] = {
2919 S_0286E0_PERSP_SAMPLE_ENA(1),
2920 S_0286E0_PERSP_CENTER_ENA(1),
2921 S_0286E0_PERSP_CENTROID_ENA(1),
2922 S_0286E0_LINEAR_SAMPLE_ENA(1),
2923 S_0286E0_LINEAR_CENTER_ENA(1),
2924 S_0286E0_LINEAR_CENTROID_ENA(1)
2925 };
2926 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2927 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2928 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2929 uint32_t spi_ps_input_cntl[32];
2930
2931 if (!cb->buf) {
2932 r600_init_command_buffer(cb, 64);
2933 } else {
2934 cb->num_dw = 0;
2935 }
2936
2937 for (i = 0; i < rshader->ninput; i++) {
2938 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2939 POSITION goes via GPRs from the SC so isn't counted */
2940 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2941 pos_index = i;
2942 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2943 if (face_index == -1)
2944 face_index = i;
2945 }
2946 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2947 if (face_index == -1)
2948 face_index = i; /* lives in same register, same enable bit */
2949 }
2950 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
2951 fixed_pt_position_index = i;
2952 }
2953 else {
2954 ninterp++;
2955 int k = eg_get_interpolator_index(
2956 rshader->input[i].interpolate,
2957 rshader->input[i].interpolate_location);
2958 if (k >= 0) {
2959 spi_baryc_cntl |= spi_baryc_enable_bit[k];
2960 have_perspective |= k < 3;
2961 have_linear |= !(k < 3);
2962 }
2963 }
2964
2965 sid = rshader->input[i].spi_sid;
2966
2967 if (sid) {
2968 tmp = S_028644_SEMANTIC(sid);
2969
2970 /* D3D 9 behaviour. GL is undefined */
2971 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2972 tmp |= S_028644_DEFAULT_VAL(3);
2973
2974 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2975 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2976 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2977 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2978 tmp |= S_028644_FLAT_SHADE(1);
2979 }
2980
2981 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2982 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
2983 tmp |= S_028644_PT_SPRITE_TEX(1);
2984 }
2985
2986 spi_ps_input_cntl[num++] = tmp;
2987 }
2988 }
2989
2990 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
2991 r600_store_array(cb, num, spi_ps_input_cntl);
2992
2993 for (i = 0; i < rshader->noutput; i++) {
2994 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2995 z_export = 1;
2996 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2997 stencil_export = 1;
2998 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2999 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3000 mask_export = 1;
3001 }
3002 if (rshader->uses_kill)
3003 db_shader_control |= S_02880C_KILL_ENABLE(1);
3004
3005 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3006 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3007 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3008
3009 switch (rshader->ps_conservative_z) {
3010 default: /* fall through */
3011 case TGSI_FS_DEPTH_LAYOUT_ANY:
3012 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3013 break;
3014 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3015 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3016 break;
3017 case TGSI_FS_DEPTH_LAYOUT_LESS:
3018 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3019 break;
3020 }
3021
3022 exports_ps = 0;
3023 for (i = 0; i < rshader->noutput; i++) {
3024 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3025 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3026 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3027 exports_ps |= 1;
3028 }
3029
3030 num_cout = rshader->nr_ps_color_exports;
3031
3032 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3033 if (!exports_ps) {
3034 /* always at least export 1 component per pixel */
3035 exports_ps = 2;
3036 }
3037 shader->nr_ps_color_outputs = num_cout;
3038 if (ninterp == 0) {
3039 ninterp = 1;
3040 have_perspective = TRUE;
3041 }
3042 if (!spi_baryc_cntl)
3043 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3044
3045 if (!have_perspective && !have_linear)
3046 have_perspective = TRUE;
3047
3048 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3049 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3050 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3051 spi_input_z = 0;
3052 if (pos_index != -1) {
3053 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3054 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3055 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3056 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3057 }
3058
3059 spi_ps_in_control_1 = 0;
3060 if (face_index != -1) {
3061 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3062 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3063 }
3064 if (fixed_pt_position_index != -1) {
3065 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3066 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3067 }
3068
3069 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3070 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3071 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3072
3073 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3074 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3075 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3076
3077 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3078 r600_store_value(cb, shader->bo->gpu_address >> 8);
3079 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3080 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3081 S_028844_PRIME_CACHE_ON_DRAW(1) |
3082 S_028844_STACK_SIZE(rshader->bc.nstack));
3083 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3084
3085 shader->db_shader_control = db_shader_control;
3086 shader->ps_depth_export = z_export | stencil_export | mask_export;
3087
3088 shader->sprite_coord_enable = sprite_coord_enable;
3089 if (rctx->rasterizer)
3090 shader->flatshade = rctx->rasterizer->flatshade;
3091 }
3092
evergreen_update_es_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3093 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3094 {
3095 struct r600_command_buffer *cb = &shader->command_buffer;
3096 struct r600_shader *rshader = &shader->shader;
3097
3098 r600_init_command_buffer(cb, 32);
3099
3100 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3101 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3102 S_028890_STACK_SIZE(rshader->bc.nstack));
3103 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3104 shader->bo->gpu_address >> 8);
3105 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3106 }
3107
evergreen_update_gs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3108 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3109 {
3110 struct r600_context *rctx = (struct r600_context *)ctx;
3111 struct r600_command_buffer *cb = &shader->command_buffer;
3112 struct r600_shader *rshader = &shader->shader;
3113 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3114 unsigned gsvs_itemsizes[4] = {
3115 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3116 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3117 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3118 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3119 };
3120
3121 r600_init_command_buffer(cb, 64);
3122
3123 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3124
3125
3126 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3127 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3128 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3129 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3130
3131 if (rctx->screen->b.info.drm_minor >= 35) {
3132 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3133 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3134 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3135 }
3136 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3137 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3138 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3139 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3140 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3141
3142 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3143 (rshader->ring_item_sizes[0]) >> 2);
3144
3145 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3146 gsvs_itemsizes[0] +
3147 gsvs_itemsizes[1] +
3148 gsvs_itemsizes[2] +
3149 gsvs_itemsizes[3]);
3150
3151 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3152 r600_store_value(cb, gsvs_itemsizes[0]);
3153 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3154 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3155
3156 /* FIXME calculate these values somehow ??? */
3157 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3158 r600_store_value(cb, 0x80); /* GS_PER_ES */
3159 r600_store_value(cb, 0x100); /* ES_PER_GS */
3160 r600_store_value(cb, 0x2); /* GS_PER_VS */
3161
3162 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3163 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3164 S_028878_STACK_SIZE(rshader->bc.nstack));
3165 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3166 shader->bo->gpu_address >> 8);
3167 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3168 }
3169
3170
evergreen_update_vs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3171 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3172 {
3173 struct r600_command_buffer *cb = &shader->command_buffer;
3174 struct r600_shader *rshader = &shader->shader;
3175 unsigned spi_vs_out_id[10] = {};
3176 unsigned i, tmp, nparams = 0;
3177
3178 for (i = 0; i < rshader->noutput; i++) {
3179 if (rshader->output[i].spi_sid) {
3180 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3181 spi_vs_out_id[nparams / 4] |= tmp;
3182 nparams++;
3183 }
3184 }
3185
3186 r600_init_command_buffer(cb, 32);
3187
3188 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3189 for (i = 0; i < 10; i++) {
3190 r600_store_value(cb, spi_vs_out_id[i]);
3191 }
3192
3193 /* Certain attributes (position, psize, etc.) don't count as params.
3194 * VS is required to export at least one param and r600_shader_from_tgsi()
3195 * takes care of adding a dummy export.
3196 */
3197 if (nparams < 1)
3198 nparams = 1;
3199
3200 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3201 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3202 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3203 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3204 S_028860_STACK_SIZE(rshader->bc.nstack));
3205 if (rshader->vs_position_window_space) {
3206 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3207 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3208 } else {
3209 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3210 S_028818_VTX_W0_FMT(1) |
3211 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3212 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3213 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3214
3215 }
3216 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3217 shader->bo->gpu_address >> 8);
3218 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3219
3220 shader->pa_cl_vs_out_cntl =
3221 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3222 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3223 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3224 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3225 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3226 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3227 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3228 }
3229
evergreen_update_hs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3230 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3231 {
3232 struct r600_command_buffer *cb = &shader->command_buffer;
3233 struct r600_shader *rshader = &shader->shader;
3234
3235 r600_init_command_buffer(cb, 32);
3236 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3237 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3238 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3239 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3240 shader->bo->gpu_address >> 8);
3241 }
3242
evergreen_update_ls_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3243 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3244 {
3245 struct r600_command_buffer *cb = &shader->command_buffer;
3246 struct r600_shader *rshader = &shader->shader;
3247
3248 r600_init_command_buffer(cb, 32);
3249 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3250 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3251 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3252 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3253 shader->bo->gpu_address >> 8);
3254 }
evergreen_create_resolve_blend(struct r600_context * rctx)3255 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3256 {
3257 struct pipe_blend_state blend;
3258
3259 memset(&blend, 0, sizeof(blend));
3260 blend.independent_blend_enable = true;
3261 blend.rt[0].colormask = 0xf;
3262 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3263 }
3264
evergreen_create_decompress_blend(struct r600_context * rctx)3265 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3266 {
3267 struct pipe_blend_state blend;
3268 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3269 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3270
3271 memset(&blend, 0, sizeof(blend));
3272 blend.independent_blend_enable = true;
3273 blend.rt[0].colormask = 0xf;
3274 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3275 }
3276
evergreen_create_fastclear_blend(struct r600_context * rctx)3277 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3278 {
3279 struct pipe_blend_state blend;
3280 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3281
3282 memset(&blend, 0, sizeof(blend));
3283 blend.independent_blend_enable = true;
3284 blend.rt[0].colormask = 0xf;
3285 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3286 }
3287
evergreen_create_db_flush_dsa(struct r600_context * rctx)3288 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3289 {
3290 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3291
3292 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3293 }
3294
evergreen_update_db_shader_control(struct r600_context * rctx)3295 void evergreen_update_db_shader_control(struct r600_context * rctx)
3296 {
3297 bool dual_export;
3298 unsigned db_shader_control;
3299
3300 if (!rctx->ps_shader) {
3301 return;
3302 }
3303
3304 dual_export = rctx->framebuffer.export_16bpc &&
3305 !rctx->ps_shader->current->ps_depth_export;
3306
3307 db_shader_control = rctx->ps_shader->current->db_shader_control |
3308 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3309 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3310 V_02880C_EXPORT_DB_FULL) |
3311 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3312
3313 /* When alpha test is enabled we can't trust the hw to make the proper
3314 * decision on the order in which ztest should be run related to fragment
3315 * shader execution.
3316 *
3317 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3318 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3319 * execution and thus after alpha test so if discarded by the alpha test
3320 * the z value is not written.
3321 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3322 * get a hang unless you flush the DB in between. For now just use
3323 * LATE_Z.
3324 */
3325 if (rctx->alphatest_state.sx_alpha_test_control) {
3326 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3327 } else {
3328 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3329 }
3330
3331 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3332 rctx->db_misc_state.db_shader_control = db_shader_control;
3333 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3334 }
3335 }
3336
evergreen_dma_copy_tile(struct r600_context * rctx,struct pipe_resource * dst,unsigned dst_level,unsigned dst_x,unsigned dst_y,unsigned dst_z,struct pipe_resource * src,unsigned src_level,unsigned src_x,unsigned src_y,unsigned src_z,unsigned copy_height,unsigned pitch,unsigned bpp)3337 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3338 struct pipe_resource *dst,
3339 unsigned dst_level,
3340 unsigned dst_x,
3341 unsigned dst_y,
3342 unsigned dst_z,
3343 struct pipe_resource *src,
3344 unsigned src_level,
3345 unsigned src_x,
3346 unsigned src_y,
3347 unsigned src_z,
3348 unsigned copy_height,
3349 unsigned pitch,
3350 unsigned bpp)
3351 {
3352 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3353 struct r600_texture *rsrc = (struct r600_texture*)src;
3354 struct r600_texture *rdst = (struct r600_texture*)dst;
3355 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3356 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3357 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3358 uint64_t base, addr;
3359
3360 dst_mode = rdst->surface.level[dst_level].mode;
3361 src_mode = rsrc->surface.level[src_level].mode;
3362 assert(dst_mode != src_mode);
3363
3364 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3365 if (util_format_has_depth(util_format_description(src->format)))
3366 non_disp_tiling = 1;
3367
3368 y = 0;
3369 sub_cmd = EG_DMA_COPY_TILED;
3370 lbpp = util_logbase2(bpp);
3371 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3372 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3373
3374 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3375 /* T2L */
3376 array_mode = evergreen_array_mode(src_mode);
3377 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3378 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3379 /* linear height must be the same as the slice tile max height, it's ok even
3380 * if the linear destination/source have smaller heigh as the size of the
3381 * dma packet will be using the copy_height which is always smaller or equal
3382 * to the linear height
3383 */
3384 height = u_minify(rsrc->resource.b.b.height0, src_level);
3385 detile = 1;
3386 x = src_x;
3387 y = src_y;
3388 z = src_z;
3389 base = rsrc->surface.level[src_level].offset;
3390 addr = rdst->surface.level[dst_level].offset;
3391 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3392 addr += dst_y * pitch + dst_x * bpp;
3393 bank_h = eg_bank_wh(rsrc->surface.bankh);
3394 bank_w = eg_bank_wh(rsrc->surface.bankw);
3395 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3396 tile_split = eg_tile_split(rsrc->surface.tile_split);
3397 base += rsrc->resource.gpu_address;
3398 addr += rdst->resource.gpu_address;
3399 } else {
3400 /* L2T */
3401 array_mode = evergreen_array_mode(dst_mode);
3402 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3403 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3404 /* linear height must be the same as the slice tile max height, it's ok even
3405 * if the linear destination/source have smaller heigh as the size of the
3406 * dma packet will be using the copy_height which is always smaller or equal
3407 * to the linear height
3408 */
3409 height = u_minify(rdst->resource.b.b.height0, dst_level);
3410 detile = 0;
3411 x = dst_x;
3412 y = dst_y;
3413 z = dst_z;
3414 base = rdst->surface.level[dst_level].offset;
3415 addr = rsrc->surface.level[src_level].offset;
3416 addr += rsrc->surface.level[src_level].slice_size * src_z;
3417 addr += src_y * pitch + src_x * bpp;
3418 bank_h = eg_bank_wh(rdst->surface.bankh);
3419 bank_w = eg_bank_wh(rdst->surface.bankw);
3420 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3421 tile_split = eg_tile_split(rdst->surface.tile_split);
3422 base += rdst->resource.gpu_address;
3423 addr += rsrc->resource.gpu_address;
3424 }
3425
3426 size = (copy_height * pitch) / 4;
3427 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3428 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3429
3430 for (i = 0; i < ncopy; i++) {
3431 cheight = copy_height;
3432 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3433 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3434 }
3435 size = (cheight * pitch) / 4;
3436 /* emit reloc before writing cs so that cs is always in consistent state */
3437 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3438 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3439 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3440 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3441 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3442 radeon_emit(cs, base >> 8);
3443 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3444 (lbpp << 24) | (bank_h << 21) |
3445 (bank_w << 18) | (mt_aspect << 16));
3446 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3447 radeon_emit(cs, (slice_tile_max << 0));
3448 radeon_emit(cs, (x << 0) | (z << 18));
3449 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3450 radeon_emit(cs, addr & 0xfffffffc);
3451 radeon_emit(cs, (addr >> 32UL) & 0xff);
3452 copy_height -= cheight;
3453 addr += cheight * pitch;
3454 y += cheight;
3455 }
3456 }
3457
evergreen_dma_copy(struct pipe_context * ctx,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)3458 static void evergreen_dma_copy(struct pipe_context *ctx,
3459 struct pipe_resource *dst,
3460 unsigned dst_level,
3461 unsigned dstx, unsigned dsty, unsigned dstz,
3462 struct pipe_resource *src,
3463 unsigned src_level,
3464 const struct pipe_box *src_box)
3465 {
3466 struct r600_context *rctx = (struct r600_context *)ctx;
3467 struct r600_texture *rsrc = (struct r600_texture*)src;
3468 struct r600_texture *rdst = (struct r600_texture*)dst;
3469 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3470 unsigned src_w, dst_w;
3471 unsigned src_x, src_y;
3472 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3473
3474 if (rctx->b.dma.cs == NULL) {
3475 goto fallback;
3476 }
3477
3478 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3479 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3480 return;
3481 }
3482
3483 if (src_box->depth > 1 ||
3484 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3485 dstz, rsrc, src_level, src_box))
3486 goto fallback;
3487
3488 src_x = util_format_get_nblocksx(src->format, src_box->x);
3489 dst_x = util_format_get_nblocksx(src->format, dst_x);
3490 src_y = util_format_get_nblocksy(src->format, src_box->y);
3491 dst_y = util_format_get_nblocksy(src->format, dst_y);
3492
3493 bpp = rdst->surface.bpe;
3494 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
3495 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
3496 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3497 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3498 copy_height = src_box->height / rsrc->surface.blk_h;
3499
3500 dst_mode = rdst->surface.level[dst_level].mode;
3501 src_mode = rsrc->surface.level[src_level].mode;
3502
3503 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3504 /* FIXME evergreen can do partial blit */
3505 goto fallback;
3506 }
3507 /* the x test here are currently useless (because we don't support partial blit)
3508 * but keep them around so we don't forget about those
3509 */
3510 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3511 goto fallback;
3512 }
3513
3514 /* 128 bpp surfaces require non_disp_tiling for both
3515 * tiled and linear buffers on cayman. However, async
3516 * DMA only supports it on the tiled side. As such
3517 * the tile order is backwards after a L2T/T2L packet.
3518 */
3519 if ((rctx->b.chip_class == CAYMAN) &&
3520 (src_mode != dst_mode) &&
3521 (util_format_get_blocksize(src->format) >= 16)) {
3522 goto fallback;
3523 }
3524
3525 if (src_mode == dst_mode) {
3526 uint64_t dst_offset, src_offset;
3527 /* simple dma blit would do NOTE code here assume :
3528 * src_box.x/y == 0
3529 * dst_x/y == 0
3530 * dst_pitch == src_pitch
3531 */
3532 src_offset= rsrc->surface.level[src_level].offset;
3533 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3534 src_offset += src_y * src_pitch + src_x * bpp;
3535 dst_offset = rdst->surface.level[dst_level].offset;
3536 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3537 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3538 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3539 src_box->height * src_pitch);
3540 } else {
3541 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3542 src, src_level, src_x, src_y, src_box->z,
3543 copy_height, dst_pitch, bpp);
3544 }
3545 return;
3546
3547 fallback:
3548 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3549 src, src_level, src_box);
3550 }
3551
evergreen_set_tess_state(struct pipe_context * ctx,const float default_outer_level[4],const float default_inner_level[2])3552 static void evergreen_set_tess_state(struct pipe_context *ctx,
3553 const float default_outer_level[4],
3554 const float default_inner_level[2])
3555 {
3556 struct r600_context *rctx = (struct r600_context *)ctx;
3557
3558 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3559 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3560 rctx->tess_state_dirty = true;
3561 }
3562
evergreen_init_state_functions(struct r600_context * rctx)3563 void evergreen_init_state_functions(struct r600_context *rctx)
3564 {
3565 unsigned id = 1;
3566 unsigned i;
3567 /* !!!
3568 * To avoid GPU lockup registers must be emitted in a specific order
3569 * (no kidding ...). The order below is important and have been
3570 * partially inferred from analyzing fglrx command stream.
3571 *
3572 * Don't reorder atom without carefully checking the effect (GPU lockup
3573 * or piglit regression).
3574 * !!!
3575 */
3576 if (rctx->b.chip_class == EVERGREEN) {
3577 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3578 rctx->config_state.dyn_gpr_enabled = true;
3579 }
3580 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3581 /* shader const */
3582 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3583 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3584 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3585 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3586 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3587 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3588 /* shader program */
3589 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3590 /* sampler */
3591 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3592 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3593 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3594 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3595 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3596 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3597 /* resources */
3598 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3599 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3600 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3601 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3602 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3603 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3604 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3605 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3606
3607 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3608
3609 if (rctx->b.chip_class == EVERGREEN) {
3610 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3611 } else {
3612 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3613 }
3614 rctx->sample_mask.sample_mask = ~0;
3615
3616 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3617 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3618 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3619 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3620 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3621 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3622 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3623 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3624 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3625 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
3626 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3627 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3628 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3629 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3630 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3631 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3632 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3633 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3634 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3635 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3636 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3637 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3638
3639 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3640 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3641 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3642 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3643 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3644 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3645 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3646 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3647 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3648 if (rctx->b.chip_class == EVERGREEN)
3649 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3650 else
3651 rctx->b.b.get_sample_position = cayman_get_sample_position;
3652 rctx->b.dma_copy = evergreen_dma_copy;
3653
3654 evergreen_init_compute_state_functions(rctx);
3655 }
3656
3657 /**
3658 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3659 *
3660 * The information about LDS and other non-compile-time parameters is then
3661 * written to the const buffer.
3662
3663 * const buffer contains -
3664 * uint32_t input_patch_size
3665 * uint32_t input_vertex_size
3666 * uint32_t num_tcs_input_cp
3667 * uint32_t num_tcs_output_cp;
3668 * uint32_t output_patch_size
3669 * uint32_t output_vertex_size
3670 * uint32_t output_patch0_offset
3671 * uint32_t perpatch_output_offset
3672 * and the same constbuf is bound to LS/HS/VS(ES).
3673 */
evergreen_setup_tess_constants(struct r600_context * rctx,const struct pipe_draw_info * info,unsigned * num_patches)3674 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3675 {
3676 struct pipe_constant_buffer constbuf = {0};
3677 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3678 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3679 unsigned num_tcs_input_cp = info->vertices_per_patch;
3680 unsigned num_tcs_outputs;
3681 unsigned num_tcs_output_cp;
3682 unsigned num_tcs_patch_outputs;
3683 unsigned num_tcs_inputs;
3684 unsigned input_vertex_size, output_vertex_size;
3685 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3686 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3687 uint32_t values[16];
3688 unsigned num_waves;
3689 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3690 unsigned wave_divisor = (16 * num_pipes);
3691
3692 *num_patches = 1;
3693
3694 if (!rctx->tes_shader) {
3695 rctx->lds_alloc = 0;
3696 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3697 R600_LDS_INFO_CONST_BUFFER, NULL);
3698 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3699 R600_LDS_INFO_CONST_BUFFER, NULL);
3700 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3701 R600_LDS_INFO_CONST_BUFFER, NULL);
3702 return;
3703 }
3704
3705 if (rctx->lds_alloc != 0 &&
3706 rctx->last_ls == ls &&
3707 !rctx->tess_state_dirty &&
3708 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3709 rctx->last_tcs == tcs)
3710 return;
3711
3712 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3713
3714 if (rctx->tcs_shader) {
3715 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3716 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3717 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3718 } else {
3719 num_tcs_outputs = num_tcs_inputs;
3720 num_tcs_output_cp = num_tcs_input_cp;
3721 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3722 }
3723
3724 /* size in bytes */
3725 input_vertex_size = num_tcs_inputs * 16;
3726 output_vertex_size = num_tcs_outputs * 16;
3727
3728 input_patch_size = num_tcs_input_cp * input_vertex_size;
3729
3730 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3731 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3732
3733 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3734 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3735
3736 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3737
3738 values[0] = input_patch_size;
3739 values[1] = input_vertex_size;
3740 values[2] = num_tcs_input_cp;
3741 values[3] = num_tcs_output_cp;
3742
3743 values[4] = output_patch_size;
3744 values[5] = output_vertex_size;
3745 values[6] = output_patch0_offset;
3746 values[7] = perpatch_output_offset;
3747
3748 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3749 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3750 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3751
3752 rctx->lds_alloc = (lds_size | (num_waves << 14));
3753
3754 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3755 values[14] = 0;
3756 values[15] = 0;
3757
3758 rctx->tess_state_dirty = false;
3759 rctx->last_ls = ls;
3760 rctx->last_tcs = tcs;
3761 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3762
3763 constbuf.user_buffer = values;
3764 constbuf.buffer_size = 16 * 4;
3765
3766 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3767 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3768 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3769 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3770 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3771 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3772 pipe_resource_reference(&constbuf.buffer, NULL);
3773 }
3774
evergreen_get_ls_hs_config(struct r600_context * rctx,const struct pipe_draw_info * info,unsigned num_patches)3775 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3776 const struct pipe_draw_info *info,
3777 unsigned num_patches)
3778 {
3779 unsigned num_output_cp;
3780
3781 if (!rctx->tes_shader)
3782 return 0;
3783
3784 num_output_cp = rctx->tcs_shader ?
3785 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3786 info->vertices_per_patch;
3787
3788 return S_028B58_NUM_PATCHES(num_patches) |
3789 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3790 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3791 }
3792
evergreen_set_ls_hs_config(struct r600_context * rctx,struct radeon_winsys_cs * cs,uint32_t ls_hs_config)3793 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3794 struct radeon_winsys_cs *cs,
3795 uint32_t ls_hs_config)
3796 {
3797 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3798 }
3799
evergreen_set_lds_alloc(struct r600_context * rctx,struct radeon_winsys_cs * cs,uint32_t lds_alloc)3800 void evergreen_set_lds_alloc(struct r600_context *rctx,
3801 struct radeon_winsys_cs *cs,
3802 uint32_t lds_alloc)
3803 {
3804 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3805 }
3806
3807 /* on evergreen if you are running tessellation you need to disable dynamic
3808 GPRs to workaround a hardware bug.*/
evergreen_adjust_gprs(struct r600_context * rctx)3809 bool evergreen_adjust_gprs(struct r600_context *rctx)
3810 {
3811 unsigned num_gprs[EG_NUM_HW_STAGES];
3812 unsigned def_gprs[EG_NUM_HW_STAGES];
3813 unsigned cur_gprs[EG_NUM_HW_STAGES];
3814 unsigned new_gprs[EG_NUM_HW_STAGES];
3815 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3816 unsigned max_gprs;
3817 unsigned i;
3818 unsigned total_gprs;
3819 unsigned tmp[3];
3820 bool rework = false, set_default = false, set_dirty = false;
3821 max_gprs = 0;
3822 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3823 def_gprs[i] = rctx->default_gprs[i];
3824 max_gprs += def_gprs[i];
3825 }
3826 max_gprs += def_num_clause_temp_gprs * 2;
3827
3828 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3829 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3830 if (rctx->config_state.dyn_gpr_enabled)
3831 return true;
3832
3833 /* transition back to dyn gpr enabled state */
3834 rctx->config_state.dyn_gpr_enabled = true;
3835 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3836 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3837 return true;
3838 }
3839
3840
3841 /* gather required shader gprs */
3842 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3843 if (rctx->hw_shader_stages[i].shader)
3844 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3845 else
3846 num_gprs[i] = 0;
3847 }
3848
3849 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3850 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3851 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3852 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3853 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3854 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3855
3856 total_gprs = 0;
3857 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3858 new_gprs[i] = num_gprs[i];
3859 total_gprs += num_gprs[i];
3860 }
3861
3862 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3863 return false;
3864
3865 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3866 if (new_gprs[i] > cur_gprs[i]) {
3867 rework = true;
3868 break;
3869 }
3870 }
3871
3872 if (rctx->config_state.dyn_gpr_enabled) {
3873 set_dirty = true;
3874 rctx->config_state.dyn_gpr_enabled = false;
3875 }
3876
3877 if (rework) {
3878 set_default = true;
3879 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3880 if (new_gprs[i] > def_gprs[i])
3881 set_default = false;
3882 }
3883
3884 if (set_default) {
3885 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3886 new_gprs[i] = def_gprs[i];
3887 }
3888 } else {
3889 unsigned ps_value = max_gprs;
3890
3891 ps_value -= (def_num_clause_temp_gprs * 2);
3892 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3893 ps_value -= new_gprs[i];
3894
3895 new_gprs[R600_HW_STAGE_PS] = ps_value;
3896 }
3897
3898 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3899 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3900 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3901
3902 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3903 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3904
3905 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3906 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3907
3908 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3909 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3910 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3911 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3912 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3913 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3914 set_dirty = true;
3915 }
3916 }
3917
3918
3919 if (set_dirty) {
3920 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3921 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3922 }
3923 return true;
3924 }
3925