• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- llvm/InlineAsm.h - Class to represent inline asm strings-*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class represents the inline asm strings, which are Value*'s that are
11 // used as the callee operand of call instructions.  InlineAsm's are uniqued
12 // like constants, and created via InlineAsm::get(...).
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_IR_INLINEASM_H
17 #define LLVM_IR_INLINEASM_H
18 
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/IR/Value.h"
21 #include <vector>
22 
23 namespace llvm {
24 
25 class PointerType;
26 class FunctionType;
27 class Module;
28 
29 struct InlineAsmKeyType;
30 template <class ConstantClass> class ConstantUniqueMap;
31 
32 class InlineAsm : public Value {
33 public:
34   enum AsmDialect {
35     AD_ATT,
36     AD_Intel
37   };
38 
39 private:
40   friend struct InlineAsmKeyType;
41   friend class ConstantUniqueMap<InlineAsm>;
42 
43   InlineAsm(const InlineAsm &) = delete;
44   void operator=(const InlineAsm&) = delete;
45 
46   std::string AsmString, Constraints;
47   FunctionType *FTy;
48   bool HasSideEffects;
49   bool IsAlignStack;
50   AsmDialect Dialect;
51 
52   InlineAsm(FunctionType *Ty, const std::string &AsmString,
53             const std::string &Constraints, bool hasSideEffects,
54             bool isAlignStack, AsmDialect asmDialect);
55   ~InlineAsm() override;
56 
57   /// When the ConstantUniqueMap merges two types and makes two InlineAsms
58   /// identical, it destroys one of them with this method.
59   void destroyConstant();
60 
61 public:
62   /// InlineAsm::get - Return the specified uniqued inline asm string.
63   ///
64   static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
65                         StringRef Constraints, bool hasSideEffects,
66                         bool isAlignStack = false,
67                         AsmDialect asmDialect = AD_ATT);
68 
hasSideEffects()69   bool hasSideEffects() const { return HasSideEffects; }
isAlignStack()70   bool isAlignStack() const { return IsAlignStack; }
getDialect()71   AsmDialect getDialect() const { return Dialect; }
72 
73   /// getType - InlineAsm's are always pointers.
74   ///
getType()75   PointerType *getType() const {
76     return reinterpret_cast<PointerType*>(Value::getType());
77   }
78 
79   /// getFunctionType - InlineAsm's are always pointers to functions.
80   ///
81   FunctionType *getFunctionType() const;
82 
getAsmString()83   const std::string &getAsmString() const { return AsmString; }
getConstraintString()84   const std::string &getConstraintString() const { return Constraints; }
85 
86   /// Verify - This static method can be used by the parser to check to see if
87   /// the specified constraint string is legal for the type.  This returns true
88   /// if legal, false if not.
89   ///
90   static bool Verify(FunctionType *Ty, StringRef Constraints);
91 
92   // Constraint String Parsing
93   enum ConstraintPrefix {
94     isInput,            // 'x'
95     isOutput,           // '=x'
96     isClobber           // '~x'
97   };
98 
99   typedef std::vector<std::string> ConstraintCodeVector;
100 
101   struct SubConstraintInfo {
102     /// MatchingInput - If this is not -1, this is an output constraint where an
103     /// input constraint is required to match it (e.g. "0").  The value is the
104     /// constraint number that matches this one (for example, if this is
105     /// constraint #0 and constraint #4 has the value "0", this will be 4).
106     signed char MatchingInput;
107     /// Code - The constraint code, either the register name (in braces) or the
108     /// constraint letter/number.
109     ConstraintCodeVector Codes;
110     /// Default constructor.
SubConstraintInfoSubConstraintInfo111     SubConstraintInfo() : MatchingInput(-1) {}
112   };
113 
114   typedef std::vector<SubConstraintInfo> SubConstraintInfoVector;
115   struct ConstraintInfo;
116   typedef std::vector<ConstraintInfo> ConstraintInfoVector;
117 
118   struct ConstraintInfo {
119     /// Type - The basic type of the constraint: input/output/clobber
120     ///
121     ConstraintPrefix Type;
122 
123     /// isEarlyClobber - "&": output operand writes result before inputs are all
124     /// read.  This is only ever set for an output operand.
125     bool isEarlyClobber;
126 
127     /// MatchingInput - If this is not -1, this is an output constraint where an
128     /// input constraint is required to match it (e.g. "0").  The value is the
129     /// constraint number that matches this one (for example, if this is
130     /// constraint #0 and constraint #4 has the value "0", this will be 4).
131     signed char MatchingInput;
132 
133     /// hasMatchingInput - Return true if this is an output constraint that has
134     /// a matching input constraint.
hasMatchingInputConstraintInfo135     bool hasMatchingInput() const { return MatchingInput != -1; }
136 
137     /// isCommutative - This is set to true for a constraint that is commutative
138     /// with the next operand.
139     bool isCommutative;
140 
141     /// isIndirect - True if this operand is an indirect operand.  This means
142     /// that the address of the source or destination is present in the call
143     /// instruction, instead of it being returned or passed in explicitly.  This
144     /// is represented with a '*' in the asm string.
145     bool isIndirect;
146 
147     /// Code - The constraint code, either the register name (in braces) or the
148     /// constraint letter/number.
149     ConstraintCodeVector Codes;
150 
151     /// isMultipleAlternative - '|': has multiple-alternative constraints.
152     bool isMultipleAlternative;
153 
154     /// multipleAlternatives - If there are multiple alternative constraints,
155     /// this array will contain them.  Otherwise it will be empty.
156     SubConstraintInfoVector multipleAlternatives;
157 
158     /// The currently selected alternative constraint index.
159     unsigned currentAlternativeIndex;
160 
161     /// Default constructor.
162     ConstraintInfo();
163 
164     /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
165     /// fields in this structure.  If the constraint string is not understood,
166     /// return true, otherwise return false.
167     bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
168 
169     /// selectAlternative - Point this constraint to the alternative constraint
170     /// indicated by the index.
171     void selectAlternative(unsigned index);
172   };
173 
174   /// ParseConstraints - Split up the constraint string into the specific
175   /// constraints and their prefixes.  If this returns an empty vector, and if
176   /// the constraint string itself isn't empty, there was an error parsing.
177   static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
178 
179   /// ParseConstraints - Parse the constraints of this inlineasm object,
180   /// returning them the same way that ParseConstraints(str) does.
ParseConstraints()181   ConstraintInfoVector ParseConstraints() const {
182     return ParseConstraints(Constraints);
183   }
184 
185   // Methods for support type inquiry through isa, cast, and dyn_cast:
classof(const Value * V)186   static inline bool classof(const Value *V) {
187     return V->getValueID() == Value::InlineAsmVal;
188   }
189 
190   // These are helper methods for dealing with flags in the INLINEASM SDNode
191   // in the backend.
192   //
193   // The encoding of the flag word is currently:
194   //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
195   //   Bits 15-3 - The number of SDNode operands associated with this inline
196   //               assembly operand.
197   //   If bit 31 is set:
198   //     Bit 30-16 - The operand number that this operand must match.
199   //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
200   //                 obtained from the flags for this operand number.
201   //   Else if bits 2-0 are Kind_Mem:
202   //     Bit 30-16 - A Constraint_* value indicating the original constraint
203   //                 code.
204   //   Else:
205   //     Bit 30-16 - The register class ID to use for the operand.
206 
207   enum : uint32_t {
208     // Fixed operands on an INLINEASM SDNode.
209     Op_InputChain = 0,
210     Op_AsmString = 1,
211     Op_MDNode = 2,
212     Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
213     Op_FirstOperand = 4,
214 
215     // Fixed operands on an INLINEASM MachineInstr.
216     MIOp_AsmString = 0,
217     MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
218     MIOp_FirstOperand = 2,
219 
220     // Interpretation of the MIOp_ExtraInfo bit field.
221     Extra_HasSideEffects = 1,
222     Extra_IsAlignStack = 2,
223     Extra_AsmDialect = 4,
224     Extra_MayLoad = 8,
225     Extra_MayStore = 16,
226     Extra_IsConvergent = 32,
227 
228     // Inline asm operands map to multiple SDNode / MachineInstr operands.
229     // The first operand is an immediate describing the asm operand, the low
230     // bits is the kind:
231     Kind_RegUse = 1,             // Input register, "r".
232     Kind_RegDef = 2,             // Output register, "=r".
233     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
234     Kind_Clobber = 4,            // Clobbered register, "~r".
235     Kind_Imm = 5,                // Immediate.
236     Kind_Mem = 6,                // Memory operand, "m".
237 
238     // Memory constraint codes.
239     // These could be tablegenerated but there's little need to do that since
240     // there's plenty of space in the encoding to support the union of all
241     // constraint codes for all targets.
242     Constraint_Unknown = 0,
243     Constraint_es,
244     Constraint_i,
245     Constraint_m,
246     Constraint_o,
247     Constraint_v,
248     Constraint_Q,
249     Constraint_R,
250     Constraint_S,
251     Constraint_T,
252     Constraint_Um,
253     Constraint_Un,
254     Constraint_Uq,
255     Constraint_Us,
256     Constraint_Ut,
257     Constraint_Uv,
258     Constraint_Uy,
259     Constraint_X,
260     Constraint_Z,
261     Constraint_ZC,
262     Constraint_Zy,
263     Constraints_Max = Constraint_Zy,
264     Constraints_ShiftAmount = 16,
265 
266     Flag_MatchingOperand = 0x80000000
267   };
268 
getFlagWord(unsigned Kind,unsigned NumOps)269   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
270     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
271     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
272     return Kind | (NumOps << 3);
273   }
274 
275   /// getFlagWordForMatchingOp - Augment an existing flag word returned by
276   /// getFlagWord with information indicating that this input operand is tied
277   /// to a previous output operand.
getFlagWordForMatchingOp(unsigned InputFlag,unsigned MatchedOperandNo)278   static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
279                                            unsigned MatchedOperandNo) {
280     assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
281     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
282     return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
283   }
284 
285   /// getFlagWordForRegClass - Augment an existing flag word returned by
286   /// getFlagWord with the required register class for the following register
287   /// operands.
288   /// A tied use operand cannot have a register class, use the register class
289   /// from the def operand instead.
getFlagWordForRegClass(unsigned InputFlag,unsigned RC)290   static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
291     // Store RC + 1, reserve the value 0 to mean 'no register class'.
292     ++RC;
293     assert(RC <= 0x7fff && "Too large register class ID");
294     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
295     return InputFlag | (RC << 16);
296   }
297 
298   /// Augment an existing flag word returned by getFlagWord with the constraint
299   /// code for a memory constraint.
getFlagWordForMem(unsigned InputFlag,unsigned Constraint)300   static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
301     assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
302     assert(Constraint <= Constraints_Max && "Unknown constraint ID");
303     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
304     return InputFlag | (Constraint << Constraints_ShiftAmount);
305   }
306 
convertMemFlagWordToMatchingFlagWord(unsigned InputFlag)307   static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
308     assert(isMemKind(InputFlag));
309     return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
310   }
311 
getKind(unsigned Flags)312   static unsigned getKind(unsigned Flags) {
313     return Flags & 7;
314   }
315 
isRegDefKind(unsigned Flag)316   static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
isImmKind(unsigned Flag)317   static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
isMemKind(unsigned Flag)318   static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
isRegDefEarlyClobberKind(unsigned Flag)319   static bool isRegDefEarlyClobberKind(unsigned Flag) {
320     return getKind(Flag) == Kind_RegDefEarlyClobber;
321   }
isClobberKind(unsigned Flag)322   static bool isClobberKind(unsigned Flag) {
323     return getKind(Flag) == Kind_Clobber;
324   }
325 
getMemoryConstraintID(unsigned Flag)326   static unsigned getMemoryConstraintID(unsigned Flag) {
327     assert(isMemKind(Flag));
328     return (Flag >> Constraints_ShiftAmount) & 0x7fff;
329   }
330 
331   /// getNumOperandRegisters - Extract the number of registers field from the
332   /// inline asm operand flag.
getNumOperandRegisters(unsigned Flag)333   static unsigned getNumOperandRegisters(unsigned Flag) {
334     return (Flag & 0xffff) >> 3;
335   }
336 
337   /// isUseOperandTiedToDef - Return true if the flag of the inline asm
338   /// operand indicates it is an use operand that's matched to a def operand.
isUseOperandTiedToDef(unsigned Flag,unsigned & Idx)339   static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
340     if ((Flag & Flag_MatchingOperand) == 0)
341       return false;
342     Idx = (Flag & ~Flag_MatchingOperand) >> 16;
343     return true;
344   }
345 
346   /// hasRegClassConstraint - Returns true if the flag contains a register
347   /// class constraint.  Sets RC to the register class ID.
hasRegClassConstraint(unsigned Flag,unsigned & RC)348   static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
349     if (Flag & Flag_MatchingOperand)
350       return false;
351     unsigned High = Flag >> 16;
352     // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
353     // stores RC + 1.
354     if (!High)
355       return false;
356     RC = High - 1;
357     return true;
358   }
359 };
360 
361 } // End llvm namespace
362 
363 #endif
364