1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Record.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include <algorithm>
20 using namespace llvm;
21
PrintDefList(const std::vector<Record * > & Uses,unsigned Num,raw_ostream & OS)22 static void PrintDefList(const std::vector<Record*> &Uses,
23 unsigned Num, raw_ostream &OS) {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
27 OS << "0 };\n";
28 }
29
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary Information.
32 //===----------------------------------------------------------------------===//
33
GatherItinClasses()34 void InstrInfoEmitter::GatherItinClasses() {
35 std::vector<Record*> DefList =
36 Records.getAllDerivedDefinitions("InstrItinClass");
37 std::sort(DefList.begin(), DefList.end(), LessRecord());
38
39 for (unsigned i = 0, N = DefList.size(); i < N; i++)
40 ItinClassMap[DefList[i]->getName()] = i;
41 }
42
getItinClassNumber(const Record * InstRec)43 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
44 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
45 }
46
47 //===----------------------------------------------------------------------===//
48 // Operand Info Emission.
49 //===----------------------------------------------------------------------===//
50
51 std::vector<std::string>
GetOperandInfo(const CodeGenInstruction & Inst)52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
53 std::vector<std::string> Result;
54
55 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
56 // Handle aggregate operands and normal operands the same way by expanding
57 // either case into a list of operands for this op.
58 std::vector<CGIOperandList::OperandInfo> OperandList;
59
60 // This might be a multiple operand thing. Targets like X86 have
61 // registers in their multi-operand operands. It may also be an anonymous
62 // operand, which has a single operand, but no declared class for the
63 // operand.
64 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
65
66 if (!MIOI || MIOI->getNumArgs() == 0) {
67 // Single, anonymous, operand.
68 OperandList.push_back(Inst.Operands[i]);
69 } else {
70 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
71 OperandList.push_back(Inst.Operands[i]);
72
73 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
74 OperandList.back().Rec = OpR;
75 }
76 }
77
78 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
79 Record *OpR = OperandList[j].Rec;
80 std::string Res;
81
82 if (OpR->isSubClassOf("RegisterOperand"))
83 OpR = OpR->getValueAsDef("RegClass");
84 if (OpR->isSubClassOf("RegisterClass"))
85 Res += getQualifiedName(OpR) + "RegClassID, ";
86 else if (OpR->isSubClassOf("PointerLikeRegClass"))
87 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
88 else
89 // -1 means the operand does not have a fixed register class.
90 Res += "-1, ";
91
92 // Fill in applicable flags.
93 Res += "0";
94
95 // Ptr value whose register class is resolved via callback.
96 if (OpR->isSubClassOf("PointerLikeRegClass"))
97 Res += "|(1<<MCOI::LookupPtrRegClass)";
98
99 // Predicate operands. Check to see if the original unexpanded operand
100 // was of type PredicateOperand.
101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
102 Res += "|(1<<MCOI::Predicate)";
103
104 // Optional def operands. Check to see if the original unexpanded operand
105 // was of type OptionalDefOperand.
106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
107 Res += "|(1<<MCOI::OptionalDef)";
108
109 // Fill in constraint info.
110 Res += ", ";
111
112 const CGIOperandList::ConstraintInfo &Constraint =
113 Inst.Operands[i].Constraints[j];
114 if (Constraint.isNone())
115 Res += "0";
116 else if (Constraint.isEarlyClobber())
117 Res += "(1 << MCOI::EARLY_CLOBBER)";
118 else {
119 assert(Constraint.isTied());
120 Res += "((" + utostr(Constraint.getTiedOperand()) +
121 " << 16) | (1 << MCOI::TIED_TO))";
122 }
123
124 // Fill in operand type.
125 Res += ", MCOI::";
126 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
127 Res += Inst.Operands[i].OperandType;
128
129 Result.push_back(Res);
130 }
131 }
132
133 return Result;
134 }
135
EmitOperandInfo(raw_ostream & OS,OperandInfoMapTy & OperandInfoIDs)136 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
137 OperandInfoMapTy &OperandInfoIDs) {
138 // ID #0 is for no operand info.
139 unsigned OperandListNum = 0;
140 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
141
142 OS << "\n";
143 const CodeGenTarget &Target = CDP.getTargetInfo();
144 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
145 E = Target.inst_end(); II != E; ++II) {
146 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
147 unsigned &N = OperandInfoIDs[OperandInfo];
148 if (N != 0) continue;
149
150 N = ++OperandListNum;
151 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
152 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
153 OS << "{ " << OperandInfo[i] << " }, ";
154 OS << "};\n";
155 }
156 }
157
158 //===----------------------------------------------------------------------===//
159 // Main Output.
160 //===----------------------------------------------------------------------===//
161
162 // run - Emit the main instruction description records for the target...
run(raw_ostream & OS)163 void InstrInfoEmitter::run(raw_ostream &OS) {
164 emitEnums(OS);
165
166 GatherItinClasses();
167
168 EmitSourceFileHeader("Target Instruction Descriptors", OS);
169
170 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
171 OS << "#undef GET_INSTRINFO_MC_DESC\n";
172
173 OS << "namespace llvm {\n\n";
174
175 CodeGenTarget &Target = CDP.getTargetInfo();
176 const std::string &TargetName = Target.getName();
177 Record *InstrInfo = Target.getInstructionSet();
178
179 // Keep track of all of the def lists we have emitted already.
180 std::map<std::vector<Record*>, unsigned> EmittedLists;
181 unsigned ListNumber = 0;
182
183 // Emit all of the instruction's implicit uses and defs.
184 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
185 E = Target.inst_end(); II != E; ++II) {
186 Record *Inst = (*II)->TheDef;
187 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
188 if (!Uses.empty()) {
189 unsigned &IL = EmittedLists[Uses];
190 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
191 }
192 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
193 if (!Defs.empty()) {
194 unsigned &IL = EmittedLists[Defs];
195 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
196 }
197 }
198
199 OperandInfoMapTy OperandInfoIDs;
200
201 // Emit all of the operand info records.
202 EmitOperandInfo(OS, OperandInfoIDs);
203
204 // Emit all of the MCInstrDesc records in their ENUM ordering.
205 //
206 OS << "\nMCInstrDesc " << TargetName << "Insts[] = {\n";
207 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
208 Target.getInstructionsByEnumValue();
209
210 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
211 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
212 OperandInfoIDs, OS);
213 OS << "};\n\n";
214
215 // MCInstrInfo initialization routine.
216 OS << "static inline void Init" << TargetName
217 << "MCInstrInfo(MCInstrInfo *II) {\n";
218 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
219 << NumberedInstructions.size() << ");\n}\n\n";
220
221 OS << "} // End llvm namespace \n";
222
223 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
224
225 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
226 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
227 OS << "#undef GET_INSTRINFO_HEADER\n";
228
229 std::string ClassName = TargetName + "GenInstrInfo";
230 OS << "namespace llvm {\n";
231 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
232 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
233 << "};\n";
234 OS << "} // End llvm namespace \n";
235
236 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
237
238 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
239 OS << "#undef GET_INSTRINFO_CTOR\n";
240
241 OS << "namespace llvm {\n";
242 OS << "extern MCInstrDesc " << TargetName << "Insts[];\n";
243 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
244 << " : TargetInstrInfoImpl(SO, DO) {\n"
245 << " InitMCInstrInfo(" << TargetName << "Insts, "
246 << NumberedInstructions.size() << ");\n}\n";
247 OS << "} // End llvm namespace \n";
248
249 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
250 }
251
emitRecord(const CodeGenInstruction & Inst,unsigned Num,Record * InstrInfo,std::map<std::vector<Record * >,unsigned> & EmittedLists,const OperandInfoMapTy & OpInfo,raw_ostream & OS)252 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
253 Record *InstrInfo,
254 std::map<std::vector<Record*>, unsigned> &EmittedLists,
255 const OperandInfoMapTy &OpInfo,
256 raw_ostream &OS) {
257 int MinOperands = 0;
258 if (!Inst.Operands.size() == 0)
259 // Each logical operand can be multiple MI operands.
260 MinOperands = Inst.Operands.back().MIOperandNo +
261 Inst.Operands.back().MINumOperands;
262
263 OS << " { ";
264 OS << Num << ",\t" << MinOperands << ",\t"
265 << Inst.Operands.NumDefs << ",\t"
266 << getItinClassNumber(Inst.TheDef) << ",\t"
267 << Inst.TheDef->getValueAsInt("Size") << ",\t\""
268 << Inst.TheDef->getName() << "\", 0";
269
270 // Emit all of the target indepedent flags...
271 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
272 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
273 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
274 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
275 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
276 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
277 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
278 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
279 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
280 if (Inst.isCall) OS << "|(1<<MCID::Call)";
281 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
282 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
283 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
284 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
285 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
286 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
287 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
288 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
289 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
290 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
291 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
292 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
293 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
294 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
295 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
296 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
297 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
298
299 // Emit all of the target-specific flags...
300 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
301 if (!TSF) throw "no TSFlags?";
302 uint64_t Value = 0;
303 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
304 if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
305 Value |= uint64_t(Bit->getValue()) << i;
306 else
307 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
308 }
309 OS << ", 0x";
310 OS.write_hex(Value);
311 OS << "ULL, ";
312
313 // Emit the implicit uses and defs lists...
314 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
315 if (UseList.empty())
316 OS << "NULL, ";
317 else
318 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
319
320 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
321 if (DefList.empty())
322 OS << "NULL, ";
323 else
324 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
325
326 // Emit the operand info.
327 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
328 if (OperandInfo.empty())
329 OS << "0";
330 else
331 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
332
333 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
334 }
335
336 // emitEnums - Print out enum values for all of the instructions.
emitEnums(raw_ostream & OS)337 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
338 EmitSourceFileHeader("Target Instruction Enum Values", OS);
339
340 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
341 OS << "#undef GET_INSTRINFO_ENUM\n";
342
343 OS << "namespace llvm {\n\n";
344
345 CodeGenTarget Target(Records);
346
347 // We must emit the PHI opcode first...
348 std::string Namespace = Target.getInstNamespace();
349
350 if (Namespace.empty()) {
351 fprintf(stderr, "No instructions defined!\n");
352 exit(1);
353 }
354
355 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
356 Target.getInstructionsByEnumValue();
357
358 OS << "namespace " << Namespace << " {\n";
359 OS << " enum {\n";
360 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
361 OS << " " << NumberedInstructions[i]->TheDef->getName()
362 << "\t= " << i << ",\n";
363 }
364 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
365 OS << " };\n}\n";
366 OS << "} // End llvm namespace \n";
367
368 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
369 }
370