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1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
12 
13 #include "llvm/Support/DataTypes.h"
14 
15 namespace llvm {
16 
17 class MCAsmBackend;
18 class MCCodeEmitter;
19 class MCContext;
20 class MCInstrInfo;
21 class MCObjectWriter;
22 class MCRegisterInfo;
23 class MCSubtargetInfo;
24 class StringRef;
25 class Target;
26 class Triple;
27 class raw_pwrite_stream;
28 class raw_ostream;
29 
30 extern Target TheSystemZTarget;
31 
32 namespace SystemZMC {
33 // How many bytes are in the ABI-defined, caller-allocated part of
34 // a stack frame.
35 const int64_t CallFrameSize = 160;
36 
37 // The offset of the DWARF CFA from the incoming stack pointer.
38 const int64_t CFAOffsetFromInitialSP = CallFrameSize;
39 
40 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
41 // an invalid register.  In principle we could use 32-bit and 64-bit register
42 // classes directly, provided that we relegated the GPR allocation order
43 // in SystemZRegisterInfo.td to an AltOrder and left the default order
44 // as %r0-%r15.  It seems better to provide the same interface for
45 // all classes though.
46 extern const unsigned GR32Regs[16];
47 extern const unsigned GRH32Regs[16];
48 extern const unsigned GR64Regs[16];
49 extern const unsigned GR128Regs[16];
50 extern const unsigned FP32Regs[16];
51 extern const unsigned FP64Regs[16];
52 extern const unsigned FP128Regs[16];
53 extern const unsigned VR32Regs[32];
54 extern const unsigned VR64Regs[32];
55 extern const unsigned VR128Regs[32];
56 
57 // Return the 0-based number of the first architectural register that
58 // contains the given LLVM register.   E.g. R1D -> 1.
59 unsigned getFirstReg(unsigned Reg);
60 
61 // Return the given register as a GR64.
getRegAsGR64(unsigned Reg)62 inline unsigned getRegAsGR64(unsigned Reg) {
63   return GR64Regs[getFirstReg(Reg)];
64 }
65 
66 // Return the given register as a low GR32.
getRegAsGR32(unsigned Reg)67 inline unsigned getRegAsGR32(unsigned Reg) {
68   return GR32Regs[getFirstReg(Reg)];
69 }
70 
71 // Return the given register as a high GR32.
getRegAsGRH32(unsigned Reg)72 inline unsigned getRegAsGRH32(unsigned Reg) {
73   return GRH32Regs[getFirstReg(Reg)];
74 }
75 
76 // Return the given register as a VR128.
getRegAsVR128(unsigned Reg)77 inline unsigned getRegAsVR128(unsigned Reg) {
78   return VR128Regs[getFirstReg(Reg)];
79 }
80 } // end namespace SystemZMC
81 
82 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
83                                           const MCRegisterInfo &MRI,
84                                           MCContext &Ctx);
85 
86 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
87                                         const MCRegisterInfo &MRI,
88                                         const Triple &TT, StringRef CPU);
89 
90 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
91 } // end namespace llvm
92 
93 // Defines symbolic names for SystemZ registers.
94 // This defines a mapping from register name to register number.
95 #define GET_REGINFO_ENUM
96 #include "SystemZGenRegisterInfo.inc"
97 
98 // Defines symbolic names for the SystemZ instructions.
99 #define GET_INSTRINFO_ENUM
100 #include "SystemZGenInstrInfo.inc"
101 
102 #define GET_SUBTARGETINFO_ENUM
103 #include "SystemZGenSubtargetInfo.inc"
104 
105 #endif
106