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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBankInfo class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/iterator_range.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetOpcodes.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
28 
29 #include <algorithm> // For std::max.
30 
31 #define DEBUG_TYPE "registerbankinfo"
32 
33 using namespace llvm;
34 
35 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
36 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
37 
38 //------------------------------------------------------------------------------
39 // RegisterBankInfo implementation.
40 //------------------------------------------------------------------------------
RegisterBankInfo(unsigned NumRegBanks)41 RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
42     : NumRegBanks(NumRegBanks) {
43   RegBanks.reset(new RegisterBank[NumRegBanks]);
44 }
45 
verify(const TargetRegisterInfo & TRI) const46 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
47   DEBUG(for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
48     const RegisterBank &RegBank = getRegBank(Idx);
49     assert(Idx == RegBank.getID() &&
50            "ID does not match the index in the array");
51     dbgs() << "Verify " << RegBank << '\n';
52     assert(RegBank.verify(TRI) && "RegBank is invalid");
53   });
54   return true;
55 }
56 
createRegisterBank(unsigned ID,const char * Name)57 void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) {
58   DEBUG(dbgs() << "Create register bank: " << ID << " with name \"" << Name
59                << "\"\n");
60   RegisterBank &RegBank = getRegBank(ID);
61   assert(RegBank.getID() == RegisterBank::InvalidID &&
62          "A register bank should be created only once");
63   RegBank.ID = ID;
64   RegBank.Name = Name;
65 }
66 
addRegBankCoverage(unsigned ID,unsigned RCId,const TargetRegisterInfo & TRI,bool AddTypeMapping)67 void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
68                                           const TargetRegisterInfo &TRI,
69                                           bool AddTypeMapping) {
70   RegisterBank &RB = getRegBank(ID);
71   unsigned NbOfRegClasses = TRI.getNumRegClasses();
72 
73   DEBUG(dbgs() << "Add coverage for: " << RB << '\n');
74 
75   // Check if RB is underconstruction.
76   if (!RB.isValid())
77     RB.ContainedRegClasses.resize(NbOfRegClasses);
78   else if (RB.covers(*TRI.getRegClass(RCId)))
79     // If RB already covers this register class, there is nothing
80     // to do.
81     return;
82 
83   BitVector &Covered = RB.ContainedRegClasses;
84   SmallVector<unsigned, 8> WorkList;
85 
86   WorkList.push_back(RCId);
87   Covered.set(RCId);
88 
89   unsigned &MaxSize = RB.Size;
90   do {
91     unsigned RCId = WorkList.pop_back_val();
92 
93     const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId);
94 
95     DEBUG(dbgs() << "Examine: " << TRI.getRegClassName(&CurRC)
96                  << "(Size*8: " << (CurRC.getSize() * 8) << ")\n");
97 
98     // Remember the biggest size in bits.
99     MaxSize = std::max(MaxSize, CurRC.getSize() * 8);
100 
101     // If we have been asked to record the type supported by this
102     // register bank, do it now.
103     if (AddTypeMapping)
104       for (MVT::SimpleValueType SVT :
105            make_range(CurRC.vt_begin(), CurRC.vt_end()))
106         recordRegBankForType(getRegBank(ID), SVT);
107 
108     // Walk through all sub register classes and push them into the worklist.
109     bool First = true;
110     for (BitMaskClassIterator It(CurRC.getSubClassMask(), TRI); It.isValid();
111          ++It) {
112       unsigned SubRCId = It.getID();
113       if (!Covered.test(SubRCId)) {
114         if (First)
115           DEBUG(dbgs() << "  Enqueue sub-class: ");
116         DEBUG(dbgs() << TRI.getRegClassName(TRI.getRegClass(SubRCId)) << ", ");
117         WorkList.push_back(SubRCId);
118         // Remember that we saw the sub class.
119         Covered.set(SubRCId);
120         First = false;
121       }
122     }
123     if (!First)
124       DEBUG(dbgs() << '\n');
125 
126     // Push also all the register classes that can be accessed via a
127     // subreg index, i.e., its subreg-class (which is different than
128     // its subclass).
129     //
130     // Note: It would probably be faster to go the other way around
131     // and have this method add only super classes, since this
132     // information is available in a more efficient way. However, it
133     // feels less natural for the client of this APIs plus we will
134     // TableGen the whole bitset at some point, so compile time for
135     // the initialization is not very important.
136     First = true;
137     for (unsigned SubRCId = 0; SubRCId < NbOfRegClasses; ++SubRCId) {
138       if (Covered.test(SubRCId))
139         continue;
140       bool Pushed = false;
141       const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId);
142       for (SuperRegClassIterator SuperRCIt(SubRC, &TRI); SuperRCIt.isValid();
143            ++SuperRCIt) {
144         if (Pushed)
145           break;
146         for (BitMaskClassIterator It(SuperRCIt.getMask(), TRI); It.isValid();
147              ++It) {
148           unsigned SuperRCId = It.getID();
149           if (SuperRCId == RCId) {
150             if (First)
151               DEBUG(dbgs() << "  Enqueue subreg-class: ");
152             DEBUG(dbgs() << TRI.getRegClassName(SubRC) << ", ");
153             WorkList.push_back(SubRCId);
154             // Remember that we saw the sub class.
155             Covered.set(SubRCId);
156             Pushed = true;
157             First = false;
158             break;
159           }
160         }
161       }
162     }
163     if (!First)
164       DEBUG(dbgs() << '\n');
165   } while (!WorkList.empty());
166 }
167 
168 const RegisterBank *
getRegBank(unsigned Reg,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const169 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
170                              const TargetRegisterInfo &TRI) const {
171   if (TargetRegisterInfo::isPhysicalRegister(Reg))
172     return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg));
173 
174   assert(Reg && "NoRegister does not have a register bank");
175   const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
176   if (RegClassOrBank.is<const RegisterBank *>())
177     return RegClassOrBank.get<const RegisterBank *>();
178   const TargetRegisterClass *RC =
179       RegClassOrBank.get<const TargetRegisterClass *>();
180   if (RC)
181     return &getRegBankFromRegClass(*RC);
182   return nullptr;
183 }
184 
getRegBankFromConstraints(const MachineInstr & MI,unsigned OpIdx,const TargetInstrInfo & TII,const TargetRegisterInfo & TRI) const185 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
186     const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
187     const TargetRegisterInfo &TRI) const {
188   // The mapping of the registers may be available via the
189   // register class constraints.
190   const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
191 
192   if (!RC)
193     return nullptr;
194 
195   const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
196   // Sanity check that the target properly implemented getRegBankFromRegClass.
197   assert(RegBank.covers(*RC) &&
198          "The mapping of the register bank does not make sense");
199   return &RegBank;
200 }
201 
202 RegisterBankInfo::InstructionMapping
getInstrMappingImpl(const MachineInstr & MI) const203 RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
204   RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
205                                                MI.getNumOperands());
206   const MachineFunction &MF = *MI.getParent()->getParent();
207   const TargetSubtargetInfo &STI = MF.getSubtarget();
208   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
209   const MachineRegisterInfo &MRI = MF.getRegInfo();
210   // We may need to query the instruction encoding to guess the mapping.
211   const TargetInstrInfo &TII = *STI.getInstrInfo();
212 
213   // Before doing anything complicated check if the mapping is not
214   // directly available.
215   bool CompleteMapping = true;
216   // For copies we want to walk over the operands and try to find one
217   // that has a register bank.
218   bool isCopyLike = MI.isCopy() || MI.isPHI();
219   // Remember the register bank for reuse for copy-like instructions.
220   const RegisterBank *RegBank = nullptr;
221   // Remember the size of the register for reuse for copy-like instructions.
222   unsigned RegSize = 0;
223   for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
224     const MachineOperand &MO = MI.getOperand(OpIdx);
225     if (!MO.isReg())
226       continue;
227     unsigned Reg = MO.getReg();
228     if (!Reg)
229       continue;
230     // The register bank of Reg is just a side effect of the current
231     // excution and in particular, there is no reason to believe this
232     // is the best default mapping for the current instruction.  Keep
233     // it as an alternative register bank if we cannot figure out
234     // something.
235     const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
236     // For copy-like instruction, we want to reuse the register bank
237     // that is already set on Reg, if any, since those instructions do
238     // not have any constraints.
239     const RegisterBank *CurRegBank = isCopyLike ? AltRegBank : nullptr;
240     if (!CurRegBank) {
241       // If this is a target specific instruction, we can deduce
242       // the register bank from the encoding constraints.
243       CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
244       if (!CurRegBank) {
245         // Check if we can deduce the register bank from the type of
246         // the instruction.
247         Type *MITy = MI.getType();
248         if (MITy)
249           CurRegBank = getRegBankForType(
250               MVT::getVT(MITy, /*HandleUnknown*/ true).SimpleTy);
251         if (!CurRegBank)
252           // Use the current assigned register bank.
253           // That may not make much sense though.
254           CurRegBank = AltRegBank;
255         if (!CurRegBank) {
256           // All our attempts failed, give up.
257           CompleteMapping = false;
258 
259           if (!isCopyLike)
260             // MI does not carry enough information to guess the mapping.
261             return InstructionMapping();
262 
263           // For copies, we want to keep interating to find a register
264           // bank for the other operands if we did not find one yet.
265           if (RegBank)
266             break;
267           continue;
268         }
269       }
270     }
271     RegBank = CurRegBank;
272     RegSize = getSizeInBits(Reg, MRI, TRI);
273     Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank);
274   }
275 
276   if (CompleteMapping)
277     return Mapping;
278 
279   assert(isCopyLike && "We should have bailed on non-copies at this point");
280   // For copy like instruction, if none of the operand has a register
281   // bank avialable, there is nothing we can propagate.
282   if (!RegBank)
283     return InstructionMapping();
284 
285   // This is a copy-like instruction.
286   // Propagate RegBank to all operands that do not have a
287   // mapping yet.
288   for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
289     const MachineOperand &MO = MI.getOperand(OpIdx);
290     // Don't assign a mapping for non-reg operands.
291     if (!MO.isReg())
292       continue;
293 
294     // If a mapping already exists, do not touch it.
295     if (!static_cast<const InstructionMapping *>(&Mapping)
296              ->getOperandMapping(OpIdx)
297              .BreakDown.empty())
298       continue;
299 
300     Mapping.setOperandMapping(OpIdx, RegSize, *RegBank);
301   }
302   return Mapping;
303 }
304 
305 RegisterBankInfo::InstructionMapping
getInstrMapping(const MachineInstr & MI) const306 RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
307     RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
308     if (Mapping.isValid())
309       return Mapping;
310   llvm_unreachable("The target must implement this");
311 }
312 
313 RegisterBankInfo::InstructionMappings
getInstrPossibleMappings(const MachineInstr & MI) const314 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
315   InstructionMappings PossibleMappings;
316   // Put the default mapping first.
317   PossibleMappings.push_back(getInstrMapping(MI));
318   // Then the alternative mapping, if any.
319   InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
320   for (InstructionMapping &AltMapping : AltMappings)
321     PossibleMappings.emplace_back(std::move(AltMapping));
322 #ifndef NDEBUG
323   for (const InstructionMapping &Mapping : PossibleMappings)
324     assert(Mapping.verify(MI) && "Mapping is invalid");
325 #endif
326   return PossibleMappings;
327 }
328 
329 RegisterBankInfo::InstructionMappings
getInstrAlternativeMappings(const MachineInstr & MI) const330 RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
331   // No alternative for MI.
332   return InstructionMappings();
333 }
334 
applyDefaultMapping(const OperandsMapper & OpdMapper)335 void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
336   MachineInstr &MI = OpdMapper.getMI();
337   DEBUG(dbgs() << "Applying default-like mapping\n");
338   for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
339        ++OpIdx) {
340     DEBUG(dbgs() << "OpIdx " << OpIdx);
341     MachineOperand &MO = MI.getOperand(OpIdx);
342     if (!MO.isReg()) {
343       DEBUG(dbgs() << " is not a register, nothing to be done\n");
344       continue;
345     }
346     assert(
347         OpdMapper.getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() ==
348             1 &&
349         "This mapping is too complex for this function");
350     iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs =
351         OpdMapper.getVRegs(OpIdx);
352     if (NewRegs.begin() == NewRegs.end()) {
353       DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
354       continue;
355     }
356     DEBUG(dbgs() << " changed, replace " << MO.getReg());
357     MO.setReg(*NewRegs.begin());
358     DEBUG(dbgs() << " with " << MO.getReg());
359   }
360 }
361 
getSizeInBits(unsigned Reg,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI)362 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
363                                          const MachineRegisterInfo &MRI,
364                                          const TargetRegisterInfo &TRI) {
365   const TargetRegisterClass *RC = nullptr;
366   if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
367     // The size is not directly available for physical registers.
368     // Instead, we need to access a register class that contains Reg and
369     // get the size of that register class.
370     RC = TRI.getMinimalPhysRegClass(Reg);
371   } else {
372     unsigned RegSize = MRI.getSize(Reg);
373     // If Reg is not a generic register, query the register class to
374     // get its size.
375     if (RegSize)
376       return RegSize;
377     // Since Reg is not a generic register, it must have a register class.
378     RC = MRI.getRegClass(Reg);
379   }
380   assert(RC && "Unable to deduce the register class");
381   return RC->getSize() * 8;
382 }
383 
384 //------------------------------------------------------------------------------
385 // Helper classes implementation.
386 //------------------------------------------------------------------------------
dump() const387 void RegisterBankInfo::PartialMapping::dump() const {
388   print(dbgs());
389   dbgs() << '\n';
390 }
391 
verify() const392 bool RegisterBankInfo::PartialMapping::verify() const {
393   assert(RegBank && "Register bank not set");
394   assert(Length && "Empty mapping");
395   assert((StartIdx < getHighBitIdx()) && "Overflow, switch to APInt?");
396   // Check if the minimum width fits into RegBank.
397   assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
398   return true;
399 }
400 
print(raw_ostream & OS) const401 void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
402   OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
403   if (RegBank)
404     OS << *RegBank;
405   else
406     OS << "nullptr";
407 }
408 
verify(unsigned ExpectedBitWidth) const409 bool RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
410   assert(!BreakDown.empty() && "Value mapped nowhere?!");
411   unsigned OrigValueBitWidth = 0;
412   for (const RegisterBankInfo::PartialMapping &PartMap : BreakDown) {
413     // Check that each register bank is big enough to hold the partial value:
414     // this check is done by PartialMapping::verify
415     assert(PartMap.verify() && "Partial mapping is invalid");
416     // The original value should completely be mapped.
417     // Thus the maximum accessed index + 1 is the size of the original value.
418     OrigValueBitWidth =
419         std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
420   }
421   assert(OrigValueBitWidth == ExpectedBitWidth && "BitWidth does not match");
422   APInt ValueMask(OrigValueBitWidth, 0);
423   for (const RegisterBankInfo::PartialMapping &PartMap : BreakDown) {
424     // Check that the union of the partial mappings covers the whole value,
425     // without overlaps.
426     // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
427     APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
428                                           PartMap.getHighBitIdx() + 1);
429     ValueMask ^= PartMapMask;
430     assert((ValueMask & PartMapMask) == PartMapMask &&
431            "Some partial mappings overlap");
432   }
433   assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
434   return true;
435 }
436 
dump() const437 void RegisterBankInfo::ValueMapping::dump() const {
438   print(dbgs());
439   dbgs() << '\n';
440 }
441 
print(raw_ostream & OS) const442 void RegisterBankInfo::ValueMapping::print(raw_ostream &OS) const {
443   OS << "#BreakDown: " << BreakDown.size() << " ";
444   bool IsFirst = true;
445   for (const PartialMapping &PartMap : BreakDown) {
446     if (!IsFirst)
447       OS << ", ";
448     OS << '[' << PartMap << ']';
449     IsFirst = false;
450   }
451 }
452 
setOperandMapping(unsigned OpIdx,unsigned MaskSize,const RegisterBank & RegBank)453 void RegisterBankInfo::InstructionMapping::setOperandMapping(
454     unsigned OpIdx, unsigned MaskSize, const RegisterBank &RegBank) {
455   // Build the value mapping.
456   assert(MaskSize <= RegBank.getSize() && "Register bank is too small");
457 
458   // Create the mapping object.
459   getOperandMapping(OpIdx).BreakDown.push_back(
460       PartialMapping(0, MaskSize, RegBank));
461 }
462 
verify(const MachineInstr & MI) const463 bool RegisterBankInfo::InstructionMapping::verify(
464     const MachineInstr &MI) const {
465   // Check that all the register operands are properly mapped.
466   // Check the constructor invariant.
467   assert(NumOperands == MI.getNumOperands() &&
468          "NumOperands must match, see constructor");
469   assert(MI.getParent() && MI.getParent()->getParent() &&
470          "MI must be connected to a MachineFunction");
471   const MachineFunction &MF = *MI.getParent()->getParent();
472   (void)MF;
473 
474   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
475     const MachineOperand &MO = MI.getOperand(Idx);
476     const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
477     (void)MOMapping;
478     if (!MO.isReg()) {
479       assert(MOMapping.BreakDown.empty() &&
480              "We should not care about non-reg mapping");
481       continue;
482     }
483     unsigned Reg = MO.getReg();
484     if (!Reg)
485       continue;
486     // Register size in bits.
487     // This size must match what the mapping expects.
488     assert(MOMapping.verify(getSizeInBits(
489                Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
490            "Value mapping is invalid");
491   }
492   return true;
493 }
494 
dump() const495 void RegisterBankInfo::InstructionMapping::dump() const {
496   print(dbgs());
497   dbgs() << '\n';
498 }
499 
print(raw_ostream & OS) const500 void RegisterBankInfo::InstructionMapping::print(raw_ostream &OS) const {
501   OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
502 
503   for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
504     const ValueMapping &ValMapping = getOperandMapping(OpIdx);
505     if (OpIdx)
506       OS << ", ";
507     OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
508   }
509 }
510 
511 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
512 
OperandsMapper(MachineInstr & MI,const InstructionMapping & InstrMapping,MachineRegisterInfo & MRI)513 RegisterBankInfo::OperandsMapper::OperandsMapper(
514     MachineInstr &MI, const InstructionMapping &InstrMapping,
515     MachineRegisterInfo &MRI)
516     : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
517   unsigned NumOpds = MI.getNumOperands();
518   OpToNewVRegIdx.reset(new int[NumOpds]);
519   std::fill(&OpToNewVRegIdx[0], &OpToNewVRegIdx[NumOpds],
520             OperandsMapper::DontKnowIdx);
521   assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
522 }
523 
524 iterator_range<SmallVectorImpl<unsigned>::iterator>
getVRegsMem(unsigned OpIdx)525 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
526   assert(OpIdx < getMI().getNumOperands() && "Out-of-bound access");
527   unsigned NumPartialVal =
528       getInstrMapping().getOperandMapping(OpIdx).BreakDown.size();
529   int StartIdx = OpToNewVRegIdx[OpIdx];
530 
531   if (StartIdx == OperandsMapper::DontKnowIdx) {
532     // This is the first time we try to access OpIdx.
533     // Create the cells that will hold all the partial values at the
534     // end of the list of NewVReg.
535     StartIdx = NewVRegs.size();
536     OpToNewVRegIdx[OpIdx] = StartIdx;
537     for (unsigned i = 0; i < NumPartialVal; ++i)
538       NewVRegs.push_back(0);
539   }
540   SmallVectorImpl<unsigned>::iterator End =
541       getNewVRegsEnd(StartIdx, NumPartialVal);
542 
543   return make_range(&NewVRegs[StartIdx], End);
544 }
545 
546 SmallVectorImpl<unsigned>::const_iterator
getNewVRegsEnd(unsigned StartIdx,unsigned NumVal) const547 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
548                                                  unsigned NumVal) const {
549   return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
550 }
551 SmallVectorImpl<unsigned>::iterator
getNewVRegsEnd(unsigned StartIdx,unsigned NumVal)552 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
553                                                  unsigned NumVal) {
554   assert((NewVRegs.size() == StartIdx + NumVal ||
555           NewVRegs.size() > StartIdx + NumVal) &&
556          "NewVRegs too small to contain all the partial mapping");
557   return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
558                                               : &NewVRegs[StartIdx + NumVal];
559 }
560 
createVRegs(unsigned OpIdx)561 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) {
562   assert(OpIdx < getMI().getNumOperands() && "Out-of-bound access");
563   iterator_range<SmallVectorImpl<unsigned>::iterator> NewVRegsForOpIdx =
564       getVRegsMem(OpIdx);
565   const SmallVectorImpl<PartialMapping> &PartMapList =
566       getInstrMapping().getOperandMapping(OpIdx).BreakDown;
567   SmallVectorImpl<PartialMapping>::const_iterator PartMap = PartMapList.begin();
568   for (unsigned &NewVReg : NewVRegsForOpIdx) {
569     assert(PartMap != PartMapList.end() && "Out-of-bound access");
570     assert(NewVReg == 0 && "Register has already been created");
571     NewVReg = MRI.createGenericVirtualRegister(PartMap->Length);
572     MRI.setRegBank(NewVReg, *PartMap->RegBank);
573     ++PartMap;
574   }
575 }
576 
setVRegs(unsigned OpIdx,unsigned PartialMapIdx,unsigned NewVReg)577 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx,
578                                                 unsigned PartialMapIdx,
579                                                 unsigned NewVReg) {
580   assert(OpIdx < getMI().getNumOperands() && "Out-of-bound access");
581   assert(getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
582              PartialMapIdx &&
583          "Out-of-bound access for partial mapping");
584   // Make sure the memory is initialized for that operand.
585   (void)getVRegsMem(OpIdx);
586   assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
587          "This value is already set");
588   NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
589 }
590 
591 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
getVRegs(unsigned OpIdx,bool ForDebug) const592 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx,
593                                            bool ForDebug) const {
594   (void)ForDebug;
595   assert(OpIdx < getMI().getNumOperands() && "Out-of-bound access");
596   int StartIdx = OpToNewVRegIdx[OpIdx];
597 
598   if (StartIdx == OperandsMapper::DontKnowIdx)
599     return make_range(NewVRegs.end(), NewVRegs.end());
600 
601   unsigned PartMapSize =
602       getInstrMapping().getOperandMapping(OpIdx).BreakDown.size();
603   SmallVectorImpl<unsigned>::const_iterator End =
604       getNewVRegsEnd(StartIdx, PartMapSize);
605   iterator_range<SmallVectorImpl<unsigned>::const_iterator> Res =
606       make_range(&NewVRegs[StartIdx], End);
607 #ifndef NDEBUG
608   for (unsigned VReg : Res)
609     assert((VReg || ForDebug) && "Some registers are uninitialized");
610 #endif
611   return Res;
612 }
613 
dump() const614 void RegisterBankInfo::OperandsMapper::dump() const {
615   print(dbgs(), true);
616   dbgs() << '\n';
617 }
618 
print(raw_ostream & OS,bool ForDebug) const619 void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS,
620                                              bool ForDebug) const {
621   unsigned NumOpds = getMI().getNumOperands();
622   if (ForDebug) {
623     OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
624     // Print out the internal state of the index table.
625     OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
626     bool IsFirst = true;
627     for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
628       if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
629         if (!IsFirst)
630           OS << ", ";
631         OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
632         IsFirst = false;
633       }
634     }
635     OS << '\n';
636   } else
637     OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
638 
639   OS << "Operand Mapping: ";
640   // If we have a function, we can pretty print the name of the registers.
641   // Otherwise we will print the raw numbers.
642   const TargetRegisterInfo *TRI =
643       getMI().getParent() && getMI().getParent()->getParent()
644           ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo()
645           : nullptr;
646   bool IsFirst = true;
647   for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
648     if (OpToNewVRegIdx[Idx] == DontKnowIdx)
649       continue;
650     if (!IsFirst)
651       OS << ", ";
652     IsFirst = false;
653     OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
654     bool IsFirstNewVReg = true;
655     for (unsigned VReg : getVRegs(Idx)) {
656       if (!IsFirstNewVReg)
657         OS << ", ";
658       IsFirstNewVReg = false;
659       OS << PrintReg(VReg, TRI);
660     }
661     OS << "])";
662   }
663 }
664