1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #ifndef IR3_SHADER_H_
30 #define IR3_SHADER_H_
31
32 #include "pipe/p_state.h"
33 #include "compiler/shader_enums.h"
34 #include "util/bitscan.h"
35
36 #include "ir3.h"
37 #include "disasm.h"
38
39 /* driver param indices: */
40 enum ir3_driver_param {
41 IR3_DP_VTXID_BASE = 0,
42 IR3_DP_VTXCNT_MAX = 1,
43 /* user-clip-plane components, up to 8x vec4's: */
44 IR3_DP_UCP0_X = 4,
45 /* .... */
46 IR3_DP_UCP7_W = 35,
47 IR3_DP_COUNT = 36 /* must be aligned to vec4 */
48 };
49
50 /* Configuration key used to identify a shader variant.. different
51 * shader variants can be used to implement features not supported
52 * in hw (two sided color), binning-pass vertex shader, etc.
53 */
54 struct ir3_shader_key {
55 union {
56 struct {
57 /*
58 * Combined Vertex/Fragment shader parameters:
59 */
60 unsigned ucp_enables : 8;
61
62 /* do we need to check {v,f}saturate_{s,t,r}? */
63 unsigned has_per_samp : 1;
64
65 /*
66 * Vertex shader variant parameters:
67 */
68 unsigned binning_pass : 1;
69 unsigned vclamp_color : 1;
70
71 /*
72 * Fragment shader variant parameters:
73 */
74 unsigned color_two_side : 1;
75 unsigned half_precision : 1;
76 /* used when shader needs to handle flat varyings (a4xx)
77 * for front/back color inputs to frag shader:
78 */
79 unsigned rasterflat : 1;
80 unsigned fclamp_color : 1;
81 };
82 uint32_t global;
83 };
84
85 /* bitmask of sampler which needs coords clamped for vertex
86 * shader:
87 */
88 uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
89
90 /* bitmask of sampler which needs coords clamped for frag
91 * shader:
92 */
93 uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
94
95 /* bitmask of samplers which need astc srgb workaround: */
96 uint16_t vastc_srgb, fastc_srgb;
97 };
98
99 static inline bool
ir3_shader_key_equal(struct ir3_shader_key * a,struct ir3_shader_key * b)100 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
101 {
102 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
103 if (a->has_per_samp || b->has_per_samp)
104 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
105 return a->global == b->global;
106 }
107
108 struct ir3_shader_variant {
109 struct fd_bo *bo;
110
111 /* variant id (for debug) */
112 uint32_t id;
113
114 struct ir3_shader_key key;
115
116 struct ir3_info info;
117 struct ir3 *ir;
118
119 /* the instructions length is in units of instruction groups
120 * (4 instructions for a3xx, 16 instructions for a4xx.. each
121 * instruction is 2 dwords):
122 */
123 unsigned instrlen;
124
125 /* the constants length is in units of vec4's, and is the sum of
126 * the uniforms and the built-in compiler constants
127 */
128 unsigned constlen;
129
130 /* number of uniforms (in vec4), not including built-in compiler
131 * constants, etc.
132 */
133 unsigned num_uniforms;
134 unsigned num_ubos;
135
136 /* About Linkage:
137 * + Let the frag shader determine the position/compmask for the
138 * varyings, since it is the place where we know if the varying
139 * is actually used, and if so, which components are used. So
140 * what the hw calls "outloc" is taken from the "inloc" of the
141 * frag shader.
142 * + From the vert shader, we only need the output regid
143 */
144
145 /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
146 * to bary.f instructions
147 */
148 uint8_t pos_regid;
149 bool frag_coord, frag_face, color0_mrt;
150
151 /* NOTE: for input/outputs, slot is:
152 * gl_vert_attrib - for VS inputs
153 * gl_varying_slot - for VS output / FS input
154 * gl_frag_result - for FS output
155 */
156
157 /* varyings/outputs: */
158 unsigned outputs_count;
159 struct {
160 uint8_t slot;
161 uint8_t regid;
162 } outputs[16 + 2]; /* +POSITION +PSIZE */
163 bool writes_pos, writes_psize;
164
165 /* attributes (VS) / varyings (FS):
166 * Note that sysval's should come *after* normal inputs.
167 */
168 unsigned inputs_count;
169 struct {
170 uint8_t slot;
171 uint8_t regid;
172 uint8_t compmask;
173 uint8_t ncomp;
174 /* location of input (ie. offset passed to bary.f, etc). This
175 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
176 * have the OUTLOCn value offset by 8, presumably to account
177 * for gl_Position/gl_PointSize)
178 */
179 uint8_t inloc;
180 /* vertex shader specific: */
181 bool sysval : 1; /* slot is a gl_system_value */
182 /* fragment shader specific: */
183 bool bary : 1; /* fetched varying (vs one loaded into reg) */
184 bool rasterflat : 1; /* special handling for emit->rasterflat */
185 enum glsl_interp_mode interpolate;
186 } inputs[16 + 2]; /* +POSITION +FACE */
187
188 /* sum of input components (scalar). For frag shaders, it only counts
189 * the varying inputs:
190 */
191 unsigned total_in;
192
193 /* For frag shaders, the total number of inputs (not scalar,
194 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
195 */
196 unsigned varying_in;
197
198 /* do we have one or more texture sample instructions: */
199 bool has_samp;
200
201 /* do we have kill instructions: */
202 bool has_kill;
203
204 /* Layout of constant registers, each section (in vec4). Pointer size
205 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
206 * UBO and stream-out consts.
207 */
208 struct {
209 /* user const start at zero */
210 unsigned ubo;
211 unsigned driver_param;
212 unsigned tfbo;
213 unsigned immediate;
214 } constbase;
215
216 unsigned immediates_count;
217 struct {
218 uint32_t val[4];
219 } immediates[64];
220
221 /* for astc srgb workaround, the number/base of additional
222 * alpha tex states we need, and index of original tex states
223 */
224 struct {
225 unsigned base, count;
226 unsigned orig_idx[16];
227 } astc_srgb;
228
229 /* shader variants form a linked list: */
230 struct ir3_shader_variant *next;
231
232 /* replicated here to avoid passing extra ptrs everywhere: */
233 enum shader_t type;
234 struct ir3_shader *shader;
235 };
236
237 typedef struct nir_shader nir_shader;
238
239 struct ir3_shader {
240 enum shader_t type;
241
242 /* shader id (for debug): */
243 uint32_t id;
244 uint32_t variant_count;
245
246 /* so we know when we can disable TGSI related hacks: */
247 bool from_tgsi;
248
249 struct ir3_compiler *compiler;
250
251 nir_shader *nir;
252 struct pipe_stream_output_info stream_output;
253
254 struct ir3_shader_variant *variants;
255 };
256
257 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
258
259 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
260 const struct pipe_shader_state *cso, enum shader_t type,
261 struct pipe_debug_callback *debug);
262 void ir3_shader_destroy(struct ir3_shader *shader);
263 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
264 struct ir3_shader_key key, struct pipe_debug_callback *debug);
265 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
266 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
267
268 struct fd_ringbuffer;
269 struct fd_context;
270 void ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
271 struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty);
272
273 static inline const char *
ir3_shader_stage(struct ir3_shader * shader)274 ir3_shader_stage(struct ir3_shader *shader)
275 {
276 switch (shader->type) {
277 case SHADER_VERTEX: return "VERT";
278 case SHADER_FRAGMENT: return "FRAG";
279 case SHADER_COMPUTE: return "CL";
280 default:
281 unreachable("invalid type");
282 return NULL;
283 }
284 }
285
286 /*
287 * Helper/util:
288 */
289
290 #include "pipe/p_shader_tokens.h"
291
292 static inline int
ir3_find_output(const struct ir3_shader_variant * so,gl_varying_slot slot)293 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
294 {
295 int j;
296
297 for (j = 0; j < so->outputs_count; j++)
298 if (so->outputs[j].slot == slot)
299 return j;
300
301 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
302 * in the vertex shader.. but the fragment shader doesn't know this
303 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
304 * at link time if there is no matching OUT.BCOLOR[n], we must map
305 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
306 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
307 */
308 if (slot == VARYING_SLOT_BFC0) {
309 slot = VARYING_SLOT_COL0;
310 } else if (slot == VARYING_SLOT_BFC1) {
311 slot = VARYING_SLOT_COL1;
312 } else if (slot == VARYING_SLOT_COL0) {
313 slot = VARYING_SLOT_BFC0;
314 } else if (slot == VARYING_SLOT_COL1) {
315 slot = VARYING_SLOT_BFC1;
316 } else {
317 return 0;
318 }
319
320 for (j = 0; j < so->outputs_count; j++)
321 if (so->outputs[j].slot == slot)
322 return j;
323
324 debug_assert(0);
325
326 return 0;
327 }
328
329 static inline int
ir3_next_varying(const struct ir3_shader_variant * so,int i)330 ir3_next_varying(const struct ir3_shader_variant *so, int i)
331 {
332 while (++i < so->inputs_count)
333 if (so->inputs[i].compmask && so->inputs[i].bary)
334 break;
335 return i;
336 }
337
338 struct ir3_shader_linkage {
339 uint8_t max_loc;
340 uint8_t cnt;
341 struct {
342 uint8_t regid;
343 uint8_t compmask;
344 uint8_t loc;
345 } var[32];
346 };
347
348 static inline void
ir3_link_add(struct ir3_shader_linkage * l,uint8_t regid,uint8_t compmask,uint8_t loc)349 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
350 {
351 int i = l->cnt++;
352
353 debug_assert(i < ARRAY_SIZE(l->var));
354
355 l->var[i].regid = regid;
356 l->var[i].compmask = compmask;
357 l->var[i].loc = loc;
358 l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
359 }
360
361 static inline void
ir3_link_shaders(struct ir3_shader_linkage * l,const struct ir3_shader_variant * vs,const struct ir3_shader_variant * fs)362 ir3_link_shaders(struct ir3_shader_linkage *l,
363 const struct ir3_shader_variant *vs,
364 const struct ir3_shader_variant *fs)
365 {
366 int j = -1, k;
367
368 while (l->cnt < ARRAY_SIZE(l->var)) {
369 j = ir3_next_varying(fs, j);
370
371 if (j >= fs->inputs_count)
372 break;
373
374 if (fs->inputs[j].inloc >= fs->total_in)
375 continue;
376
377 k = ir3_find_output(vs, fs->inputs[j].slot);
378
379 ir3_link_add(l, vs->outputs[k].regid,
380 fs->inputs[j].compmask, fs->inputs[j].inloc);
381 }
382 }
383
384 static inline uint32_t
ir3_find_output_regid(const struct ir3_shader_variant * so,unsigned slot)385 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
386 {
387 int j;
388 for (j = 0; j < so->outputs_count; j++)
389 if (so->outputs[j].slot == slot)
390 return so->outputs[j].regid;
391 return regid(63, 0);
392 }
393
394 static inline uint32_t
ir3_find_sysval_regid(const struct ir3_shader_variant * so,unsigned slot)395 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
396 {
397 int j;
398 for (j = 0; j < so->inputs_count; j++)
399 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
400 return so->inputs[j].regid;
401 return regid(63, 0);
402 }
403
404 #endif /* IR3_SHADER_H_ */
405