1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_SAMPLES_LOG2 4
83 #define NUM_META_FS_KEYS 11
84 #define RADV_MAX_DRM_DEVICES 8
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103
104 enum {
105 RADV_DEBUG_FAST_CLEARS = 0x1,
106 RADV_DEBUG_NO_DCC = 0x2,
107 RADV_DEBUG_DUMP_SHADERS = 0x4,
108 RADV_DEBUG_NO_CACHE = 0x8,
109 RADV_DEBUG_DUMP_SHADER_STATS = 0x10,
110 RADV_DEBUG_NO_HIZ = 0x20,
111 RADV_DEBUG_NO_COMPUTE_QUEUE = 0x40,
112 RADV_DEBUG_UNSAFE_MATH = 0x80,
113 };
114
115 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116
117 static inline uint32_t
align_u32(uint32_t v,uint32_t a)118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint32_t
align_u32_npot(uint32_t v,uint32_t a)125 align_u32_npot(uint32_t v, uint32_t a)
126 {
127 return (v + a - 1) / a * a;
128 }
129
130 static inline uint64_t
align_u64(uint64_t v,uint64_t a)131 align_u64(uint64_t v, uint64_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline int32_t
align_i32(int32_t v,int32_t a)138 align_i32(int32_t v, int32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 /** Alignment must be a power of 2. */
145 static inline bool
radv_is_aligned(uintmax_t n,uintmax_t a)146 radv_is_aligned(uintmax_t n, uintmax_t a)
147 {
148 assert(a == (a & -a));
149 return (n & (a - 1)) == 0;
150 }
151
152 static inline uint32_t
round_up_u32(uint32_t v,uint32_t a)153 round_up_u32(uint32_t v, uint32_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint64_t
round_up_u64(uint64_t v,uint64_t a)159 round_up_u64(uint64_t v, uint64_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint32_t
radv_minify(uint32_t n,uint32_t levels)165 radv_minify(uint32_t n, uint32_t levels)
166 {
167 if (unlikely(n == 0))
168 return 0;
169 else
170 return MAX2(n >> levels, 1);
171 }
172 static inline float
radv_clamp_f(float f,float min,float max)173 radv_clamp_f(float f, float min, float max)
174 {
175 assert(min < max);
176
177 if (f > max)
178 return max;
179 else if (f < min)
180 return min;
181 else
182 return f;
183 }
184
185 static inline bool
radv_clear_mask(uint32_t * inout_mask,uint32_t clear_mask)186 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
187 {
188 if (*inout_mask & clear_mask) {
189 *inout_mask &= ~clear_mask;
190 return true;
191 } else {
192 return false;
193 }
194 }
195
196 #define for_each_bit(b, dword) \
197 for (uint32_t __dword = (dword); \
198 (b) = __builtin_ffs(__dword) - 1, __dword; \
199 __dword &= ~(1 << (b)))
200
201 #define typed_memcpy(dest, src, count) ({ \
202 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
203 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 })
205
206 #define zero(x) (memset(&(x), 0, sizeof(x)))
207
208 /* Whenever we generate an error, pass it through this function. Useful for
209 * debugging, where we can break on it. Only call at error site, not when
210 * propagating errors. Might be useful to plug in a stack trace here.
211 */
212
213 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
214
215 #ifdef DEBUG
216 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
217 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
218 #else
219 #define vk_error(error) error
220 #define vk_errorf(error, format, ...) error
221 #endif
222
223 void __radv_finishme(const char *file, int line, const char *format, ...)
224 radv_printflike(3, 4);
225 void radv_loge(const char *format, ...) radv_printflike(1, 2);
226 void radv_loge_v(const char *format, va_list va);
227
228 /**
229 * Print a FINISHME message, including its source location.
230 */
231 #define radv_finishme(format, ...) \
232 do { \
233 static bool reported = false; \
234 if (!reported) { \
235 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 reported = true; \
237 } \
238 } while (0)
239
240 /* A non-fatal assert. Useful for debugging. */
241 #ifdef DEBUG
242 #define radv_assert(x) ({ \
243 if (unlikely(!(x))) \
244 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
245 })
246 #else
247 #define radv_assert(x)
248 #endif
249
250 #define stub_return(v) \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return (v); \
254 } while (0)
255
256 #define stub() \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return; \
260 } while (0)
261
262 void *radv_resolve_entrypoint(uint32_t index);
263 void *radv_lookup_entrypoint(const char *name);
264
265 extern struct radv_dispatch_table dtable;
266
267 struct radv_extensions {
268 VkExtensionProperties *ext_array;
269 uint32_t num_ext;
270 };
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 const char * name;
281 uint8_t uuid[VK_UUID_SIZE];
282
283 struct wsi_device wsi_device;
284 struct radv_extensions extensions;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 };
298
299 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
300 void radv_finish_wsi(struct radv_physical_device *physical_device);
301
302 struct cache_entry;
303
304 struct radv_pipeline_cache {
305 struct radv_device * device;
306 pthread_mutex_t mutex;
307
308 uint32_t total_size;
309 uint32_t table_size;
310 uint32_t kernel_count;
311 struct cache_entry ** hash_table;
312 bool modified;
313
314 VkAllocationCallbacks alloc;
315 };
316
317 void
318 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
319 struct radv_device *device);
320 void
321 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
322 void
323 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
324 const void *data, size_t size);
325
326 struct radv_shader_variant *
327 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
328 struct radv_pipeline_cache *cache,
329 const unsigned char *sha1);
330
331 struct radv_shader_variant *
332 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
333 const unsigned char *sha1,
334 struct radv_shader_variant *variant,
335 const void *code, unsigned code_size);
336
337 void radv_shader_variant_destroy(struct radv_device *device,
338 struct radv_shader_variant *variant);
339
340 struct radv_meta_state {
341 VkAllocationCallbacks alloc;
342
343 struct radv_pipeline_cache cache;
344
345 /**
346 * Use array element `i` for images with `2^i` samples.
347 */
348 struct {
349 VkRenderPass render_pass[NUM_META_FS_KEYS];
350 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
351
352 VkRenderPass depthstencil_rp;
353 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
354 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
355 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
356 } clear[1 + MAX_SAMPLES_LOG2];
357
358 struct {
359 VkRenderPass render_pass[NUM_META_FS_KEYS];
360
361 /** Pipeline that blits from a 1D image. */
362 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
363
364 /** Pipeline that blits from a 2D image. */
365 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
366
367 /** Pipeline that blits from a 3D image. */
368 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
369
370 VkRenderPass depth_only_rp;
371 VkPipeline depth_only_1d_pipeline;
372 VkPipeline depth_only_2d_pipeline;
373 VkPipeline depth_only_3d_pipeline;
374
375 VkRenderPass stencil_only_rp;
376 VkPipeline stencil_only_1d_pipeline;
377 VkPipeline stencil_only_2d_pipeline;
378 VkPipeline stencil_only_3d_pipeline;
379 VkPipelineLayout pipeline_layout;
380 VkDescriptorSetLayout ds_layout;
381 } blit;
382
383 struct {
384 VkRenderPass render_passes[NUM_META_FS_KEYS];
385
386 VkPipelineLayout p_layouts[2];
387 VkDescriptorSetLayout ds_layouts[2];
388 VkPipeline pipelines[2][NUM_META_FS_KEYS];
389
390 VkRenderPass depth_only_rp;
391 VkPipeline depth_only_pipeline[2];
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_pipeline[2];
395 } blit2d;
396
397 struct {
398 VkPipelineLayout img_p_layout;
399 VkDescriptorSetLayout img_ds_layout;
400 VkPipeline pipeline;
401 } itob;
402 struct {
403 VkRenderPass render_pass;
404 VkPipelineLayout img_p_layout;
405 VkDescriptorSetLayout img_ds_layout;
406 VkPipeline pipeline;
407 } btoi;
408 struct {
409 VkPipelineLayout img_p_layout;
410 VkDescriptorSetLayout img_ds_layout;
411 VkPipeline pipeline;
412 } itoi;
413 struct {
414 VkPipelineLayout img_p_layout;
415 VkDescriptorSetLayout img_ds_layout;
416 VkPipeline pipeline;
417 } cleari;
418
419 struct {
420 VkPipeline pipeline;
421 VkRenderPass pass;
422 } resolve;
423
424 struct {
425 VkDescriptorSetLayout ds_layout;
426 VkPipelineLayout p_layout;
427 struct {
428 VkPipeline pipeline;
429 VkPipeline i_pipeline;
430 } rc[MAX_SAMPLES_LOG2];
431 } resolve_compute;
432
433 struct {
434 VkPipeline decompress_pipeline;
435 VkPipeline resummarize_pipeline;
436 VkRenderPass pass;
437 } depth_decomp;
438
439 struct {
440 VkPipeline cmask_eliminate_pipeline;
441 VkPipeline fmask_decompress_pipeline;
442 VkRenderPass pass;
443 } fast_clear_flush;
444
445 struct {
446 VkPipelineLayout fill_p_layout;
447 VkPipelineLayout copy_p_layout;
448 VkDescriptorSetLayout fill_ds_layout;
449 VkDescriptorSetLayout copy_ds_layout;
450 VkPipeline fill_pipeline;
451 VkPipeline copy_pipeline;
452 } buffer;
453 };
454
455 /* queue types */
456 #define RADV_QUEUE_GENERAL 0
457 #define RADV_QUEUE_COMPUTE 1
458 #define RADV_QUEUE_TRANSFER 2
459
460 #define RADV_MAX_QUEUE_FAMILIES 3
461
462 enum ring_type radv_queue_family_to_ring(int f);
463
464 struct radv_queue {
465 VK_LOADER_DATA _loader_data;
466 struct radv_device * device;
467 struct radeon_winsys_ctx *hw_ctx;
468 int queue_family_index;
469 int queue_idx;
470 };
471
472 struct radv_device {
473 VK_LOADER_DATA _loader_data;
474
475 VkAllocationCallbacks alloc;
476
477 struct radv_instance * instance;
478 struct radeon_winsys *ws;
479
480 struct radv_meta_state meta_state;
481
482 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
483 int queue_count[RADV_MAX_QUEUE_FAMILIES];
484 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
485
486 uint64_t debug_flags;
487
488 /* MSAA sample locations.
489 * The first index is the sample index.
490 * The second index is the coordinate: X, Y. */
491 float sample_locations_1x[1][2];
492 float sample_locations_2x[2][2];
493 float sample_locations_4x[4][2];
494 float sample_locations_8x[8][2];
495 float sample_locations_16x[16][2];
496
497 struct radeon_winsys_bo *trace_bo;
498 uint32_t *trace_id_ptr;
499
500 struct radv_physical_device *physical_device;
501 };
502
503 struct radv_device_memory {
504 struct radeon_winsys_bo *bo;
505 uint32_t type_index;
506 VkDeviceSize map_size;
507 void * map;
508 };
509
510
511 struct radv_descriptor_range {
512 uint64_t va;
513 uint32_t size;
514 };
515
516 struct radv_descriptor_set {
517 const struct radv_descriptor_set_layout *layout;
518 struct list_head descriptor_pool;
519 uint32_t size;
520
521 struct radv_buffer_view *buffer_views;
522 struct radeon_winsys_bo *bo;
523 uint64_t va;
524 uint32_t *mapped_ptr;
525 struct radv_descriptor_range *dynamic_descriptors;
526 struct radeon_winsys_bo *descriptors[0];
527 };
528
529 struct radv_descriptor_pool_free_node {
530 int next;
531 uint32_t offset;
532 uint32_t size;
533 };
534
535 struct radv_descriptor_pool {
536 struct list_head descriptor_sets;
537
538 struct radeon_winsys_bo *bo;
539 uint8_t *mapped_ptr;
540 uint64_t current_offset;
541 uint64_t size;
542
543 int free_list;
544 int full_list;
545 uint32_t max_sets;
546 uint32_t allocated_sets;
547 struct radv_descriptor_pool_free_node free_nodes[];
548 };
549
550 struct radv_buffer {
551 struct radv_device * device;
552 VkDeviceSize size;
553
554 VkBufferUsageFlags usage;
555
556 /* Set when bound */
557 struct radeon_winsys_bo * bo;
558 VkDeviceSize offset;
559 };
560
561
562 enum radv_cmd_dirty_bits {
563 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
564 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
565 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
566 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
567 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
568 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
569 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
570 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
571 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
572 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
573 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
574 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
575 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
576 };
577 typedef uint32_t radv_cmd_dirty_mask_t;
578
579 enum radv_cmd_flush_bits {
580 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
581 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
582 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
583 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
584 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
585 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
586 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
587 /* Framebuffer caches */
588 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
589 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
590 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
591 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
592 /* Engine synchronization. */
593 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
594 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
595 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
596 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
597
598 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
599 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
600 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
601 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
602 };
603
604 struct radv_vertex_binding {
605 struct radv_buffer * buffer;
606 VkDeviceSize offset;
607 };
608
609 struct radv_dynamic_state {
610 struct {
611 uint32_t count;
612 VkViewport viewports[MAX_VIEWPORTS];
613 } viewport;
614
615 struct {
616 uint32_t count;
617 VkRect2D scissors[MAX_SCISSORS];
618 } scissor;
619
620 float line_width;
621
622 struct {
623 float bias;
624 float clamp;
625 float slope;
626 } depth_bias;
627
628 float blend_constants[4];
629
630 struct {
631 float min;
632 float max;
633 } depth_bounds;
634
635 struct {
636 uint32_t front;
637 uint32_t back;
638 } stencil_compare_mask;
639
640 struct {
641 uint32_t front;
642 uint32_t back;
643 } stencil_write_mask;
644
645 struct {
646 uint32_t front;
647 uint32_t back;
648 } stencil_reference;
649 };
650
651 extern const struct radv_dynamic_state default_dynamic_state;
652
653 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
654 const struct radv_dynamic_state *src,
655 uint32_t copy_mask);
656 /**
657 * Attachment state when recording a renderpass instance.
658 *
659 * The clear value is valid only if there exists a pending clear.
660 */
661 struct radv_attachment_state {
662 VkImageAspectFlags pending_clear_aspects;
663 VkClearValue clear_value;
664 VkImageLayout current_layout;
665 };
666
667 struct radv_cmd_state {
668 uint32_t vb_dirty;
669 bool vertex_descriptors_dirty;
670 radv_cmd_dirty_mask_t dirty;
671
672 struct radv_pipeline * pipeline;
673 struct radv_pipeline * emitted_pipeline;
674 struct radv_pipeline * compute_pipeline;
675 struct radv_pipeline * emitted_compute_pipeline;
676 struct radv_framebuffer * framebuffer;
677 struct radv_render_pass * pass;
678 const struct radv_subpass * subpass;
679 struct radv_dynamic_state dynamic;
680 struct radv_vertex_binding vertex_bindings[MAX_VBS];
681 struct radv_descriptor_set * descriptors[MAX_SETS];
682 struct radv_attachment_state * attachments;
683 VkRect2D render_area;
684 struct radv_buffer * index_buffer;
685 uint32_t index_type;
686 uint32_t index_offset;
687 uint32_t last_primitive_reset_index;
688 enum radv_cmd_flush_bits flush_bits;
689 unsigned active_occlusion_queries;
690 float offset_scale;
691 uint32_t descriptors_dirty;
692 uint32_t trace_id;
693 };
694
695 struct radv_cmd_pool {
696 VkAllocationCallbacks alloc;
697 struct list_head cmd_buffers;
698 uint32_t queue_family_index;
699 };
700
701 struct radv_cmd_buffer_upload {
702 uint8_t *map;
703 unsigned offset;
704 uint64_t size;
705 struct radeon_winsys_bo *upload_bo;
706 struct list_head list;
707 };
708
709 struct radv_cmd_buffer {
710 VK_LOADER_DATA _loader_data;
711
712 struct radv_device * device;
713
714 struct radv_cmd_pool * pool;
715 struct list_head pool_link;
716
717 VkCommandBufferUsageFlags usage_flags;
718 VkCommandBufferLevel level;
719 struct radeon_winsys_cs *cs;
720 struct radv_cmd_state state;
721 uint32_t queue_family_index;
722
723 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
724 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
725 VkShaderStageFlags push_constant_stages;
726
727 struct radv_cmd_buffer_upload upload;
728
729 bool record_fail;
730 };
731
732 struct radv_image;
733
734 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
735
736 void si_init_compute(struct radv_physical_device *physical_device,
737 struct radv_cmd_buffer *cmd_buffer);
738 void si_init_config(struct radv_physical_device *physical_device,
739 struct radv_cmd_buffer *cmd_buffer);
740 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
741 int count, const VkViewport *viewports);
742 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
743 int count, const VkRect2D *scissors);
744 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
745 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
746 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
747 uint64_t src_va, uint64_t dest_va,
748 uint64_t size);
749 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
750 uint64_t size, unsigned value);
751 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
752 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
753 struct radv_descriptor_set *set,
754 unsigned idx);
755 bool
756 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
757 unsigned size,
758 unsigned alignment,
759 unsigned *out_offset,
760 void **ptr);
761 void
762 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
763 const struct radv_subpass *subpass,
764 bool transitions);
765 bool
766 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
767 unsigned size, unsigned alignmnet,
768 const void *data, unsigned *out_offset);
769 void
770 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
771 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
772 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
773 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
774 unsigned radv_cayman_get_maxdist(int log_samples);
775 void radv_device_init_msaa(struct radv_device *device);
776 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
777 struct radv_image *image,
778 VkClearDepthStencilValue ds_clear_value,
779 VkImageAspectFlags aspects);
780 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
781 struct radv_image *image,
782 int idx,
783 uint32_t color_values[2]);
784 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
785 struct radeon_winsys_bo *bo,
786 uint64_t offset, uint64_t size, uint32_t value);
787 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
788
789 /*
790 * Takes x,y,z as exact numbers of invocations, instead of blocks.
791 *
792 * Limitations: Can't call normal dispatch functions without binding or rebinding
793 * the compute pipeline.
794 */
795 void radv_unaligned_dispatch(
796 struct radv_cmd_buffer *cmd_buffer,
797 uint32_t x,
798 uint32_t y,
799 uint32_t z);
800
801 struct radv_event {
802 struct radeon_winsys_bo *bo;
803 uint64_t *map;
804 };
805
806 struct nir_shader;
807
808 struct radv_shader_module {
809 struct nir_shader * nir;
810 unsigned char sha1[20];
811 uint32_t size;
812 char data[0];
813 };
814
815 union ac_shader_variant_key;
816
817 void
818 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
819 const char *entrypoint,
820 const VkSpecializationInfo *spec_info,
821 const struct radv_pipeline_layout *layout,
822 const union ac_shader_variant_key *key);
823
824 static inline gl_shader_stage
vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)825 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
826 {
827 assert(__builtin_popcount(vk_stage) == 1);
828 return ffs(vk_stage) - 1;
829 }
830
831 static inline VkShaderStageFlagBits
mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)832 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
833 {
834 return (1 << mesa_stage);
835 }
836
837 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
838
839 #define radv_foreach_stage(stage, stage_bits) \
840 for (gl_shader_stage stage, \
841 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
842 stage = __builtin_ffs(__tmp) - 1, __tmp; \
843 __tmp &= ~(1 << (stage)))
844
845 struct radv_shader_variant {
846 uint32_t ref_count;
847
848 struct radeon_winsys_bo *bo;
849 struct ac_shader_config config;
850 struct ac_shader_variant_info info;
851 unsigned rsrc1;
852 unsigned rsrc2;
853 uint32_t code_size;
854 };
855
856 struct radv_depth_stencil_state {
857 uint32_t db_depth_control;
858 uint32_t db_stencil_control;
859 uint32_t db_render_control;
860 uint32_t db_render_override2;
861 };
862
863 struct radv_blend_state {
864 uint32_t cb_color_control;
865 uint32_t cb_target_mask;
866 uint32_t sx_mrt0_blend_opt[8];
867 uint32_t cb_blend_control[8];
868
869 uint32_t spi_shader_col_format;
870 uint32_t cb_shader_mask;
871 uint32_t db_alpha_to_mask;
872 };
873
874 unsigned radv_format_meta_fs_key(VkFormat format);
875
876 struct radv_raster_state {
877 uint32_t pa_cl_clip_cntl;
878 uint32_t pa_cl_vs_out_cntl;
879 uint32_t spi_interp_control;
880 uint32_t pa_su_point_size;
881 uint32_t pa_su_point_minmax;
882 uint32_t pa_su_line_cntl;
883 uint32_t pa_su_vtx_cntl;
884 uint32_t pa_su_sc_mode_cntl;
885 };
886
887 struct radv_multisample_state {
888 uint32_t db_eqaa;
889 uint32_t pa_sc_line_cntl;
890 uint32_t pa_sc_mode_cntl_0;
891 uint32_t pa_sc_mode_cntl_1;
892 uint32_t pa_sc_aa_config;
893 uint32_t pa_sc_aa_mask[2];
894 unsigned num_samples;
895 };
896
897 struct radv_pipeline {
898 struct radv_device * device;
899 uint32_t dynamic_state_mask;
900 struct radv_dynamic_state dynamic_state;
901
902 struct radv_pipeline_layout * layout;
903
904 bool needs_data_cache;
905
906 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
907 VkShaderStageFlags active_stages;
908
909 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
910 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
911 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
912 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
913 uint32_t num_vertex_attribs;
914 uint32_t binding_stride[MAX_VBS];
915
916 union {
917 struct {
918 struct radv_blend_state blend;
919 struct radv_depth_stencil_state ds;
920 struct radv_raster_state raster;
921 struct radv_multisample_state ms;
922 unsigned prim;
923 unsigned gs_out;
924 bool prim_restart_enable;
925 } graphics;
926 };
927 };
928
929 struct radv_graphics_pipeline_create_info {
930 bool use_rectlist;
931 bool db_depth_clear;
932 bool db_stencil_clear;
933 bool db_depth_disable_expclear;
934 bool db_stencil_disable_expclear;
935 bool db_flush_depth_inplace;
936 bool db_flush_stencil_inplace;
937 bool db_resummarize;
938 uint32_t custom_blend_mode;
939 };
940
941 VkResult
942 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
943 struct radv_pipeline_cache *cache,
944 const VkGraphicsPipelineCreateInfo *pCreateInfo,
945 const struct radv_graphics_pipeline_create_info *extra,
946 const VkAllocationCallbacks *alloc);
947
948 VkResult
949 radv_graphics_pipeline_create(VkDevice device,
950 VkPipelineCache cache,
951 const VkGraphicsPipelineCreateInfo *pCreateInfo,
952 const struct radv_graphics_pipeline_create_info *extra,
953 const VkAllocationCallbacks *alloc,
954 VkPipeline *pPipeline);
955
956 struct vk_format_description;
957 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
958 int first_non_void);
959 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
960 int first_non_void);
961 uint32_t radv_translate_colorformat(VkFormat format);
962 uint32_t radv_translate_color_numformat(VkFormat format,
963 const struct vk_format_description *desc,
964 int first_non_void);
965 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
966 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
967 uint32_t radv_translate_dbformat(VkFormat format);
968 uint32_t radv_translate_tex_dataformat(VkFormat format,
969 const struct vk_format_description *desc,
970 int first_non_void);
971 uint32_t radv_translate_tex_numformat(VkFormat format,
972 const struct vk_format_description *desc,
973 int first_non_void);
974 bool radv_format_pack_clear_color(VkFormat format,
975 uint32_t clear_vals[2],
976 VkClearColorValue *value);
977 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
978
979 struct radv_fmask_info {
980 uint64_t offset;
981 uint64_t size;
982 unsigned alignment;
983 unsigned pitch_in_pixels;
984 unsigned bank_height;
985 unsigned slice_tile_max;
986 unsigned tile_mode_index;
987 };
988
989 struct radv_cmask_info {
990 uint64_t offset;
991 uint64_t size;
992 unsigned alignment;
993 unsigned slice_tile_max;
994 unsigned base_address_reg;
995 };
996
997 struct r600_htile_info {
998 uint64_t offset;
999 uint64_t size;
1000 unsigned pitch;
1001 unsigned height;
1002 unsigned xalign;
1003 unsigned yalign;
1004 };
1005
1006 struct radv_image {
1007 VkImageType type;
1008 /* The original VkFormat provided by the client. This may not match any
1009 * of the actual surface formats.
1010 */
1011 VkFormat vk_format;
1012 VkImageAspectFlags aspects;
1013 VkExtent3D extent;
1014 uint32_t levels;
1015 uint32_t array_size;
1016 uint32_t samples; /**< VkImageCreateInfo::samples */
1017 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1018 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1019
1020 VkDeviceSize size;
1021 uint32_t alignment;
1022
1023 bool exclusive;
1024 unsigned queue_family_mask;
1025
1026 /* Set when bound */
1027 struct radeon_winsys_bo *bo;
1028 VkDeviceSize offset;
1029 uint32_t dcc_offset;
1030 struct radeon_surf surface;
1031
1032 struct radv_fmask_info fmask;
1033 struct radv_cmask_info cmask;
1034 uint32_t clear_value_offset;
1035
1036 /* Depth buffer compression and fast clear. */
1037 struct r600_htile_info htile;
1038 };
1039
1040 bool radv_layout_has_htile(const struct radv_image *image,
1041 VkImageLayout layout);
1042 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1043 VkImageLayout layout);
1044 bool radv_layout_can_expclear(const struct radv_image *image,
1045 VkImageLayout layout);
1046 bool radv_layout_can_fast_clear(const struct radv_image *image,
1047 VkImageLayout layout,
1048 unsigned queue_mask);
1049
1050
1051 unsigned radv_image_queue_family_mask(const struct radv_image *image, int family);
1052
1053 static inline uint32_t
radv_get_layerCount(const struct radv_image * image,const VkImageSubresourceRange * range)1054 radv_get_layerCount(const struct radv_image *image,
1055 const VkImageSubresourceRange *range)
1056 {
1057 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1058 image->array_size - range->baseArrayLayer : range->layerCount;
1059 }
1060
1061 static inline uint32_t
radv_get_levelCount(const struct radv_image * image,const VkImageSubresourceRange * range)1062 radv_get_levelCount(const struct radv_image *image,
1063 const VkImageSubresourceRange *range)
1064 {
1065 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1066 image->levels - range->baseMipLevel : range->levelCount;
1067 }
1068
1069 struct radeon_bo_metadata;
1070 void
1071 radv_init_metadata(struct radv_device *device,
1072 struct radv_image *image,
1073 struct radeon_bo_metadata *metadata);
1074
1075 struct radv_image_view {
1076 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1077 struct radeon_winsys_bo *bo;
1078
1079 VkImageViewType type;
1080 VkImageAspectFlags aspect_mask;
1081 VkFormat vk_format;
1082 uint32_t base_layer;
1083 uint32_t layer_count;
1084 uint32_t base_mip;
1085 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1086
1087 uint32_t descriptor[8];
1088 uint32_t fmask_descriptor[8];
1089 };
1090
1091 struct radv_image_create_info {
1092 const VkImageCreateInfo *vk_info;
1093 uint32_t stride;
1094 bool scanout;
1095 };
1096
1097 VkResult radv_image_create(VkDevice _device,
1098 const struct radv_image_create_info *info,
1099 const VkAllocationCallbacks* alloc,
1100 VkImage *pImage);
1101
1102 void radv_image_view_init(struct radv_image_view *view,
1103 struct radv_device *device,
1104 const VkImageViewCreateInfo* pCreateInfo,
1105 struct radv_cmd_buffer *cmd_buffer,
1106 VkImageUsageFlags usage_mask);
1107 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1108 struct radv_image *image, uint32_t micro_tile_mode);
1109 struct radv_buffer_view {
1110 struct radeon_winsys_bo *bo;
1111 VkFormat vk_format;
1112 uint64_t range; /**< VkBufferViewCreateInfo::range */
1113 uint32_t state[4];
1114 };
1115 void radv_buffer_view_init(struct radv_buffer_view *view,
1116 struct radv_device *device,
1117 const VkBufferViewCreateInfo* pCreateInfo,
1118 struct radv_cmd_buffer *cmd_buffer);
1119
1120 static inline struct VkExtent3D
radv_sanitize_image_extent(const VkImageType imageType,const struct VkExtent3D imageExtent)1121 radv_sanitize_image_extent(const VkImageType imageType,
1122 const struct VkExtent3D imageExtent)
1123 {
1124 switch (imageType) {
1125 case VK_IMAGE_TYPE_1D:
1126 return (VkExtent3D) { imageExtent.width, 1, 1 };
1127 case VK_IMAGE_TYPE_2D:
1128 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1129 case VK_IMAGE_TYPE_3D:
1130 return imageExtent;
1131 default:
1132 unreachable("invalid image type");
1133 }
1134 }
1135
1136 static inline struct VkOffset3D
radv_sanitize_image_offset(const VkImageType imageType,const struct VkOffset3D imageOffset)1137 radv_sanitize_image_offset(const VkImageType imageType,
1138 const struct VkOffset3D imageOffset)
1139 {
1140 switch (imageType) {
1141 case VK_IMAGE_TYPE_1D:
1142 return (VkOffset3D) { imageOffset.x, 0, 0 };
1143 case VK_IMAGE_TYPE_2D:
1144 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1145 case VK_IMAGE_TYPE_3D:
1146 return imageOffset;
1147 default:
1148 unreachable("invalid image type");
1149 }
1150 }
1151
1152 struct radv_sampler {
1153 uint32_t state[4];
1154 };
1155
1156 struct radv_color_buffer_info {
1157 uint32_t cb_color_base;
1158 uint32_t cb_color_pitch;
1159 uint32_t cb_color_slice;
1160 uint32_t cb_color_view;
1161 uint32_t cb_color_info;
1162 uint32_t cb_color_attrib;
1163 uint32_t cb_dcc_control;
1164 uint32_t cb_color_cmask;
1165 uint32_t cb_color_cmask_slice;
1166 uint32_t cb_color_fmask;
1167 uint32_t cb_color_fmask_slice;
1168 uint32_t cb_clear_value0;
1169 uint32_t cb_clear_value1;
1170 uint32_t cb_dcc_base;
1171 uint32_t micro_tile_mode;
1172 };
1173
1174 struct radv_ds_buffer_info {
1175 uint32_t db_depth_info;
1176 uint32_t db_z_info;
1177 uint32_t db_stencil_info;
1178 uint32_t db_z_read_base;
1179 uint32_t db_stencil_read_base;
1180 uint32_t db_z_write_base;
1181 uint32_t db_stencil_write_base;
1182 uint32_t db_depth_view;
1183 uint32_t db_depth_size;
1184 uint32_t db_depth_slice;
1185 uint32_t db_htile_surface;
1186 uint32_t db_htile_data_base;
1187 uint32_t pa_su_poly_offset_db_fmt_cntl;
1188 float offset_scale;
1189 };
1190
1191 struct radv_attachment_info {
1192 union {
1193 struct radv_color_buffer_info cb;
1194 struct radv_ds_buffer_info ds;
1195 };
1196 struct radv_image_view *attachment;
1197 };
1198
1199 struct radv_framebuffer {
1200 uint32_t width;
1201 uint32_t height;
1202 uint32_t layers;
1203
1204 uint32_t attachment_count;
1205 struct radv_attachment_info attachments[0];
1206 };
1207
1208 struct radv_subpass_barrier {
1209 VkPipelineStageFlags src_stage_mask;
1210 VkAccessFlags src_access_mask;
1211 VkAccessFlags dst_access_mask;
1212 };
1213
1214 struct radv_subpass {
1215 uint32_t input_count;
1216 VkAttachmentReference * input_attachments;
1217 uint32_t color_count;
1218 VkAttachmentReference * color_attachments;
1219 VkAttachmentReference * resolve_attachments;
1220 VkAttachmentReference depth_stencil_attachment;
1221
1222 /** Subpass has at least one resolve attachment */
1223 bool has_resolve;
1224
1225 struct radv_subpass_barrier start_barrier;
1226 };
1227
1228 struct radv_render_pass_attachment {
1229 VkFormat format;
1230 uint32_t samples;
1231 VkAttachmentLoadOp load_op;
1232 VkAttachmentLoadOp stencil_load_op;
1233 VkImageLayout initial_layout;
1234 VkImageLayout final_layout;
1235 };
1236
1237 struct radv_render_pass {
1238 uint32_t attachment_count;
1239 uint32_t subpass_count;
1240 VkAttachmentReference * subpass_attachments;
1241 struct radv_render_pass_attachment * attachments;
1242 struct radv_subpass_barrier end_barrier;
1243 struct radv_subpass subpasses[0];
1244 };
1245
1246 VkResult radv_device_init_meta(struct radv_device *device);
1247 void radv_device_finish_meta(struct radv_device *device);
1248
1249 struct radv_query_pool {
1250 struct radeon_winsys_bo *bo;
1251 uint32_t stride;
1252 uint32_t availability_offset;
1253 char *ptr;
1254 VkQueryType type;
1255 };
1256
1257 VkResult
1258 radv_temp_descriptor_set_create(struct radv_device *device,
1259 struct radv_cmd_buffer *cmd_buffer,
1260 VkDescriptorSetLayout _layout,
1261 VkDescriptorSet *_set);
1262
1263 void
1264 radv_temp_descriptor_set_destroy(struct radv_device *device,
1265 VkDescriptorSet _set);
1266 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1267 struct radv_image *image, uint32_t value);
1268 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1269 struct radv_image *image, uint32_t value);
1270
1271 struct radv_fence {
1272 struct radeon_winsys_fence *fence;
1273 bool submitted;
1274 bool signalled;
1275 };
1276
1277 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1278 \
1279 static inline struct __radv_type * \
1280 __radv_type ## _from_handle(__VkType _handle) \
1281 { \
1282 return (struct __radv_type *) _handle; \
1283 } \
1284 \
1285 static inline __VkType \
1286 __radv_type ## _to_handle(struct __radv_type *_obj) \
1287 { \
1288 return (__VkType) _obj; \
1289 }
1290
1291 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1292 \
1293 static inline struct __radv_type * \
1294 __radv_type ## _from_handle(__VkType _handle) \
1295 { \
1296 return (struct __radv_type *)(uintptr_t) _handle; \
1297 } \
1298 \
1299 static inline __VkType \
1300 __radv_type ## _to_handle(struct __radv_type *_obj) \
1301 { \
1302 return (__VkType)(uintptr_t) _obj; \
1303 }
1304
1305 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1306 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1307
1308 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1309 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1310 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1311 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1312 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1313
1314 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1315 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1316 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1317 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1318 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1319 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1320 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1321 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1322 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1323 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1324 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1325 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1326 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1327 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1328 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1329 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1330 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1331 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1332 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1333
1334 #endif /* RADV_PRIVATE_H */
1335