1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2012-2015 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "ilo_debug.h"
29 #include "ilo_image.h"
30 #include "ilo_vma.h"
31 #include "ilo_state_surface.h"
32
33 static bool
surface_set_gen6_null_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev)34 surface_set_gen6_null_SURFACE_STATE(struct ilo_state_surface *surf,
35 const struct ilo_dev *dev)
36 {
37 uint32_t dw0, dw3;
38
39 ILO_DEV_ASSERT(dev, 6, 6);
40
41 /*
42 * From the Sandy Bridge PRM, volume 4 part 1, page 71:
43 *
44 * "All of the remaining fields in surface state are ignored for null
45 * surfaces, with the following exceptions:
46 *
47 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
48 * depth buffer's corresponding state for all render target
49 * surfaces, including null.
50 * - Surface Format must be R8G8B8A8_UNORM."
51 *
52 * From the Sandy Bridge PRM, volume 4 part 1, page 82:
53 *
54 * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must
55 * be true"
56 *
57 * Note that we ignore the first exception for all surface types.
58 */
59 dw0 = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT |
60 GEN6_FORMAT_R8G8B8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT;
61 dw3 = GEN6_TILING_X << GEN6_SURFACE_DW3_TILING__SHIFT;
62
63 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
64 surf->surface[0] = dw0;
65 surf->surface[1] = 0;
66 surf->surface[2] = 0;
67 surf->surface[3] = dw3;
68 surf->surface[4] = 0;
69 surf->surface[5] = 0;
70
71 return true;
72 }
73
74 static bool
surface_set_gen7_null_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev)75 surface_set_gen7_null_SURFACE_STATE(struct ilo_state_surface *surf,
76 const struct ilo_dev *dev)
77 {
78 uint32_t dw0;
79
80 ILO_DEV_ASSERT(dev, 7, 8);
81
82 dw0 = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
83 GEN6_FORMAT_R8G8B8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT;
84 if (ilo_dev_gen(dev) >= ILO_GEN(8))
85 dw0 |= GEN6_TILING_X << GEN8_SURFACE_DW0_TILING__SHIFT;
86 else
87 dw0 |= GEN6_TILING_X << GEN7_SURFACE_DW0_TILING__SHIFT;
88
89 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
90 surf->surface[0] = dw0;
91 memset(&surf->surface[1], 0, sizeof(uint32_t) *
92 (((ilo_dev_gen(dev) >= ILO_GEN(8)) ? 13 : 8) - 1));
93
94 return true;
95 }
96
97 static uint32_t
surface_get_gen6_buffer_offset_alignment(const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info)98 surface_get_gen6_buffer_offset_alignment(const struct ilo_dev *dev,
99 const struct ilo_state_surface_buffer_info *info)
100 {
101 uint32_t alignment;
102
103 ILO_DEV_ASSERT(dev, 6, 8);
104
105 /*
106 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
107 *
108 * "The Base Address for linear render target surfaces and surfaces
109 * accessed with the typed surface read/write data port messages must
110 * be element-size aligned, for non-YUV surface formats, or a multiple
111 * of 2 element-sizes for YUV surface formats. Other linear surfaces
112 * have no alignment requirements (byte alignment is sufficient)."
113 *
114 * "Certain message types used to access surfaces have more stringent
115 * alignment requirements. Please refer to the specific message
116 * documentation for additional restrictions."
117 */
118 switch (info->access) {
119 case ILO_STATE_SURFACE_ACCESS_SAMPLER:
120 /* no alignment requirements */
121 alignment = 1;
122 break;
123 case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
124 case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
125 /* element-size aligned */
126 alignment = info->format_size;
127
128 assert(info->struct_size % alignment == 0);
129 break;
130 case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
131 /*
132 * Nothing is said about Untyped* messages, but I think they require the
133 * base address to be DWord aligned.
134 */
135 alignment = 4;
136
137 /*
138 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
139 *
140 * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the
141 * pitch must be a multiple of 4 bytes."
142 */
143 if (info->struct_size > 1)
144 assert(info->struct_size % alignment == 0);
145 break;
146 case ILO_STATE_SURFACE_ACCESS_DP_DATA:
147 /*
148 * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, and 237:
149 *
150 * "the surface base address must be OWord aligned"
151 *
152 * for OWord Block Read/Write, Unaligned OWord Block Read, and OWord
153 * Dual Block Read/Write.
154 *
155 * From the Ivy Bridge PRM, volume 4 part 1, page 246 and 249:
156 *
157 * "The surface base address must be DWord aligned"
158 *
159 * for DWord Scattered Read/Write and Byte Scattered Read/Write.
160 */
161 alignment = (info->format_size > 4) ? 16 : 4;
162
163 /*
164 * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, 237, and
165 * 246:
166 *
167 * "the surface pitch is ignored, the surface is treated as a
168 * 1-dimensional surface. An element size (pitch) of 16 bytes is
169 * used to determine the size of the buffer for out-of-bounds
170 * checking if using the surface state model."
171 *
172 * for OWord Block Read/Write, Unaligned OWord Block Read, OWord
173 * Dual Block Read/Write, and DWord Scattered Read/Write.
174 *
175 * From the Ivy Bridge PRM, volume 4 part 1, page 248:
176 *
177 * "The surface pitch is ignored, the surface is treated as a
178 * 1-dimensional surface. An element size (pitch) of 4 bytes is
179 * used to determine the size of the buffer for out-of-bounds
180 * checking if using the surface state model."
181 *
182 * for Byte Scattered Read/Write.
183 *
184 * It is programmable on Gen7.5+.
185 */
186 if (ilo_dev_gen(dev) < ILO_GEN(7.5)) {
187 const int fixed = (info->format_size > 1) ? 16 : 4;
188 assert(info->struct_size == fixed);
189 }
190 break;
191 case ILO_STATE_SURFACE_ACCESS_DP_SVB:
192 /*
193 * From the Sandy Bridge PRM, volume 4 part 1, page 259:
194 *
195 * "Both the surface base address and surface pitch must be DWord
196 * aligned."
197 */
198 alignment = 4;
199
200 assert(info->struct_size % alignment == 0);
201 break;
202 default:
203 assert(!"unknown access");
204 alignment = 1;
205 break;
206 }
207
208 return alignment;
209 }
210
211 static bool
surface_validate_gen6_buffer(const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info)212 surface_validate_gen6_buffer(const struct ilo_dev *dev,
213 const struct ilo_state_surface_buffer_info *info)
214 {
215 uint32_t alignment;
216
217 ILO_DEV_ASSERT(dev, 6, 8);
218
219 if (info->offset + info->size > info->vma->vm_size) {
220 ilo_warn("invalid buffer range\n");
221 return false;
222 }
223
224 /*
225 * From the Sandy Bridge PRM, volume 4 part 1, page 81:
226 *
227 * "For surfaces of type SURFTYPE_BUFFER: [0,2047] -> [1B, 2048B]
228 * For surfaces of type SURFTYPE_STRBUF: [0,2047] -> [1B, 2048B]"
229 */
230 if (!info->struct_size || info->struct_size > 2048) {
231 ilo_warn("invalid buffer struct size\n");
232 return false;
233 }
234
235 alignment = surface_get_gen6_buffer_offset_alignment(dev, info);
236 if (info->offset % alignment || info->vma->vm_alignment % alignment) {
237 ilo_warn("bad buffer offset\n");
238 return false;
239 }
240
241 /* no STRBUF on Gen6 */
242 if (info->format == GEN6_FORMAT_RAW && info->struct_size > 1)
243 assert(ilo_dev_gen(dev) >= ILO_GEN(7));
244
245 /* SVB writes are Gen6 only */
246 if (info->access == ILO_STATE_SURFACE_ACCESS_DP_SVB)
247 assert(ilo_dev_gen(dev) == ILO_GEN(6));
248
249 /*
250 * From the Ivy Bridge PRM, volume 4 part 1, page 83:
251 *
252 * "NOTE: "RAW" is supported only with buffers and structured buffers
253 * accessed via the untyped surface read/write and untyped atomic
254 * operation messages, which do not have a column in the table."
255 *
256 * From the Ivy Bridge PRM, volume 4 part 1, page 252:
257 *
258 * "For untyped messages, the Surface Format must be RAW and the
259 * Surface Type must be SURFTYPE_BUFFER or SURFTYPE_STRBUF."
260 */
261 assert((info->access == ILO_STATE_SURFACE_ACCESS_DP_UNTYPED) ==
262 (info->format == GEN6_FORMAT_RAW));
263
264 return true;
265 }
266
267 static bool
surface_get_gen6_buffer_struct_count(const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info,uint32_t * count)268 surface_get_gen6_buffer_struct_count(const struct ilo_dev *dev,
269 const struct ilo_state_surface_buffer_info *info,
270 uint32_t *count)
271 {
272 uint32_t max_struct, c;
273
274 ILO_DEV_ASSERT(dev, 6, 8);
275
276 c = info->size / info->struct_size;
277 if (info->format_size < info->size - info->struct_size * c)
278 c++;
279
280 /*
281 * From the Sandy Bridge PRM, volume 4 part 1, page 77:
282 *
283 * "For buffer surfaces, the number of entries in the buffer ranges
284 * from 1 to 2^27."
285 *
286 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
287 *
288 * "For typed buffer and structured buffer surfaces, the number of
289 * entries in the buffer ranges from 1 to 2^27. For raw buffer
290 * surfaces, the number of entries in the buffer is the number of
291 * bytes which can range from 1 to 2^30."
292 *
293 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
294 *
295 * For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
296 * 11 if the Surface Format is RAW (the size of the buffer must be a
297 * multiple of 4 bytes)."
298 */
299 max_struct = 1 << 27;
300 if (info->format == GEN6_FORMAT_RAW && info->struct_size == 1) {
301 if (ilo_dev_gen(dev) >= ILO_GEN(7))
302 max_struct = 1 << 30;
303
304 c &= ~3;
305 }
306
307 if (!c || c > max_struct) {
308 ilo_warn("too many or zero buffer structs\n");
309 return false;
310 }
311
312 *count = c - 1;
313
314 return true;
315 }
316
317 static bool
surface_set_gen6_buffer_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info)318 surface_set_gen6_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
319 const struct ilo_dev *dev,
320 const struct ilo_state_surface_buffer_info *info)
321 {
322 uint32_t dw0, dw1, dw2, dw3;
323 uint32_t struct_count;
324 int width, height, depth;
325
326 ILO_DEV_ASSERT(dev, 6, 6);
327
328 if (!surface_validate_gen6_buffer(dev, info) ||
329 !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
330 return false;
331
332 /* bits [6:0] */
333 width = (struct_count & 0x0000007f);
334 /* bits [19:7] */
335 height = (struct_count & 0x000fff80) >> 7;
336 /* bits [26:20] */
337 depth = (struct_count & 0x07f00000) >> 20;
338
339 dw0 = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
340 info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
341 dw1 = info->offset;
342 dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
343 width << GEN6_SURFACE_DW2_WIDTH__SHIFT;
344 dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
345 (info->struct_size - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT;
346
347 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
348 surf->surface[0] = dw0;
349 surf->surface[1] = dw1;
350 surf->surface[2] = dw2;
351 surf->surface[3] = dw3;
352 surf->surface[4] = 0;
353 surf->surface[5] = 0;
354
355 surf->type = GEN6_SURFTYPE_BUFFER;
356 surf->min_lod = 0;
357 surf->mip_count = 0;
358
359 return true;
360 }
361
362 static bool
surface_set_gen7_buffer_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info)363 surface_set_gen7_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
364 const struct ilo_dev *dev,
365 const struct ilo_state_surface_buffer_info *info)
366 {
367 uint32_t dw0, dw1, dw2, dw3, dw7;
368 enum gen_surface_type type;
369 uint32_t struct_count;
370 int width, height, depth;
371
372 ILO_DEV_ASSERT(dev, 7, 8);
373
374 if (!surface_validate_gen6_buffer(dev, info) ||
375 !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
376 return false;
377
378 type = (info->format == GEN6_FORMAT_RAW && info->struct_size > 1) ?
379 GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
380
381 /* bits [6:0] */
382 width = (struct_count & 0x0000007f);
383 /* bits [20:7] */
384 height = (struct_count & 0x001fff80) >> 7;
385 /* bits [30:21] */
386 depth = (struct_count & 0x7fe00000) >> 21;
387
388 dw0 = type << GEN7_SURFACE_DW0_TYPE__SHIFT |
389 info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
390 dw1 = (ilo_dev_gen(dev) >= ILO_GEN(8)) ? 0 : info->offset;
391 dw2 = GEN_SHIFT32(height, GEN7_SURFACE_DW2_HEIGHT) |
392 GEN_SHIFT32(width, GEN7_SURFACE_DW2_WIDTH);
393 dw3 = GEN_SHIFT32(depth, GEN7_SURFACE_DW3_DEPTH) |
394 GEN_SHIFT32(info->struct_size - 1, GEN7_SURFACE_DW3_PITCH);
395
396 dw7 = 0;
397 if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
398 dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
399 GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
400 GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
401 GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
402 }
403
404 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
405 surf->surface[0] = dw0;
406 surf->surface[1] = dw1;
407 surf->surface[2] = dw2;
408 surf->surface[3] = dw3;
409 surf->surface[4] = 0;
410 surf->surface[5] = 0;
411 surf->surface[6] = 0;
412 surf->surface[7] = dw7;
413 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
414 surf->surface[8] = info->offset;
415 surf->surface[9] = 0;
416 surf->surface[10] = 0;
417 surf->surface[11] = 0;
418 surf->surface[12] = 0;
419 }
420
421 surf->type = type;
422 surf->min_lod = 0;
423 surf->mip_count = 0;
424
425 return true;
426 }
427
428 static bool
surface_validate_gen6_image(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info)429 surface_validate_gen6_image(const struct ilo_dev *dev,
430 const struct ilo_state_surface_image_info *info)
431 {
432 ILO_DEV_ASSERT(dev, 6, 8);
433
434 switch (info->access) {
435 case ILO_STATE_SURFACE_ACCESS_SAMPLER:
436 case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
437 break;
438 case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
439 assert(ilo_dev_gen(dev) >= ILO_GEN(7));
440 break;
441 default:
442 assert(!"unsupported surface access");
443 break;
444 }
445
446 assert(info->img && info->vma);
447
448 if (info->img->tiling != GEN6_TILING_NONE)
449 assert(info->vma->vm_alignment % 4096 == 0);
450
451 if (info->aux_vma) {
452 assert(ilo_image_can_enable_aux(info->img, info->level_base));
453 /* always tiled */
454 assert(info->aux_vma->vm_alignment % 4096 == 0);
455 }
456
457 /*
458 * From the Sandy Bridge PRM, volume 4 part 1, page 78:
459 *
460 * "For surface types other than SURFTYPE_BUFFER, the Width specified
461 * by this field must be less than or equal to the surface pitch
462 * (specified in bytes via the Surface Pitch field)."
463 */
464 assert(info->img->bo_stride && info->img->bo_stride <= 512 * 1024 &&
465 info->img->width0 <= info->img->bo_stride);
466
467 if (info->type != info->img->type) {
468 assert(info->type == GEN6_SURFTYPE_2D &&
469 info->img->type == GEN6_SURFTYPE_CUBE);
470 }
471
472 /*
473 * From the Sandy Bridge PRM, volume 4 part 1, page 78:
474 *
475 * "For cube maps, Width must be set equal to the Height."
476 */
477 if (info->type == GEN6_SURFTYPE_CUBE)
478 assert(info->img->width0 == info->img->height0);
479
480 /*
481 * From the Sandy Bridge PRM, volume 4 part 1, page 72:
482 *
483 * "Tile Walk TILEWALK_YMAJOR is UNDEFINED for render target formats
484 * that have 128 bits-per-element (BPE)."
485 *
486 * "If Number of Multisamples is set to a value other than
487 * MULTISAMPLECOUNT_1, this field cannot be set to the following
488 * formats:
489 *
490 * - any format with greater than 64 bits per element
491 * - any compressed texture format (BC*)
492 * - any YCRCB* format"
493 *
494 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
495 *
496 * If Number of Multisamples is set to a value other than
497 * MULTISAMPLECOUNT_1, this field cannot be set to the following
498 * formats: any format with greater than 64 bits per element, if
499 * Number of Multisamples is MULTISAMPLECOUNT_8, any compressed
500 * texture format (BC*), and any YCRCB* format.
501 *
502 * TODO
503 */
504
505 if (ilo_dev_gen(dev) < ILO_GEN(8) && info->img->tiling == GEN8_TILING_W) {
506 ilo_warn("tiling W is not supported\n");
507 return false;
508 }
509
510 return true;
511 }
512
513 static void
surface_get_gen6_image_max_extent(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,uint16_t * max_w,uint16_t * max_h)514 surface_get_gen6_image_max_extent(const struct ilo_dev *dev,
515 const struct ilo_state_surface_image_info *info,
516 uint16_t *max_w, uint16_t *max_h)
517 {
518 const uint16_t max_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
519
520 ILO_DEV_ASSERT(dev, 6, 8);
521
522 switch (info->type) {
523 case GEN6_SURFTYPE_1D:
524 *max_w = max_size;
525 *max_h = 1;
526 break;
527 case GEN6_SURFTYPE_2D:
528 case GEN6_SURFTYPE_CUBE:
529 *max_w = max_size;
530 *max_h = max_size;
531 break;
532 case GEN6_SURFTYPE_3D:
533 *max_w = 2048;
534 *max_h = 2048;
535 break;
536 default:
537 assert(!"invalid surface type");
538 *max_w = 1;
539 *max_h = 1;
540 break;
541 }
542 }
543
544 static bool
surface_get_gen6_image_extent(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,uint16_t * width,uint16_t * height)545 surface_get_gen6_image_extent(const struct ilo_dev *dev,
546 const struct ilo_state_surface_image_info *info,
547 uint16_t *width, uint16_t *height)
548 {
549 uint16_t w, h, max_w, max_h;
550
551 ILO_DEV_ASSERT(dev, 6, 8);
552
553 w = info->img->width0;
554 h = info->img->height0;
555
556 surface_get_gen6_image_max_extent(dev, info, &max_w, &max_h);
557 assert(w && h && w <= max_w && h <= max_h);
558
559 *width = w - 1;
560 *height = h - 1;
561
562 return true;
563 }
564
565 static bool
surface_get_gen6_image_slices(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,uint16_t * depth,uint16_t * min_array_elem,uint16_t * rt_view_extent)566 surface_get_gen6_image_slices(const struct ilo_dev *dev,
567 const struct ilo_state_surface_image_info *info,
568 uint16_t *depth, uint16_t *min_array_elem,
569 uint16_t *rt_view_extent)
570 {
571 uint16_t max_slice, d;
572
573 ILO_DEV_ASSERT(dev, 6, 8);
574
575 /*
576 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
577 *
578 * "If this field (Surface Array) is enabled, the Surface Type must be
579 * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
580 * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
581 * SURFTYPE_CUBE, the Depth field must be set to zero."
582 *
583 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
584 *
585 * "This field (Depth) specifies the total number of levels for a
586 * volume texture or the number of array elements allowed to be
587 * accessed starting at the Minimum Array Element for arrayed
588 * surfaces. If the volume texture is MIP-mapped, this field
589 * specifies the depth of the base MIP level."
590 *
591 * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of this
592 * field is [0,340], indicating the number of cube array elements
593 * (equal to the number of underlying 2D array elements divided by 6).
594 * For other surfaces, this field must be zero."
595 *
596 * "Errata: For SURFTYPE_CUBE sampling engine surfaces, the range of
597 * this field is limited to [0,85].
598 *
599 * Errata: If Surface Array is enabled, and Depth is between 1024 and
600 * 2047, an incorrect array slice may be accessed if the requested
601 * array index in the message is greater than or equal to 4096."
602 *
603 * The errata are for Gen7-specific, and they limit the number of useable
604 * layers to (86 * 6), about 512.
605 */
606
607 switch (info->type) {
608 case GEN6_SURFTYPE_1D:
609 case GEN6_SURFTYPE_2D:
610 case GEN6_SURFTYPE_CUBE:
611 max_slice = (ilo_dev_gen(dev) >= ILO_GEN(7.5)) ? 2048 : 512;
612
613 assert(info->img->array_size <= max_slice);
614 max_slice = info->img->array_size;
615
616 d = info->slice_count;
617 if (info->type == GEN6_SURFTYPE_CUBE) {
618 if (info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
619 if (!d || d % 6) {
620 ilo_warn("invalid cube slice count\n");
621 return false;
622 }
623
624 if (ilo_dev_gen(dev) == ILO_GEN(7) && d > 86 * 6) {
625 ilo_warn("cube slice count exceeds Gen7 limit\n");
626 return false;
627 }
628 } else {
629 /*
630 * Minumum Array Element and Depth must be 0; Render Target View
631 * Extent is ignored.
632 */
633 if (info->slice_base || d != 6) {
634 ilo_warn("no cube RT array support in data port\n");
635 return false;
636 }
637 }
638
639 d /= 6;
640 }
641
642 if (!info->is_array && d > 1) {
643 ilo_warn("non-array surface with non-zero depth\n");
644 return false;
645 }
646 break;
647 case GEN6_SURFTYPE_3D:
648 max_slice = 2048;
649
650 assert(info->img->depth0 <= max_slice);
651 max_slice = u_minify(info->img->depth0, info->level_base);
652
653 d = info->img->depth0;
654
655 if (info->is_array) {
656 ilo_warn("3D surfaces cannot be arrays\n");
657 return false;
658 }
659 break;
660 default:
661 assert(!"invalid surface type");
662 return false;
663 break;
664 }
665
666 if (!info->slice_count ||
667 info->slice_base + info->slice_count > max_slice) {
668 ilo_warn("invalid slice range\n");
669 return false;
670 }
671
672 assert(d);
673 *depth = d - 1;
674
675 /*
676 * From the Sandy Bridge PRM, volume 4 part 1, page 84:
677 *
678 * "For Sampling Engine and Render Target 1D and 2D Surfaces:
679 * This field (Minimum Array Element) indicates the minimum array
680 * element that can be accessed as part of this surface. This field
681 * is added to the delivered array index before it is used to address
682 * the surface.
683 *
684 * For Render Target 3D Surfaces:
685 * This field indicates the minimum `R' coordinate on the LOD
686 * currently being rendered to. This field is added to the delivered
687 * array index before it is used to address the surface.
688 *
689 * For Sampling Engine Cube Surfaces on [DevSNB+] only:
690 * This field indicates the minimum array element in the underlying 2D
691 * surface array that can be accessed as part of this surface (the
692 * cube array index is multipled by 6 to compute this value, although
693 * this field is not restricted to only multiples of 6). This field is
694 * added to the delivered array index before it is used to address the
695 * surface.
696 *
697 * For Other Surfaces:
698 * This field must be set to zero."
699 *
700 * On Gen7+, typed sufaces are treated like sampling engine 1D and 2D
701 * surfaces.
702 */
703 *min_array_elem = info->slice_base;
704
705 /*
706 * From the Sandy Bridge PRM, volume 4 part 1, page 84:
707 *
708 * "For Render Target 3D Surfaces:
709 * This field (Render Target View Extent) indicates the extent of the
710 * accessible `R' coordinates minus 1 on the LOD currently being
711 * rendered to.
712 *
713 * For Render Target 1D and 2D Surfaces:
714 * This field must be set to the same value as the Depth field.
715 *
716 * For Other Surfaces:
717 * This field is ignored."
718 */
719 *rt_view_extent = info->slice_count - 1;
720
721 return true;
722 }
723
724 static bool
surface_get_gen6_image_levels(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,uint8_t * min_lod,uint8_t * mip_count)725 surface_get_gen6_image_levels(const struct ilo_dev *dev,
726 const struct ilo_state_surface_image_info *info,
727 uint8_t *min_lod, uint8_t *mip_count)
728 {
729 uint8_t max_level = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 15 : 14;
730
731 ILO_DEV_ASSERT(dev, 6, 8);
732
733 assert(info->img->level_count <= max_level);
734 max_level = info->img->level_count;
735
736 if (!info->level_count ||
737 info->level_base + info->level_count > max_level) {
738 ilo_warn("invalid level range\n");
739 return false;
740 }
741
742 /*
743 * From the Sandy Bridge PRM, volume 4 part 1, page 79:
744 *
745 * "For Sampling Engine Surfaces:
746 * This field (MIP Count / LOD) indicates the number of MIP levels
747 * allowed to be accessed starting at Surface Min LOD, which must be
748 * less than or equal to the number of MIP levels actually stored in
749 * memory for this surface.
750 *
751 * Force the mip map access to be between the mipmap specified by the
752 * integer bits of the Min LOD and the ceiling of the value specified
753 * here.
754 *
755 * For Render Target Surfaces:
756 * This field defines the MIP level that is currently being rendered
757 * into. This is the absolute MIP level on the surface and is not
758 * relative to the Surface Min LOD field, which is ignored for render
759 * target surfaces.
760 *
761 * For Other Surfaces:
762 * This field is reserved : MBZ"
763 *
764 * From the Sandy Bridge PRM, volume 4 part 1, page 83:
765 *
766 * "For Sampling Engine Surfaces:
767 *
768 * This field (Surface Min LOD) indicates the most detailed LOD that
769 * can be accessed as part of this surface. This field is added to
770 * the delivered LOD (sample_l, ld, or resinfo message types) before
771 * it is used to address the surface.
772 *
773 * For Other Surfaces:
774 * This field is ignored."
775 *
776 * On Gen7+, typed sufaces are treated like sampling engine surfaces.
777 */
778 if (info->access == ILO_STATE_SURFACE_ACCESS_DP_RENDER) {
779 assert(info->level_count == 1);
780
781 *min_lod = 0;
782 *mip_count = info->level_base;
783 } else {
784 *min_lod = info->level_base;
785 *mip_count = info->level_count - 1;
786 }
787
788 return true;
789 }
790
791 static bool
surface_get_gen6_image_sample_count(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,enum gen_sample_count * sample_count)792 surface_get_gen6_image_sample_count(const struct ilo_dev *dev,
793 const struct ilo_state_surface_image_info *info,
794 enum gen_sample_count *sample_count)
795 {
796 int min_gen;
797
798 ILO_DEV_ASSERT(dev, 6, 8);
799
800 switch (info->img->sample_count) {
801 case 1:
802 *sample_count = GEN6_NUMSAMPLES_1;
803 min_gen = ILO_GEN(6);
804 break;
805 case 2:
806 *sample_count = GEN8_NUMSAMPLES_2;
807 min_gen = ILO_GEN(8);
808 break;
809 case 4:
810 *sample_count = GEN6_NUMSAMPLES_4;
811 min_gen = ILO_GEN(6);
812 break;
813 case 8:
814 *sample_count = GEN7_NUMSAMPLES_8;
815 min_gen = ILO_GEN(7);
816 break;
817 default:
818 assert(!"invalid sample count");
819 *sample_count = GEN6_NUMSAMPLES_1;
820 break;
821 }
822
823 assert(ilo_dev_gen(dev) >= min_gen);
824
825 return true;
826 }
827
828 static bool
surface_get_gen6_image_alignments(const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info,uint32_t * alignments)829 surface_get_gen6_image_alignments(const struct ilo_dev *dev,
830 const struct ilo_state_surface_image_info *info,
831 uint32_t *alignments)
832 {
833 uint32_t a = 0;
834 bool err = false;
835
836 ILO_DEV_ASSERT(dev, 6, 8);
837
838 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
839 switch (info->img->align_i) {
840 case 4:
841 a |= GEN8_SURFACE_DW0_HALIGN_4;
842 break;
843 case 8:
844 a |= GEN8_SURFACE_DW0_HALIGN_8;
845 break;
846 case 16:
847 a |= GEN8_SURFACE_DW0_HALIGN_16;
848 break;
849 default:
850 err = true;
851 break;
852 }
853
854 switch (info->img->align_j) {
855 case 4:
856 a |= GEN7_SURFACE_DW0_VALIGN_4;
857 break;
858 case 8:
859 a |= GEN8_SURFACE_DW0_VALIGN_8;
860 break;
861 case 16:
862 a |= GEN8_SURFACE_DW0_VALIGN_16;
863 break;
864 default:
865 err = true;
866 break;
867 }
868 } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
869 switch (info->img->align_i) {
870 case 4:
871 a |= GEN7_SURFACE_DW0_HALIGN_4;
872 break;
873 case 8:
874 a |= GEN7_SURFACE_DW0_HALIGN_8;
875 break;
876 default:
877 err = true;
878 break;
879 }
880
881 switch (info->img->align_j) {
882 case 2:
883 a |= GEN7_SURFACE_DW0_VALIGN_2;
884 break;
885 case 4:
886 a |= GEN7_SURFACE_DW0_VALIGN_4;
887 break;
888 default:
889 err = true;
890 break;
891 }
892 } else {
893 if (info->img->align_i != 4)
894 err = true;
895
896 switch (info->img->align_j) {
897 case 2:
898 a |= GEN6_SURFACE_DW5_VALIGN_2;
899 break;
900 case 4:
901 a |= GEN6_SURFACE_DW5_VALIGN_4;
902 break;
903 default:
904 err = true;
905 break;
906 }
907 }
908
909 if (err)
910 assert(!"invalid HALIGN or VALIGN");
911
912 *alignments = a;
913
914 return true;
915 }
916
917 static bool
surface_set_gen6_image_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info)918 surface_set_gen6_image_SURFACE_STATE(struct ilo_state_surface *surf,
919 const struct ilo_dev *dev,
920 const struct ilo_state_surface_image_info *info)
921 {
922 uint16_t width, height, depth, array_base, view_extent;
923 uint8_t min_lod, mip_count;
924 enum gen_sample_count sample_count;
925 uint32_t alignments;
926 uint32_t dw0, dw2, dw3, dw4, dw5;
927
928 ILO_DEV_ASSERT(dev, 6, 6);
929
930 if (!surface_validate_gen6_image(dev, info) ||
931 !surface_get_gen6_image_extent(dev, info, &width, &height) ||
932 !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
933 &view_extent) ||
934 !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
935 !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
936 !surface_get_gen6_image_alignments(dev, info, &alignments))
937 return false;
938
939 /* no ARYSPC_LOD0 */
940 assert(info->img->walk != ILO_IMAGE_WALK_LOD);
941 /* no UMS/CMS */
942 if (info->img->sample_count > 1)
943 assert(info->img->interleaved_samples);
944
945 dw0 = info->type << GEN6_SURFACE_DW0_TYPE__SHIFT |
946 info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT |
947 GEN6_SURFACE_DW0_MIPLAYOUT_BELOW;
948
949 /*
950 * From the Sandy Bridge PRM, volume 4 part 1, page 74:
951 *
952 * "CUBE_AVERAGE may only be selected if all of the Cube Face Enable
953 * fields are equal to one."
954 *
955 * From the Sandy Bridge PRM, volume 4 part 1, page 75-76:
956 *
957 * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine:
958 * Bits 5:0 of this field (Cube Face Enables) enable the individual
959 * faces of a cube map. Enabling a face indicates that the face is
960 * present in the cube map, while disabling it indicates that that
961 * face is represented by the texture map's border color. Refer to
962 * Memory Data Formats for the correlation between faces and the cube
963 * map memory layout. Note that storage for disabled faces must be
964 * provided.
965 *
966 * For other surfaces:
967 * This field is reserved : MBZ"
968 *
969 * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
970 * field must be programmed to 111111b (all faces enabled)."
971 */
972 if (info->type == GEN6_SURFTYPE_CUBE &&
973 info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
974 dw0 |= GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE |
975 GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
976 }
977
978 dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
979 width << GEN6_SURFACE_DW2_WIDTH__SHIFT |
980 mip_count << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
981
982 dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
983 (info->img->bo_stride - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
984 info->img->tiling << GEN6_SURFACE_DW3_TILING__SHIFT;
985
986 dw4 = min_lod << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
987 array_base << GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
988 view_extent << GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
989 sample_count << GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
990
991 dw5 = alignments;
992
993 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
994 surf->surface[0] = dw0;
995 surf->surface[1] = 0;
996 surf->surface[2] = dw2;
997 surf->surface[3] = dw3;
998 surf->surface[4] = dw4;
999 surf->surface[5] = dw5;
1000
1001 surf->type = info->type;
1002 surf->min_lod = min_lod;
1003 surf->mip_count = mip_count;
1004
1005 return true;
1006 }
1007
1008 static bool
surface_set_gen7_image_SURFACE_STATE(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info)1009 surface_set_gen7_image_SURFACE_STATE(struct ilo_state_surface *surf,
1010 const struct ilo_dev *dev,
1011 const struct ilo_state_surface_image_info *info)
1012 {
1013 uint16_t width, height, depth, array_base, view_extent;
1014 uint8_t min_lod, mip_count;
1015 uint32_t alignments;
1016 enum gen_sample_count sample_count;
1017 uint32_t dw0, dw1, dw2, dw3, dw4, dw5, dw7;
1018
1019 ILO_DEV_ASSERT(dev, 7, 8);
1020
1021 if (!surface_validate_gen6_image(dev, info) ||
1022 !surface_get_gen6_image_extent(dev, info, &width, &height) ||
1023 !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
1024 &view_extent) ||
1025 !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
1026 !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
1027 !surface_get_gen6_image_alignments(dev, info, &alignments))
1028 return false;
1029
1030 dw0 = info->type << GEN7_SURFACE_DW0_TYPE__SHIFT |
1031 info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
1032 alignments;
1033
1034 if (info->is_array)
1035 dw0 |= GEN7_SURFACE_DW0_IS_ARRAY;
1036
1037 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1038 dw0 |= info->img->tiling << GEN8_SURFACE_DW0_TILING__SHIFT;
1039 } else {
1040 dw0 |= info->img->tiling << GEN7_SURFACE_DW0_TILING__SHIFT;
1041
1042 if (info->img->walk == ILO_IMAGE_WALK_LOD)
1043 dw0 |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
1044 else
1045 dw0 |= GEN7_SURFACE_DW0_ARYSPC_FULL;
1046 }
1047
1048 /*
1049 * From the Ivy Bridge PRM, volume 4 part 1, page 67:
1050 *
1051 * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine: Bits
1052 * 5:0 of this field (Cube Face Enables) enable the individual faces
1053 * of a cube map. Enabling a face indicates that the face is present
1054 * in the cube map, while disabling it indicates that that face is
1055 * represented by the texture map's border color. Refer to Memory Data
1056 * Formats for the correlation between faces and the cube map memory
1057 * layout. Note that storage for disabled faces must be provided. For
1058 * other surfaces this field is reserved and MBZ."
1059 *
1060 * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
1061 * field must be programmed to 111111b (all faces enabled). This field
1062 * is ignored unless the Surface Type is SURFTYPE_CUBE."
1063 */
1064 if (info->type == GEN6_SURFTYPE_CUBE &&
1065 info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER)
1066 dw0 |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
1067
1068 dw1 = 0;
1069 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1070 assert(info->img->walk_layer_height % 4 == 0);
1071 dw1 |= info->img->walk_layer_height / 4 <<
1072 GEN8_SURFACE_DW1_QPITCH__SHIFT;
1073 }
1074
1075 dw2 = height << GEN7_SURFACE_DW2_HEIGHT__SHIFT |
1076 width << GEN7_SURFACE_DW2_WIDTH__SHIFT;
1077
1078 dw3 = depth << GEN7_SURFACE_DW3_DEPTH__SHIFT |
1079 (info->img->bo_stride - 1) << GEN7_SURFACE_DW3_PITCH__SHIFT;
1080
1081 if (ilo_dev_gen(dev) == ILO_GEN(7.5))
1082 dw3 |= 0 << GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT;
1083
1084 dw4 = array_base << GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
1085 view_extent << GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
1086 sample_count << GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
1087
1088 /*
1089 * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
1090 * means the samples are interleaved. The layouts are the same when the
1091 * number of samples is 1.
1092 */
1093 if (info->img->interleaved_samples && info->img->sample_count > 1) {
1094 assert(info->access != ILO_STATE_SURFACE_ACCESS_DP_RENDER);
1095 dw4 |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL;
1096 } else {
1097 dw4 |= GEN7_SURFACE_DW4_MSFMT_MSS;
1098 }
1099
1100 dw5 = min_lod << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
1101 mip_count << GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT;
1102
1103 dw7 = 0;
1104 if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
1105 dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
1106 GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
1107 GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
1108 GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
1109 }
1110
1111 STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
1112 surf->surface[0] = dw0;
1113 surf->surface[1] = dw1;
1114 surf->surface[2] = dw2;
1115 surf->surface[3] = dw3;
1116 surf->surface[4] = dw4;
1117 surf->surface[5] = dw5;
1118 surf->surface[6] = 0;
1119 surf->surface[7] = dw7;
1120 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1121 surf->surface[8] = 0;
1122 surf->surface[9] = 0;
1123 surf->surface[10] = 0;
1124 surf->surface[11] = 0;
1125 surf->surface[12] = 0;
1126 }
1127
1128 surf->type = info->type;
1129 surf->min_lod = min_lod;
1130 surf->mip_count = mip_count;
1131
1132 return true;
1133 }
1134
1135 uint32_t
ilo_state_surface_buffer_size(const struct ilo_dev * dev,enum ilo_state_surface_access access,uint32_t size,uint32_t * alignment)1136 ilo_state_surface_buffer_size(const struct ilo_dev *dev,
1137 enum ilo_state_surface_access access,
1138 uint32_t size, uint32_t *alignment)
1139 {
1140 switch (access) {
1141 case ILO_STATE_SURFACE_ACCESS_SAMPLER:
1142 /*
1143 * From the Sandy Bridge PRM, volume 1 part 1, page 118:
1144 *
1145 * "For buffers, which have no inherent "height," padding
1146 * requirements are different. A buffer must be padded to the next
1147 * multiple of 256 array elements, with an additional 16 bytes
1148 * added beyond that to account for the L1 cache line."
1149 *
1150 * Assuming tightly packed GEN6_FORMAT_R32G32B32A32_FLOAT, the size
1151 * needs to be padded to 4096 (= 16 * 256).
1152 */
1153 *alignment = 1;
1154 size = align(size, 4096) + 16;
1155 break;
1156 case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
1157 case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
1158 /* element-size aligned for worst cases */
1159 *alignment = 16;
1160 break;
1161 case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
1162 /* DWord aligned? */
1163 *alignment = 4;
1164 break;
1165 case ILO_STATE_SURFACE_ACCESS_DP_DATA:
1166 /* OWord aligned */
1167 *alignment = 16;
1168 size = align(size, 16);
1169 break;
1170 case ILO_STATE_SURFACE_ACCESS_DP_SVB:
1171 /* always DWord aligned */
1172 *alignment = 4;
1173 break;
1174 default:
1175 assert(!"unknown access");
1176 *alignment = 1;
1177 break;
1178 }
1179
1180 return size;
1181 }
1182
1183 bool
ilo_state_surface_init_for_null(struct ilo_state_surface * surf,const struct ilo_dev * dev)1184 ilo_state_surface_init_for_null(struct ilo_state_surface *surf,
1185 const struct ilo_dev *dev)
1186 {
1187 bool ret = true;
1188
1189 assert(ilo_is_zeroed(surf, sizeof(*surf)));
1190
1191 if (ilo_dev_gen(dev) >= ILO_GEN(7))
1192 ret &= surface_set_gen7_null_SURFACE_STATE(surf, dev);
1193 else
1194 ret &= surface_set_gen6_null_SURFACE_STATE(surf, dev);
1195
1196 surf->vma = NULL;
1197 surf->type = GEN6_SURFTYPE_NULL;
1198 surf->readonly = true;
1199
1200 assert(ret);
1201
1202 return ret;
1203 }
1204
1205 bool
ilo_state_surface_init_for_buffer(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_buffer_info * info)1206 ilo_state_surface_init_for_buffer(struct ilo_state_surface *surf,
1207 const struct ilo_dev *dev,
1208 const struct ilo_state_surface_buffer_info *info)
1209 {
1210 bool ret = true;
1211
1212 assert(ilo_is_zeroed(surf, sizeof(*surf)));
1213
1214 if (ilo_dev_gen(dev) >= ILO_GEN(7))
1215 ret &= surface_set_gen7_buffer_SURFACE_STATE(surf, dev, info);
1216 else
1217 ret &= surface_set_gen6_buffer_SURFACE_STATE(surf, dev, info);
1218
1219 surf->vma = info->vma;
1220 surf->readonly = info->readonly;
1221
1222 assert(ret);
1223
1224 return ret;
1225 }
1226
1227 bool
ilo_state_surface_init_for_image(struct ilo_state_surface * surf,const struct ilo_dev * dev,const struct ilo_state_surface_image_info * info)1228 ilo_state_surface_init_for_image(struct ilo_state_surface *surf,
1229 const struct ilo_dev *dev,
1230 const struct ilo_state_surface_image_info *info)
1231 {
1232 bool ret = true;
1233
1234 assert(ilo_is_zeroed(surf, sizeof(*surf)));
1235
1236 if (ilo_dev_gen(dev) >= ILO_GEN(7))
1237 ret &= surface_set_gen7_image_SURFACE_STATE(surf, dev, info);
1238 else
1239 ret &= surface_set_gen6_image_SURFACE_STATE(surf, dev, info);
1240
1241 surf->vma = info->vma;
1242 surf->aux_vma = info->aux_vma;
1243
1244 surf->is_integer = info->is_integer;
1245 surf->readonly = info->readonly;
1246 surf->scanout = info->img->scanout;
1247
1248 assert(ret);
1249
1250 return ret;
1251 }
1252
1253 bool
ilo_state_surface_set_scs(struct ilo_state_surface * surf,const struct ilo_dev * dev,enum gen_surface_scs rgba[4])1254 ilo_state_surface_set_scs(struct ilo_state_surface *surf,
1255 const struct ilo_dev *dev,
1256 enum gen_surface_scs rgba[4])
1257 {
1258 const uint32_t scs = GEN_SHIFT32(rgba[0], GEN75_SURFACE_DW7_SCS_R) |
1259 GEN_SHIFT32(rgba[1], GEN75_SURFACE_DW7_SCS_G) |
1260 GEN_SHIFT32(rgba[2], GEN75_SURFACE_DW7_SCS_B) |
1261 GEN_SHIFT32(rgba[3], GEN75_SURFACE_DW7_SCS_A);
1262
1263 ILO_DEV_ASSERT(dev, 6, 8);
1264
1265 assert(ilo_dev_gen(dev) >= ILO_GEN(7.5));
1266
1267 surf->surface[7] = (surf->surface[7] & ~GEN75_SURFACE_DW7_SCS__MASK) | scs;
1268
1269 return true;
1270 }
1271