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Searched defs:instr (Results 1 – 25 of 36) sorted by relevance

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/art/compiler/optimizing/
Dscheduler_arm64.cc24 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation()
80 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv()
133 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul()
194 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion()
203 void SchedulingLatencyVisitorARM64::HandleSimpleArithmeticSIMD(HVecOperation *instr) { in HandleSimpleArithmeticSIMD()
216 void SchedulingLatencyVisitorARM64::VisitVecSetScalars(HVecSetScalars* instr) { in VisitVecSetScalars()
220 void SchedulingLatencyVisitorARM64::VisitVecSumReduce(HVecSumReduce* instr) { in VisitVecSumReduce()
228 void SchedulingLatencyVisitorARM64::VisitVecNeg(HVecNeg* instr) { in VisitVecNeg()
232 void SchedulingLatencyVisitorARM64::VisitVecAbs(HVecAbs* instr) { in VisitVecAbs()
236 void SchedulingLatencyVisitorARM64::VisitVecNot(HVecNot* instr) { in VisitVecNot()
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Dcommon_arm.h96 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister()
102 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister()
108 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister()
117 inline vixl::aarch32::SRegister InputSRegisterAt(HInstruction* instr, int input_index) { in InputSRegisterAt()
123 inline vixl::aarch32::DRegister InputDRegisterAt(HInstruction* instr, int input_index) { in InputDRegisterAt()
129 inline vixl::aarch32::VRegister InputVRegisterAt(HInstruction* instr, int input_index) { in InputVRegisterAt()
139 inline vixl::aarch32::VRegister InputVRegister(HInstruction* instr) { in InputVRegister()
144 inline vixl::aarch32::Register OutputRegister(HInstruction* instr) { in OutputRegister()
148 inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
153 inline vixl::aarch32::Register InputRegister(HInstruction* instr) { in InputRegister()
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Dscheduler_arm.cc29 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies()
48 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd()
52 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub()
56 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul()
72 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies()
88 void SchedulingLatencyVisitorARM::VisitAnd(HAnd* instr) { in VisitAnd()
92 void SchedulingLatencyVisitorARM::VisitOr(HOr* instr) { in VisitOr()
96 void SchedulingLatencyVisitorARM::VisitXor(HXor* instr) { in VisitXor()
100 void SchedulingLatencyVisitorARM::VisitRor(HRor* instr) { in VisitRor()
129 void SchedulingLatencyVisitorARM::HandleShiftLatencies(HBinaryOperation* instr) { in HandleShiftLatencies()
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Dreference_type_propagation.cc135 HInstruction* instr = iti.Current(); in ValidateTypes() local
350 HInstruction* instr = it.Current(); in VisitBasicBlock() local
512 void ReferenceTypePropagation::RTPVisitor::SetClassAsTypeInfo(HInstruction* instr, in SetClassAsTypeInfo()
550 void ReferenceTypePropagation::RTPVisitor::VisitDeoptimize(HDeoptimize* instr) { in VisitDeoptimize()
554 void ReferenceTypePropagation::RTPVisitor::UpdateReferenceTypeInfo(HInstruction* instr, in UpdateReferenceTypeInfo()
567 void ReferenceTypePropagation::RTPVisitor::VisitNewInstance(HNewInstance* instr) { in VisitNewInstance()
572 void ReferenceTypePropagation::RTPVisitor::VisitNewArray(HNewArray* instr) { in VisitNewArray()
577 void ReferenceTypePropagation::RTPVisitor::VisitParameterValue(HParameterValue* instr) { in VisitParameterValue()
587 void ReferenceTypePropagation::RTPVisitor::UpdateFieldAccessTypeInfo(HInstruction* instr, in UpdateFieldAccessTypeInfo()
604 void ReferenceTypePropagation::RTPVisitor::VisitInstanceFieldGet(HInstanceFieldGet* instr) { in VisitInstanceFieldGet()
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
115 inline vixl::aarch64::FPRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister()
119 inline vixl::aarch64::FPRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt()
130 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) { in OutputCPURegister()
136 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { in InputCPURegisterAt()
142 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr, in InputCPURegisterOrZeroRegAt()
155 HConstant* instr = location.GetConstant(); in Int64ConstantFrom() local
174 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
237 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { in Arm64CanEncodeConstantAsImmediate()
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Dinstruction_simplifier_shared.h41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand()
Dscheduler.h157 SchedulingNode(HInstruction* instr, ArenaAllocator* arena, bool is_scheduling_barrier) in SchedulingNode()
270 SchedulingNode* GetNode(const HInstruction* instr) const { in GetNode()
Dgraph_visualizer.h66 void AddInstructionInterval(HInstruction* instr, size_t start, size_t end) { in AddInstructionInterval()
Dgraph_test.cc30 HInstruction* instr = graph->GetIntConstant(4); in createIfBlock() local
Dcode_generator_vector_arm_vixl.cc624 void LocationsBuilderARMVIXL::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
628 void InstructionCodeGeneratorARMVIXL::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_vector_mips64.cc825 void LocationsBuilderMIPS64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
829 void InstructionCodeGeneratorMIPS64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_vector_x86_64.cc815 void LocationsBuilderX86_64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
819 void InstructionCodeGeneratorX86_64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_vector_mips.cc821 void LocationsBuilderMIPS::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
825 void InstructionCodeGeneratorMIPS::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_vector_x86.cc822 void LocationsBuilderX86::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
826 void InstructionCodeGeneratorX86::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_vector_arm64.cc806 void LocationsBuilderARM64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
831 void InstructionCodeGeneratorARM64::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instr) { in VisitVecMultiplyAccumulate()
Dcode_generator_arm64.cc464 explicit NullCheckSlowPathARM64(HNullCheck* instr) : SlowPathCodeARM64(instr) {} in NullCheckSlowPathARM64()
2429 void InstructionCodeGeneratorARM64::HandleBinaryOp(HBinaryOperation* instr) { in HandleBinaryOp()
2482 void LocationsBuilderARM64::HandleShift(HBinaryOperation* instr) { in HandleShift()
2500 void InstructionCodeGeneratorARM64::HandleShift(HBinaryOperation* instr) { in HandleShift()
2554 void LocationsBuilderARM64::VisitBitwiseNegatedRight(HBitwiseNegatedRight* instr) { in VisitBitwiseNegatedRight()
2563 void InstructionCodeGeneratorARM64::VisitBitwiseNegatedRight(HBitwiseNegatedRight* instr) { in VisitBitwiseNegatedRight()
2703 void LocationsBuilderARM64::VisitMultiplyAccumulate(HMultiplyAccumulate* instr) { in VisitMultiplyAccumulate()
2720 void InstructionCodeGeneratorARM64::VisitMultiplyAccumulate(HMultiplyAccumulate* instr) { in VisitMultiplyAccumulate()
Dcode_generator.cc1163 void CodeGenerator::MaybeRecordImplicitNullCheck(HInstruction* instr) { in MaybeRecordImplicitNullCheck()
/art/disassembler/
Ddisassembler_arm64.cc44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput()
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { in VisitLoadLiteral()
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { in VisitLoadStoreUnsignedOffset()
112 const Instruction* instr = reinterpret_cast<const Instruction*>(begin); in Dump() local
Ddisassembler_x86.cc164 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress()
247 size_t DisassemblerX86::DumpNops(std::ostream& os, const uint8_t* instr) { in DumpNops()
273 size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) { in DumpInstruction()
/art/runtime/
Dinstrumentation_test.cc187 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
214 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
343 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener()
370 static void ReportEvent(const instrumentation::Instrumentation* instr, in ReportEvent()
453 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TEST_F() local
582 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
613 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
631 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
679 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
698 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
Dcommon_throws.cc442 static bool IsValidImplicitCheck(uintptr_t addr, ArtMethod* method, const Instruction& instr) in IsValidImplicitCheck()
550 const Instruction* instr = Instruction::At(&code->insns_[throw_dex_pc]); in ThrowNullPointerExceptionFromDexPC() local
/art/runtime/interpreter/
Dinterpreter.cc470 static bool IsStringInit(const Instruction* instr, ArtMethod* caller) in IsStringInit()
493 static int16_t GetReceiverRegisterForStringInit(const Instruction* instr) { in GetReceiverRegisterForStringInit()
533 const Instruction* instr = Instruction::At(&code_item->insns_[dex_pc]); in EnterInterpreterFromDeoptimize() local
Dinterpreter_switch_impl.cc29 #define HANDLE_PENDING_EXCEPTION_WITH_INSTRUMENTATION(instr) \ argument
/art/runtime/arch/arm/
Dfault_handler_arm.cc42 uint16_t instr = pc[0] | pc[1] << 8; in GetInstructionSize() local
/art/runtime/openjdkjvmti/
Devents.cc596 art::instrumentation::Instrumentation* instr = art::Runtime::Current()->GetInstrumentation(); in SetupTraceListener() local

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