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1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //
23 //===----------------------------------------------------------------------===//
24 #include "Hexagon.h"
25 #include "HexagonInstrInfo.h"
26 #include "HexagonMachineFunctionInfo.h"
27 #include "HexagonRegisterInfo.h"
28 #include "HexagonSubtarget.h"
29 #include "HexagonTargetMachine.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/LiveVariables.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/PassSupport.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "hexagon-nvj"
48 
49 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
50 
51 static cl::opt<int>
52 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
53   "Maximum number of predicated jumps to be converted to New Value Jump"));
54 
55 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
56     cl::ZeroOrMore, cl::init(false),
57     cl::desc("Disable New Value Jumps"));
58 
59 namespace llvm {
60   FunctionPass *createHexagonNewValueJump();
61   void initializeHexagonNewValueJumpPass(PassRegistry&);
62 }
63 
64 
65 namespace {
66   struct HexagonNewValueJump : public MachineFunctionPass {
67     const HexagonInstrInfo    *QII;
68     const HexagonRegisterInfo *QRI;
69 
70   public:
71     static char ID;
72 
HexagonNewValueJump__anon1729ffcd0111::HexagonNewValueJump73     HexagonNewValueJump() : MachineFunctionPass(ID) {
74       initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
75     }
76 
getAnalysisUsage__anon1729ffcd0111::HexagonNewValueJump77     void getAnalysisUsage(AnalysisUsage &AU) const override {
78       AU.addRequired<MachineBranchProbabilityInfo>();
79       MachineFunctionPass::getAnalysisUsage(AU);
80     }
81 
getPassName__anon1729ffcd0111::HexagonNewValueJump82     const char *getPassName() const override {
83       return "Hexagon NewValueJump";
84     }
85 
86     bool runOnMachineFunction(MachineFunction &Fn) override;
getRequiredProperties__anon1729ffcd0111::HexagonNewValueJump87     MachineFunctionProperties getRequiredProperties() const override {
88       return MachineFunctionProperties().set(
89           MachineFunctionProperties::Property::AllVRegsAllocated);
90     }
91 
92   private:
93     /// \brief A handle to the branch probability pass.
94     const MachineBranchProbabilityInfo *MBPI;
95 
96     bool isNewValueJumpCandidate(const MachineInstr &MI) const;
97   };
98 
99 } // end of anonymous namespace
100 
101 char HexagonNewValueJump::ID = 0;
102 
103 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
104                       "Hexagon NewValueJump", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)105 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
106 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
107                     "Hexagon NewValueJump", false, false)
108 
109 
110 // We have identified this II could be feeder to NVJ,
111 // verify that it can be.
112 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
113                                       const TargetRegisterInfo *TRI,
114                                       MachineBasicBlock::iterator II,
115                                       MachineBasicBlock::iterator end,
116                                       MachineBasicBlock::iterator skip,
117                                       MachineFunction &MF) {
118 
119   // Predicated instruction can not be feeder to NVJ.
120   if (QII->isPredicated(*II))
121     return false;
122 
123   // Bail out if feederReg is a paired register (double regs in
124   // our case). One would think that we can check to see if a given
125   // register cmpReg1 or cmpReg2 is a sub register of feederReg
126   // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
127   // before the callsite of this function
128   // But we can not as it comes in the following fashion.
129   //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
130   //    %R0<def> = KILL %R0, %D0<imp-use,kill>
131   //    %P0<def> = CMPEQri %R0<kill>, 0
132   // Hence, we need to check if it's a KILL instruction.
133   if (II->getOpcode() == TargetOpcode::KILL)
134     return false;
135 
136 
137   // Make sure there there is no 'def' or 'use' of any of the uses of
138   // feeder insn between it's definition, this MI and jump, jmpInst
139   // skipping compare, cmpInst.
140   // Here's the example.
141   //    r21=memub(r22+r24<<#0)
142   //    p0 = cmp.eq(r21, #0)
143   //    r4=memub(r3+r21<<#0)
144   //    if (p0.new) jump:t .LBB29_45
145   // Without this check, it will be converted into
146   //    r4=memub(r3+r21<<#0)
147   //    r21=memub(r22+r24<<#0)
148   //    p0 = cmp.eq(r21, #0)
149   //    if (p0.new) jump:t .LBB29_45
150   // and result WAR hazards if converted to New Value Jump.
151 
152   for (unsigned i = 0; i < II->getNumOperands(); ++i) {
153     if (II->getOperand(i).isReg() &&
154         (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
155       MachineBasicBlock::iterator localII = II;
156       ++localII;
157       unsigned Reg = II->getOperand(i).getReg();
158       for (MachineBasicBlock::iterator localBegin = localII;
159                         localBegin != end; ++localBegin) {
160         if (localBegin == skip ) continue;
161         // Check for Subregisters too.
162         if (localBegin->modifiesRegister(Reg, TRI) ||
163             localBegin->readsRegister(Reg, TRI))
164           return false;
165       }
166     }
167   }
168   return true;
169 }
170 
171 // These are the common checks that need to performed
172 // to determine if
173 // 1. compare instruction can be moved before jump.
174 // 2. feeder to the compare instruction can be moved before jump.
commonChecksToProhibitNewValueJump(bool afterRA,MachineBasicBlock::iterator MII)175 static bool commonChecksToProhibitNewValueJump(bool afterRA,
176                           MachineBasicBlock::iterator MII) {
177 
178   // If store in path, bail out.
179   if (MII->getDesc().mayStore())
180     return false;
181 
182   // if call in path, bail out.
183   if (MII->getOpcode() == Hexagon::J2_call)
184     return false;
185 
186   // if NVJ is running prior to RA, do the following checks.
187   if (!afterRA) {
188     // The following Target Opcode instructions are spurious
189     // to new value jump. If they are in the path, bail out.
190     // KILL sets kill flag on the opcode. It also sets up a
191     // single register, out of pair.
192     //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
193     //    %R0<def> = KILL %R0, %D0<imp-use,kill>
194     //    %P0<def> = CMPEQri %R0<kill>, 0
195     // PHI can be anything after RA.
196     // COPY can remateriaze things in between feeder, compare and nvj.
197     if (MII->getOpcode() == TargetOpcode::KILL ||
198         MII->getOpcode() == TargetOpcode::PHI  ||
199         MII->getOpcode() == TargetOpcode::COPY)
200       return false;
201 
202     // The following pseudo Hexagon instructions sets "use" and "def"
203     // of registers by individual passes in the backend. At this time,
204     // we don't know the scope of usage and definitions of these
205     // instructions.
206     if (MII->getOpcode() == Hexagon::LDriw_pred     ||
207         MII->getOpcode() == Hexagon::STriw_pred)
208       return false;
209   }
210 
211   return true;
212 }
213 
canCompareBeNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,unsigned pReg,bool secondReg,bool optLocation,MachineBasicBlock::iterator end,MachineFunction & MF)214 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
215                                      const TargetRegisterInfo *TRI,
216                                      MachineBasicBlock::iterator II,
217                                      unsigned pReg,
218                                      bool secondReg,
219                                      bool optLocation,
220                                      MachineBasicBlock::iterator end,
221                                      MachineFunction &MF) {
222 
223   MachineInstr &MI = *II;
224 
225   // If the second operand of the compare is an imm, make sure it's in the
226   // range specified by the arch.
227   if (!secondReg) {
228     int64_t v = MI.getOperand(2).getImm();
229 
230     if (!(isUInt<5>(v) || ((MI.getOpcode() == Hexagon::C2_cmpeqi ||
231                             MI.getOpcode() == Hexagon::C2_cmpgti) &&
232                            (v == -1))))
233       return false;
234   }
235 
236   unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
237   cmpReg1 = MI.getOperand(1).getReg();
238 
239   if (secondReg) {
240     cmpOp2 = MI.getOperand(2).getReg();
241 
242     // Make sure that that second register is not from COPY
243     // At machine code level, we don't need this, but if we decide
244     // to move new value jump prior to RA, we would be needing this.
245     MachineRegisterInfo &MRI = MF.getRegInfo();
246     if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
247       MachineInstr *def = MRI.getVRegDef(cmpOp2);
248       if (def->getOpcode() == TargetOpcode::COPY)
249         return false;
250     }
251   }
252 
253   // Walk the instructions after the compare (predicate def) to the jump,
254   // and satisfy the following conditions.
255   ++II ;
256   for (MachineBasicBlock::iterator localII = II; localII != end;
257        ++localII) {
258 
259     // Check 1.
260     // If "common" checks fail, bail out.
261     if (!commonChecksToProhibitNewValueJump(optLocation, localII))
262       return false;
263 
264     // Check 2.
265     // If there is a def or use of predicate (result of compare), bail out.
266     if (localII->modifiesRegister(pReg, TRI) ||
267         localII->readsRegister(pReg, TRI))
268       return false;
269 
270     // Check 3.
271     // If there is a def of any of the use of the compare (operands of compare),
272     // bail out.
273     // Eg.
274     //    p0 = cmp.eq(r2, r0)
275     //    r2 = r4
276     //    if (p0.new) jump:t .LBB28_3
277     if (localII->modifiesRegister(cmpReg1, TRI) ||
278         (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
279       return false;
280   }
281   return true;
282 }
283 
284 
285 // Given a compare operator, return a matching New Value Jump compare operator.
286 // Make sure that MI here is included in isNewValueJumpCandidate.
getNewValueJumpOpcode(MachineInstr * MI,int reg,bool secondRegNewified,MachineBasicBlock * jmpTarget,const MachineBranchProbabilityInfo * MBPI)287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
288                                       bool secondRegNewified,
289                                       MachineBasicBlock *jmpTarget,
290                                       const MachineBranchProbabilityInfo
291                                       *MBPI) {
292   bool taken = false;
293   MachineBasicBlock *Src = MI->getParent();
294   const BranchProbability Prediction =
295     MBPI->getEdgeProbability(Src, jmpTarget);
296 
297   if (Prediction >= BranchProbability(1,2))
298     taken = true;
299 
300   switch (MI->getOpcode()) {
301     case Hexagon::C2_cmpeq:
302       return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
303                    : Hexagon::J4_cmpeq_t_jumpnv_nt;
304 
305     case Hexagon::C2_cmpeqi: {
306       if (reg >= 0)
307         return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
308                      : Hexagon::J4_cmpeqi_t_jumpnv_nt;
309       else
310         return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
311                      : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
312     }
313 
314     case Hexagon::C2_cmpgt: {
315       if (secondRegNewified)
316         return taken ? Hexagon::J4_cmplt_t_jumpnv_t
317                      : Hexagon::J4_cmplt_t_jumpnv_nt;
318       else
319         return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
320                      : Hexagon::J4_cmpgt_t_jumpnv_nt;
321     }
322 
323     case Hexagon::C2_cmpgti: {
324       if (reg >= 0)
325         return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
326                      : Hexagon::J4_cmpgti_t_jumpnv_nt;
327       else
328         return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
329                      : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
330     }
331 
332     case Hexagon::C2_cmpgtu: {
333       if (secondRegNewified)
334         return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
335                      : Hexagon::J4_cmpltu_t_jumpnv_nt;
336       else
337         return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
338                      : Hexagon::J4_cmpgtu_t_jumpnv_nt;
339     }
340 
341     case Hexagon::C2_cmpgtui:
342       return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
343                    : Hexagon::J4_cmpgtui_t_jumpnv_nt;
344 
345     case Hexagon::C4_cmpneq:
346       return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
347                    : Hexagon::J4_cmpeq_f_jumpnv_nt;
348 
349     case Hexagon::C4_cmplte:
350       if (secondRegNewified)
351         return taken ? Hexagon::J4_cmplt_f_jumpnv_t
352                      : Hexagon::J4_cmplt_f_jumpnv_nt;
353       return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
354                    : Hexagon::J4_cmpgt_f_jumpnv_nt;
355 
356     case Hexagon::C4_cmplteu:
357       if (secondRegNewified)
358         return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
359                      : Hexagon::J4_cmpltu_f_jumpnv_nt;
360       return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
361                    : Hexagon::J4_cmpgtu_f_jumpnv_nt;
362 
363     default:
364        llvm_unreachable("Could not find matching New Value Jump instruction.");
365   }
366   // return *some value* to avoid compiler warning
367   return 0;
368 }
369 
isNewValueJumpCandidate(const MachineInstr & MI) const370 bool HexagonNewValueJump::isNewValueJumpCandidate(
371     const MachineInstr &MI) const {
372   switch (MI.getOpcode()) {
373   case Hexagon::C2_cmpeq:
374   case Hexagon::C2_cmpeqi:
375   case Hexagon::C2_cmpgt:
376   case Hexagon::C2_cmpgti:
377   case Hexagon::C2_cmpgtu:
378   case Hexagon::C2_cmpgtui:
379   case Hexagon::C4_cmpneq:
380   case Hexagon::C4_cmplte:
381   case Hexagon::C4_cmplteu:
382     return true;
383 
384   default:
385     return false;
386   }
387 }
388 
389 
runOnMachineFunction(MachineFunction & MF)390 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
391 
392   DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
393                << "********** Function: "
394                << MF.getName() << "\n");
395 
396   if (skipFunction(*MF.getFunction()))
397     return false;
398 
399   // If we move NewValueJump before register allocation we'll need live variable
400   // analysis here too.
401 
402   QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
403   QRI = static_cast<const HexagonRegisterInfo *>(
404       MF.getSubtarget().getRegisterInfo());
405   MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
406 
407   if (DisableNewValueJumps) {
408     return false;
409   }
410 
411   int nvjCount = DbgNVJCount;
412   int nvjGenerated = 0;
413 
414   // Loop through all the bb's of the function
415   for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
416         MBBb != MBBe; ++MBBb) {
417     MachineBasicBlock *MBB = &*MBBb;
418 
419     DEBUG(dbgs() << "** dumping bb ** "
420                  << MBB->getNumber() << "\n");
421     DEBUG(MBB->dump());
422     DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
423     bool foundJump    = false;
424     bool foundCompare = false;
425     bool invertPredicate = false;
426     unsigned predReg = 0; // predicate reg of the jump.
427     unsigned cmpReg1 = 0;
428     int cmpOp2 = 0;
429     bool MO1IsKill = false;
430     bool MO2IsKill = false;
431     MachineBasicBlock::iterator jmpPos;
432     MachineBasicBlock::iterator cmpPos;
433     MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
434     MachineBasicBlock *jmpTarget = nullptr;
435     bool afterRA = false;
436     bool isSecondOpReg = false;
437     bool isSecondOpNewified = false;
438     // Traverse the basic block - bottom up
439     for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
440              MII != E;) {
441       MachineInstr &MI = *--MII;
442       if (MI.isDebugValue()) {
443         continue;
444       }
445 
446       if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
447         break;
448 
449       DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
450 
451       if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
452                          MI.getOpcode() == Hexagon::J2_jumpf ||
453                          MI.getOpcode() == Hexagon::J2_jumptnewpt ||
454                          MI.getOpcode() == Hexagon::J2_jumptnew ||
455                          MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
456                          MI.getOpcode() == Hexagon::J2_jumpfnew)) {
457         // This is where you would insert your compare and
458         // instr that feeds compare
459         jmpPos = MII;
460         jmpInstr = &MI;
461         predReg = MI.getOperand(0).getReg();
462         afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
463 
464         // If ifconverter had not messed up with the kill flags of the
465         // operands, the following check on the kill flag would suffice.
466         // if(!jmpInstr->getOperand(0).isKill()) break;
467 
468         // This predicate register is live out out of BB
469         // this would only work if we can actually use Live
470         // variable analysis on phy regs - but LLVM does not
471         // provide LV analysis on phys regs.
472         //if(LVs.isLiveOut(predReg, *MBB)) break;
473 
474         // Get all the successors of this block - which will always
475         // be 2. Check if the predicate register is live in in those
476         // successor. If yes, we can not delete the predicate -
477         // I am doing this only because LLVM does not provide LiveOut
478         // at the BB level.
479         bool predLive = false;
480         for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
481                             SIE = MBB->succ_end(); SI != SIE; ++SI) {
482           MachineBasicBlock* succMBB = *SI;
483          if (succMBB->isLiveIn(predReg)) {
484             predLive = true;
485           }
486         }
487         if (predLive)
488           break;
489 
490         if (!MI.getOperand(1).isMBB())
491           continue;
492         jmpTarget = MI.getOperand(1).getMBB();
493         foundJump = true;
494         if (MI.getOpcode() == Hexagon::J2_jumpf ||
495             MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
496             MI.getOpcode() == Hexagon::J2_jumpfnew) {
497           invertPredicate = true;
498         }
499         continue;
500       }
501 
502       // No new value jump if there is a barrier. A barrier has to be in its
503       // own packet. A barrier has zero operands. We conservatively bail out
504       // here if we see any instruction with zero operands.
505       if (foundJump && MI.getNumOperands() == 0)
506         break;
507 
508       if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
509           MI.getOperand(0).getReg() == predReg) {
510 
511         // Not all compares can be new value compare. Arch Spec: 7.6.1.1
512         if (isNewValueJumpCandidate(MI)) {
513 
514           assert(
515               (MI.getDesc().isCompare()) &&
516               "Only compare instruction can be collapsed into New Value Jump");
517           isSecondOpReg = MI.getOperand(2).isReg();
518 
519           if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
520                                         afterRA, jmpPos, MF))
521             break;
522 
523           cmpInstr = &MI;
524           cmpPos = MII;
525           foundCompare = true;
526 
527           // We need cmpReg1 and cmpOp2(imm or reg) while building
528           // new value jump instruction.
529           cmpReg1 = MI.getOperand(1).getReg();
530           if (MI.getOperand(1).isKill())
531             MO1IsKill = true;
532 
533           if (isSecondOpReg) {
534             cmpOp2 = MI.getOperand(2).getReg();
535             if (MI.getOperand(2).isKill())
536               MO2IsKill = true;
537           } else
538             cmpOp2 = MI.getOperand(2).getImm();
539           continue;
540         }
541       }
542 
543       if (foundCompare && foundJump) {
544 
545         // If "common" checks fail, bail out on this BB.
546         if (!commonChecksToProhibitNewValueJump(afterRA, MII))
547           break;
548 
549         bool foundFeeder = false;
550         MachineBasicBlock::iterator feederPos = MII;
551         if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
552             (MI.getOperand(0).getReg() == cmpReg1 ||
553              (isSecondOpReg &&
554               MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
555 
556           unsigned feederReg = MI.getOperand(0).getReg();
557 
558           // First try to see if we can get the feeder from the first operand
559           // of the compare. If we can not, and if secondOpReg is true
560           // (second operand of the compare is also register), try that one.
561           // TODO: Try to come up with some heuristic to figure out which
562           // feeder would benefit.
563 
564           if (feederReg == cmpReg1) {
565             if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
566               if (!isSecondOpReg)
567                 break;
568               else
569                 continue;
570             } else
571               foundFeeder = true;
572           }
573 
574           if (!foundFeeder &&
575                isSecondOpReg &&
576                feederReg == (unsigned) cmpOp2)
577             if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
578               break;
579 
580           if (isSecondOpReg) {
581             // In case of CMPLT, or CMPLTU, or EQ with the second register
582             // to newify, swap the operands.
583             if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
584                                      feederReg == (unsigned) cmpOp2) {
585               unsigned tmp = cmpReg1;
586               bool tmpIsKill = MO1IsKill;
587               cmpReg1 = cmpOp2;
588               MO1IsKill = MO2IsKill;
589               cmpOp2 = tmp;
590               MO2IsKill = tmpIsKill;
591             }
592 
593             // Now we have swapped the operands, all we need to check is,
594             // if the second operand (after swap) is the feeder.
595             // And if it is, make a note.
596             if (feederReg == (unsigned)cmpOp2)
597               isSecondOpNewified = true;
598           }
599 
600           // Now that we are moving feeder close the jump,
601           // make sure we are respecting the kill values of
602           // the operands of the feeder.
603 
604           bool updatedIsKill = false;
605           for (unsigned i = 0; i < MI.getNumOperands(); i++) {
606             MachineOperand &MO = MI.getOperand(i);
607             if (MO.isReg() && MO.isUse()) {
608               unsigned feederReg = MO.getReg();
609               for (MachineBasicBlock::iterator localII = feederPos,
610                    end = jmpPos; localII != end; localII++) {
611                 MachineInstr &localMI = *localII;
612                 for (unsigned j = 0; j < localMI.getNumOperands(); j++) {
613                   MachineOperand &localMO = localMI.getOperand(j);
614                   if (localMO.isReg() && localMO.isUse() &&
615                       localMO.isKill() && feederReg == localMO.getReg()) {
616                     // We found that there is kill of a use register
617                     // Set up a kill flag on the register
618                     localMO.setIsKill(false);
619                     MO.setIsKill();
620                     updatedIsKill = true;
621                     break;
622                   }
623                 }
624                 if (updatedIsKill) break;
625               }
626             }
627             if (updatedIsKill) break;
628           }
629 
630           MBB->splice(jmpPos, MI.getParent(), MI);
631           MBB->splice(jmpPos, MI.getParent(), cmpInstr);
632           DebugLoc dl = MI.getDebugLoc();
633           MachineInstr *NewMI;
634 
635           assert((isNewValueJumpCandidate(*cmpInstr)) &&
636                  "This compare is not a New Value Jump candidate.");
637           unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
638                                                isSecondOpNewified,
639                                                jmpTarget, MBPI);
640           if (invertPredicate)
641             opc = QII->getInvertedPredicatedOpcode(opc);
642 
643           if (isSecondOpReg)
644             NewMI = BuildMI(*MBB, jmpPos, dl,
645                                   QII->get(opc))
646                                     .addReg(cmpReg1, getKillRegState(MO1IsKill))
647                                     .addReg(cmpOp2, getKillRegState(MO2IsKill))
648                                     .addMBB(jmpTarget);
649 
650           else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi ||
651                     cmpInstr->getOpcode() == Hexagon::C2_cmpgti) &&
652                     cmpOp2 == -1 )
653             // Corresponding new-value compare jump instructions don't have the
654             // operand for -1 immediate value.
655             NewMI = BuildMI(*MBB, jmpPos, dl,
656                                   QII->get(opc))
657                                     .addReg(cmpReg1, getKillRegState(MO1IsKill))
658                                     .addMBB(jmpTarget);
659 
660           else
661             NewMI = BuildMI(*MBB, jmpPos, dl,
662                                   QII->get(opc))
663                                     .addReg(cmpReg1, getKillRegState(MO1IsKill))
664                                     .addImm(cmpOp2)
665                                     .addMBB(jmpTarget);
666 
667           assert(NewMI && "New Value Jump Instruction Not created!");
668           (void)NewMI;
669           if (cmpInstr->getOperand(0).isReg() &&
670               cmpInstr->getOperand(0).isKill())
671             cmpInstr->getOperand(0).setIsKill(false);
672           if (cmpInstr->getOperand(1).isReg() &&
673               cmpInstr->getOperand(1).isKill())
674             cmpInstr->getOperand(1).setIsKill(false);
675           cmpInstr->eraseFromParent();
676           jmpInstr->eraseFromParent();
677           ++nvjGenerated;
678           ++NumNVJGenerated;
679           break;
680         }
681       }
682     }
683   }
684 
685   return true;
686 
687 }
688 
createHexagonNewValueJump()689 FunctionPass *llvm::createHexagonNewValueJump() {
690   return new HexagonNewValueJump();
691 }
692