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1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16 
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include <vector>
21 
22 namespace llvm {
23 
24 /// MachineRegisterInfo - Keep track of information for virtual and physical
25 /// registers, including vreg register classes, use/def chains for registers,
26 /// etc.
27 class MachineRegisterInfo {
28   const TargetRegisterInfo *const TRI;
29 
30   /// IsSSA - True when the machine function is in SSA form and virtual
31   /// registers have a single def.
32   bool IsSSA;
33 
34   /// VRegInfo - Information we keep for each virtual register.
35   ///
36   /// Each element in this list contains the register class of the vreg and the
37   /// start of the use/def list for the register.
38   IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
39              VirtReg2IndexFunctor> VRegInfo;
40 
41   /// RegAllocHints - This vector records register allocation hints for virtual
42   /// registers. For each virtual register, it keeps a register and hint type
43   /// pair making up the allocation hint. Hint type is target specific except
44   /// for the value 0 which means the second value of the pair is the preferred
45   /// register for allocation. For example, if the hint is <0, 1024>, it means
46   /// the allocator should prefer the physical register allocated to the virtual
47   /// register of the hint.
48   IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
49 
50   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
51   /// physical registers.
52   MachineOperand **PhysRegUseDefLists;
53 
54   /// UsedPhysRegs - This is a bit vector that is computed and set by the
55   /// register allocator, and must be kept up to date by passes that run after
56   /// register allocation (though most don't modify this).  This is used
57   /// so that the code generator knows which callee save registers to save and
58   /// for other target specific uses.
59   BitVector UsedPhysRegs;
60 
61   /// LiveIns/LiveOuts - Keep track of the physical registers that are
62   /// livein/liveout of the function.  Live in values are typically arguments in
63   /// registers, live out values are typically return values in registers.
64   /// LiveIn values are allowed to have virtual registers associated with them,
65   /// stored in the second element.
66   std::vector<std::pair<unsigned, unsigned> > LiveIns;
67   std::vector<unsigned> LiveOuts;
68 
69   MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
70   void operator=(const MachineRegisterInfo&);      // DO NOT IMPLEMENT
71 public:
72   explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
73   ~MachineRegisterInfo();
74 
75   //===--------------------------------------------------------------------===//
76   // Function State
77   //===--------------------------------------------------------------------===//
78 
79   // isSSA - Returns true when the machine function is in SSA form. Early
80   // passes require the machine function to be in SSA form where every virtual
81   // register has a single defining instruction.
82   //
83   // The TwoAddressInstructionPass and PHIElimination passes take the machine
84   // function out of SSA form when they introduce multiple defs per virtual
85   // register.
isSSA()86   bool isSSA() const { return IsSSA; }
87 
88   // leaveSSA - Indicates that the machine function is no longer in SSA form.
leaveSSA()89   void leaveSSA() { IsSSA = false; }
90 
91   //===--------------------------------------------------------------------===//
92   // Register Info
93   //===--------------------------------------------------------------------===//
94 
95   /// reg_begin/reg_end - Provide iteration support to walk over all definitions
96   /// and uses of a register within the MachineFunction that corresponds to this
97   /// MachineRegisterInfo object.
98   template<bool Uses, bool Defs, bool SkipDebug>
99   class defusechain_iterator;
100 
101   /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
102   /// register.
103   typedef defusechain_iterator<true,true,false> reg_iterator;
reg_begin(unsigned RegNo)104   reg_iterator reg_begin(unsigned RegNo) const {
105     return reg_iterator(getRegUseDefListHead(RegNo));
106   }
reg_end()107   static reg_iterator reg_end() { return reg_iterator(0); }
108 
109   /// reg_empty - Return true if there are no instructions using or defining the
110   /// specified register (it may be live-in).
reg_empty(unsigned RegNo)111   bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
112 
113   /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
114   /// of the specified register, skipping those marked as Debug.
115   typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
reg_nodbg_begin(unsigned RegNo)116   reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
117     return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
118   }
reg_nodbg_end()119   static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
120 
121   /// reg_nodbg_empty - Return true if the only instructions using or defining
122   /// Reg are Debug instructions.
reg_nodbg_empty(unsigned RegNo)123   bool reg_nodbg_empty(unsigned RegNo) const {
124     return reg_nodbg_begin(RegNo) == reg_nodbg_end();
125   }
126 
127   /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
128   typedef defusechain_iterator<false,true,false> def_iterator;
def_begin(unsigned RegNo)129   def_iterator def_begin(unsigned RegNo) const {
130     return def_iterator(getRegUseDefListHead(RegNo));
131   }
def_end()132   static def_iterator def_end() { return def_iterator(0); }
133 
134   /// def_empty - Return true if there are no instructions defining the
135   /// specified register (it may be live-in).
def_empty(unsigned RegNo)136   bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
137 
138   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
139   typedef defusechain_iterator<true,false,false> use_iterator;
use_begin(unsigned RegNo)140   use_iterator use_begin(unsigned RegNo) const {
141     return use_iterator(getRegUseDefListHead(RegNo));
142   }
use_end()143   static use_iterator use_end() { return use_iterator(0); }
144 
145   /// use_empty - Return true if there are no instructions using the specified
146   /// register.
use_empty(unsigned RegNo)147   bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
148 
149   /// hasOneUse - Return true if there is exactly one instruction using the
150   /// specified register.
151   bool hasOneUse(unsigned RegNo) const;
152 
153   /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
154   /// specified register, skipping those marked as Debug.
155   typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
use_nodbg_begin(unsigned RegNo)156   use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
157     return use_nodbg_iterator(getRegUseDefListHead(RegNo));
158   }
use_nodbg_end()159   static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
160 
161   /// use_nodbg_empty - Return true if there are no non-Debug instructions
162   /// using the specified register.
use_nodbg_empty(unsigned RegNo)163   bool use_nodbg_empty(unsigned RegNo) const {
164     return use_nodbg_begin(RegNo) == use_nodbg_end();
165   }
166 
167   /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
168   /// instruction using the specified register.
169   bool hasOneNonDBGUse(unsigned RegNo) const;
170 
171   /// replaceRegWith - Replace all instances of FromReg with ToReg in the
172   /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
173   /// except that it also changes any definitions of the register as well.
174   void replaceRegWith(unsigned FromReg, unsigned ToReg);
175 
176   /// getRegUseDefListHead - Return the head pointer for the register use/def
177   /// list for the specified virtual or physical register.
getRegUseDefListHead(unsigned RegNo)178   MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
179     if (TargetRegisterInfo::isVirtualRegister(RegNo))
180       return VRegInfo[RegNo].second;
181     return PhysRegUseDefLists[RegNo];
182   }
183 
getRegUseDefListHead(unsigned RegNo)184   MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
185     if (TargetRegisterInfo::isVirtualRegister(RegNo))
186       return VRegInfo[RegNo].second;
187     return PhysRegUseDefLists[RegNo];
188   }
189 
190   /// getVRegDef - Return the machine instr that defines the specified virtual
191   /// register or null if none is found.  This assumes that the code is in SSA
192   /// form, so there should only be one definition.
193   MachineInstr *getVRegDef(unsigned Reg) const;
194 
195   /// clearKillFlags - Iterate over all the uses of the given register and
196   /// clear the kill flag from the MachineOperand. This function is used by
197   /// optimization passes which extend register lifetimes and need only
198   /// preserve conservative kill flag information.
199   void clearKillFlags(unsigned Reg) const;
200 
201 #ifndef NDEBUG
202   void dumpUses(unsigned RegNo) const;
203 #endif
204 
205   //===--------------------------------------------------------------------===//
206   // Virtual Register Info
207   //===--------------------------------------------------------------------===//
208 
209   /// getRegClass - Return the register class of the specified virtual register.
210   ///
getRegClass(unsigned Reg)211   const TargetRegisterClass *getRegClass(unsigned Reg) const {
212     return VRegInfo[Reg].first;
213   }
214 
215   /// setRegClass - Set the register class of the specified virtual register.
216   ///
217   void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
218 
219   /// constrainRegClass - Constrain the register class of the specified virtual
220   /// register to be a common subclass of RC and the current register class,
221   /// but only if the new class has at least MinNumRegs registers.  Return the
222   /// new register class, or NULL if no such class exists.
223   /// This should only be used when the constraint is known to be trivial, like
224   /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
225   ///
226   const TargetRegisterClass *constrainRegClass(unsigned Reg,
227                                                const TargetRegisterClass *RC,
228                                                unsigned MinNumRegs = 0);
229 
230   /// recomputeRegClass - Try to find a legal super-class of Reg's register
231   /// class that still satisfies the constraints from the instructions using
232   /// Reg.  Returns true if Reg was upgraded.
233   ///
234   /// This method can be used after constraints have been removed from a
235   /// virtual register, for example after removing instructions or splitting
236   /// the live range.
237   ///
238   bool recomputeRegClass(unsigned Reg, const TargetMachine&);
239 
240   /// createVirtualRegister - Create and return a new virtual register in the
241   /// function with the specified register class.
242   ///
243   unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
244 
245   /// getNumVirtRegs - Return the number of virtual registers created.
246   ///
getNumVirtRegs()247   unsigned getNumVirtRegs() const { return VRegInfo.size(); }
248 
249   /// setRegAllocationHint - Specify a register allocation hint for the
250   /// specified virtual register.
setRegAllocationHint(unsigned Reg,unsigned Type,unsigned PrefReg)251   void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
252     RegAllocHints[Reg].first  = Type;
253     RegAllocHints[Reg].second = PrefReg;
254   }
255 
256   /// getRegAllocationHint - Return the register allocation hint for the
257   /// specified virtual register.
258   std::pair<unsigned, unsigned>
getRegAllocationHint(unsigned Reg)259   getRegAllocationHint(unsigned Reg) const {
260     return RegAllocHints[Reg];
261   }
262 
263   /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
264   /// standard simple hint (Type == 0) is not set.
getSimpleHint(unsigned Reg)265   unsigned getSimpleHint(unsigned Reg) const {
266     std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
267     return Hint.first ? 0 : Hint.second;
268   }
269 
270 
271   //===--------------------------------------------------------------------===//
272   // Physical Register Use Info
273   //===--------------------------------------------------------------------===//
274 
275   /// isPhysRegUsed - Return true if the specified register is used in this
276   /// function.  This only works after register allocation.
isPhysRegUsed(unsigned Reg)277   bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
278 
279   /// setPhysRegUsed - Mark the specified register used in this function.
280   /// This should only be called during and after register allocation.
setPhysRegUsed(unsigned Reg)281   void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
282 
283   /// addPhysRegsUsed - Mark the specified registers used in this function.
284   /// This should only be called during and after register allocation.
addPhysRegsUsed(const BitVector & Regs)285   void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
286 
287   /// setPhysRegUnused - Mark the specified register unused in this function.
288   /// This should only be called during and after register allocation.
setPhysRegUnused(unsigned Reg)289   void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
290 
291   /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over
292   /// subregisters. That means that if R is used, so are all subregisters.
293   void closePhysRegsUsed(const TargetRegisterInfo&);
294 
295   //===--------------------------------------------------------------------===//
296   // LiveIn/LiveOut Management
297   //===--------------------------------------------------------------------===//
298 
299   /// addLiveIn/Out - Add the specified register as a live in/out.  Note that it
300   /// is an error to add the same register to the same set more than once.
301   void addLiveIn(unsigned Reg, unsigned vreg = 0) {
302     LiveIns.push_back(std::make_pair(Reg, vreg));
303   }
addLiveOut(unsigned Reg)304   void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
305 
306   // Iteration support for live in/out sets.  These sets are kept in sorted
307   // order by their register number.
308   typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
309   livein_iterator;
310   typedef std::vector<unsigned>::const_iterator liveout_iterator;
livein_begin()311   livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_end()312   livein_iterator livein_end()   const { return LiveIns.end(); }
livein_empty()313   bool            livein_empty() const { return LiveIns.empty(); }
liveout_begin()314   liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
liveout_end()315   liveout_iterator liveout_end()   const { return LiveOuts.end(); }
liveout_empty()316   bool             liveout_empty() const { return LiveOuts.empty(); }
317 
318   bool isLiveIn(unsigned Reg) const;
319   bool isLiveOut(unsigned Reg) const;
320 
321   /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
322   /// corresponding live-in physical register.
323   unsigned getLiveInPhysReg(unsigned VReg) const;
324 
325   /// getLiveInVirtReg - If PReg is a live-in physical register, return the
326   /// corresponding live-in physical register.
327   unsigned getLiveInVirtReg(unsigned PReg) const;
328 
329   /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
330   /// into the given entry block.
331   void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
332                         const TargetRegisterInfo &TRI,
333                         const TargetInstrInfo &TII);
334 
335 private:
336   void HandleVRegListReallocation();
337 
338 public:
339   /// defusechain_iterator - This class provides iterator support for machine
340   /// operands in the function that use or define a specific register.  If
341   /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
342   /// returns defs.  If neither are true then you are silly and it always
343   /// returns end().  If SkipDebug is true it skips uses marked Debug
344   /// when incrementing.
345   template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
346   class defusechain_iterator
347     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
348     MachineOperand *Op;
defusechain_iterator(MachineOperand * op)349     explicit defusechain_iterator(MachineOperand *op) : Op(op) {
350       // If the first node isn't one we're interested in, advance to one that
351       // we are interested in.
352       if (op) {
353         if ((!ReturnUses && op->isUse()) ||
354             (!ReturnDefs && op->isDef()) ||
355             (SkipDebug && op->isDebug()))
356           ++*this;
357       }
358     }
359     friend class MachineRegisterInfo;
360   public:
361     typedef std::iterator<std::forward_iterator_tag,
362                           MachineInstr, ptrdiff_t>::reference reference;
363     typedef std::iterator<std::forward_iterator_tag,
364                           MachineInstr, ptrdiff_t>::pointer pointer;
365 
defusechain_iterator(const defusechain_iterator & I)366     defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
defusechain_iterator()367     defusechain_iterator() : Op(0) {}
368 
369     bool operator==(const defusechain_iterator &x) const {
370       return Op == x.Op;
371     }
372     bool operator!=(const defusechain_iterator &x) const {
373       return !operator==(x);
374     }
375 
376     /// atEnd - return true if this iterator is equal to reg_end() on the value.
atEnd()377     bool atEnd() const { return Op == 0; }
378 
379     // Iterator traversal: forward iteration only
380     defusechain_iterator &operator++() {          // Preincrement
381       assert(Op && "Cannot increment end iterator!");
382       Op = Op->getNextOperandForReg();
383 
384       // If this is an operand we don't care about, skip it.
385       while (Op && ((!ReturnUses && Op->isUse()) ||
386                     (!ReturnDefs && Op->isDef()) ||
387                     (SkipDebug && Op->isDebug())))
388         Op = Op->getNextOperandForReg();
389 
390       return *this;
391     }
392     defusechain_iterator operator++(int) {        // Postincrement
393       defusechain_iterator tmp = *this; ++*this; return tmp;
394     }
395 
396     /// skipInstruction - move forward until reaching a different instruction.
397     /// Return the skipped instruction that is no longer pointed to, or NULL if
398     /// already pointing to end().
skipInstruction()399     MachineInstr *skipInstruction() {
400       if (!Op) return 0;
401       MachineInstr *MI = Op->getParent();
402       do ++*this;
403       while (Op && Op->getParent() == MI);
404       return MI;
405     }
406 
getOperand()407     MachineOperand &getOperand() const {
408       assert(Op && "Cannot dereference end iterator!");
409       return *Op;
410     }
411 
412     /// getOperandNo - Return the operand # of this MachineOperand in its
413     /// MachineInstr.
getOperandNo()414     unsigned getOperandNo() const {
415       assert(Op && "Cannot dereference end iterator!");
416       return Op - &Op->getParent()->getOperand(0);
417     }
418 
419     // Retrieve a reference to the current operand.
420     MachineInstr &operator*() const {
421       assert(Op && "Cannot dereference end iterator!");
422       return *Op->getParent();
423     }
424 
425     MachineInstr *operator->() const {
426       assert(Op && "Cannot dereference end iterator!");
427       return Op->getParent();
428     }
429   };
430 
431 };
432 
433 } // End llvm namespace
434 
435 #endif
436