1 /**************************************************************************
2 * ns83820.c: Etherboot device driver for the National Semiconductor 83820
3 * Written 2004 by Timothy Legge <tlegge@rogers.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Portions of this code based on:
20 * ns83820.c by Benjamin LaHaise with contributions
21 * for Linux kernel 2.4.x.
22 *
23 * Linux Driver Version 0.20, 20020610
24 *
25 * This development of this Etherboot driver was funded by:
26 *
27 * NXTV: http://www.nxtv.com/
28 *
29 * REVISION HISTORY:
30 * ================
31 *
32 * v1.0 02-16-2004 timlegge Initial port of Linux driver
33 * v1.1 02-19-2004 timlegge More rohbust transmit and poll
34 *
35 * Indent Options: indent -kr -i8
36 ***************************************************************************/
37
38 FILE_LICENCE ( GPL2_OR_LATER );
39
40 /* to get some global routines like printf */
41 #include "etherboot.h"
42 /* to get the interface to the body of the program */
43 #include "nic.h"
44 /* to get the PCI support functions, if this is a PCI NIC */
45 #include <gpxe/pci.h>
46
47 #if ARCH == ia64 /* Support 64-bit addressing */
48 #define USE_64BIT_ADDR
49 #endif
50
51 //#define DDEBUG
52 #ifdef DDEBUG
53 #define dprintf(x) printf x
54 #else
55 #define dprintf(x)
56 #endif
57
58 #define HZ 100
59
60 /* Condensed operations for readability. */
61 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
62 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
63
64 /* NIC specific static variables go here */
65
66 /* Global parameters. See MODULE_PARM near the bottom. */
67 // static int ihr = 2;
68 static int reset_phy = 0;
69 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
70
71 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
72 #define USE_64BIT_ADDR "+"
73 #endif
74
75 #if defined(USE_64BIT_ADDR)
76 #define TRY_DAC 1
77 #else
78 #define TRY_DAC 0
79 #endif
80
81 /* tunables */
82 #define RX_BUF_SIZE 1500 /* 8192 */
83
84 /* Must not exceed ~65000. */
85 #define NR_RX_DESC 64
86 #define NR_TX_DESC 1
87
88 /* not tunable *//* Extra 6 bytes for 64 bit alignment (divisable by 8) */
89 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) /* rx/tx mac addr + type */
90
91 #define MIN_TX_DESC_FREE 8
92
93 /* register defines */
94 #define CFGCS 0x04
95
96 #define CR_TXE 0x00000001
97 #define CR_TXD 0x00000002
98 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
99 * The Receive engine skips one descriptor and moves
100 * onto the next one!! */
101 #define CR_RXE 0x00000004
102 #define CR_RXD 0x00000008
103 #define CR_TXR 0x00000010
104 #define CR_RXR 0x00000020
105 #define CR_SWI 0x00000080
106 #define CR_RST 0x00000100
107
108 #define PTSCR_EEBIST_FAIL 0x00000001
109 #define PTSCR_EEBIST_EN 0x00000002
110 #define PTSCR_EELOAD_EN 0x00000004
111 #define PTSCR_RBIST_FAIL 0x000001b8
112 #define PTSCR_RBIST_DONE 0x00000200
113 #define PTSCR_RBIST_EN 0x00000400
114 #define PTSCR_RBIST_RST 0x00002000
115
116 #define MEAR_EEDI 0x00000001
117 #define MEAR_EEDO 0x00000002
118 #define MEAR_EECLK 0x00000004
119 #define MEAR_EESEL 0x00000008
120 #define MEAR_MDIO 0x00000010
121 #define MEAR_MDDIR 0x00000020
122 #define MEAR_MDC 0x00000040
123
124 #define ISR_TXDESC3 0x40000000
125 #define ISR_TXDESC2 0x20000000
126 #define ISR_TXDESC1 0x10000000
127 #define ISR_TXDESC0 0x08000000
128 #define ISR_RXDESC3 0x04000000
129 #define ISR_RXDESC2 0x02000000
130 #define ISR_RXDESC1 0x01000000
131 #define ISR_RXDESC0 0x00800000
132 #define ISR_TXRCMP 0x00400000
133 #define ISR_RXRCMP 0x00200000
134 #define ISR_DPERR 0x00100000
135 #define ISR_SSERR 0x00080000
136 #define ISR_RMABT 0x00040000
137 #define ISR_RTABT 0x00020000
138 #define ISR_RXSOVR 0x00010000
139 #define ISR_HIBINT 0x00008000
140 #define ISR_PHY 0x00004000
141 #define ISR_PME 0x00002000
142 #define ISR_SWI 0x00001000
143 #define ISR_MIB 0x00000800
144 #define ISR_TXURN 0x00000400
145 #define ISR_TXIDLE 0x00000200
146 #define ISR_TXERR 0x00000100
147 #define ISR_TXDESC 0x00000080
148 #define ISR_TXOK 0x00000040
149 #define ISR_RXORN 0x00000020
150 #define ISR_RXIDLE 0x00000010
151 #define ISR_RXEARLY 0x00000008
152 #define ISR_RXERR 0x00000004
153 #define ISR_RXDESC 0x00000002
154 #define ISR_RXOK 0x00000001
155
156 #define TXCFG_CSI 0x80000000
157 #define TXCFG_HBI 0x40000000
158 #define TXCFG_MLB 0x20000000
159 #define TXCFG_ATP 0x10000000
160 #define TXCFG_ECRETRY 0x00800000
161 #define TXCFG_BRST_DIS 0x00080000
162 #define TXCFG_MXDMA1024 0x00000000
163 #define TXCFG_MXDMA512 0x00700000
164 #define TXCFG_MXDMA256 0x00600000
165 #define TXCFG_MXDMA128 0x00500000
166 #define TXCFG_MXDMA64 0x00400000
167 #define TXCFG_MXDMA32 0x00300000
168 #define TXCFG_MXDMA16 0x00200000
169 #define TXCFG_MXDMA8 0x00100000
170
171 #define CFG_LNKSTS 0x80000000
172 #define CFG_SPDSTS 0x60000000
173 #define CFG_SPDSTS1 0x40000000
174 #define CFG_SPDSTS0 0x20000000
175 #define CFG_DUPSTS 0x10000000
176 #define CFG_TBI_EN 0x01000000
177 #define CFG_MODE_1000 0x00400000
178 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
179 * Read the Phy response and then configure the MAC accordingly */
180 #define CFG_AUTO_1000 0x00200000
181 #define CFG_PINT_CTL 0x001c0000
182 #define CFG_PINT_DUPSTS 0x00100000
183 #define CFG_PINT_LNKSTS 0x00080000
184 #define CFG_PINT_SPDSTS 0x00040000
185 #define CFG_TMRTEST 0x00020000
186 #define CFG_MRM_DIS 0x00010000
187 #define CFG_MWI_DIS 0x00008000
188 #define CFG_T64ADDR 0x00004000
189 #define CFG_PCI64_DET 0x00002000
190 #define CFG_DATA64_EN 0x00001000
191 #define CFG_M64ADDR 0x00000800
192 #define CFG_PHY_RST 0x00000400
193 #define CFG_PHY_DIS 0x00000200
194 #define CFG_EXTSTS_EN 0x00000100
195 #define CFG_REQALG 0x00000080
196 #define CFG_SB 0x00000040
197 #define CFG_POW 0x00000020
198 #define CFG_EXD 0x00000010
199 #define CFG_PESEL 0x00000008
200 #define CFG_BROM_DIS 0x00000004
201 #define CFG_EXT_125 0x00000002
202 #define CFG_BEM 0x00000001
203
204 #define EXTSTS_UDPPKT 0x00200000
205 #define EXTSTS_TCPPKT 0x00080000
206 #define EXTSTS_IPPKT 0x00020000
207
208 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
209
210 #define MIBC_MIBS 0x00000008
211 #define MIBC_ACLR 0x00000004
212 #define MIBC_FRZ 0x00000002
213 #define MIBC_WRN 0x00000001
214
215 #define PCR_PSEN (1 << 31)
216 #define PCR_PS_MCAST (1 << 30)
217 #define PCR_PS_DA (1 << 29)
218 #define PCR_STHI_8 (3 << 23)
219 #define PCR_STLO_4 (1 << 23)
220 #define PCR_FFHI_8K (3 << 21)
221 #define PCR_FFLO_4K (1 << 21)
222 #define PCR_PAUSE_CNT 0xFFFE
223
224 #define RXCFG_AEP 0x80000000
225 #define RXCFG_ARP 0x40000000
226 #define RXCFG_STRIPCRC 0x20000000
227 #define RXCFG_RX_FD 0x10000000
228 #define RXCFG_ALP 0x08000000
229 #define RXCFG_AIRL 0x04000000
230 #define RXCFG_MXDMA512 0x00700000
231 #define RXCFG_DRTH 0x0000003e
232 #define RXCFG_DRTH0 0x00000002
233
234 #define RFCR_RFEN 0x80000000
235 #define RFCR_AAB 0x40000000
236 #define RFCR_AAM 0x20000000
237 #define RFCR_AAU 0x10000000
238 #define RFCR_APM 0x08000000
239 #define RFCR_APAT 0x07800000
240 #define RFCR_APAT3 0x04000000
241 #define RFCR_APAT2 0x02000000
242 #define RFCR_APAT1 0x01000000
243 #define RFCR_APAT0 0x00800000
244 #define RFCR_AARP 0x00400000
245 #define RFCR_MHEN 0x00200000
246 #define RFCR_UHEN 0x00100000
247 #define RFCR_ULM 0x00080000
248
249 #define VRCR_RUDPE 0x00000080
250 #define VRCR_RTCPE 0x00000040
251 #define VRCR_RIPE 0x00000020
252 #define VRCR_IPEN 0x00000010
253 #define VRCR_DUTF 0x00000008
254 #define VRCR_DVTF 0x00000004
255 #define VRCR_VTREN 0x00000002
256 #define VRCR_VTDEN 0x00000001
257
258 #define VTCR_PPCHK 0x00000008
259 #define VTCR_GCHK 0x00000004
260 #define VTCR_VPPTI 0x00000002
261 #define VTCR_VGTI 0x00000001
262
263 #define CR 0x00
264 #define CFG 0x04
265 #define MEAR 0x08
266 #define PTSCR 0x0c
267 #define ISR 0x10
268 #define IMR 0x14
269 #define IER 0x18
270 #define IHR 0x1c
271 #define TXDP 0x20
272 #define TXDP_HI 0x24
273 #define TXCFG 0x28
274 #define GPIOR 0x2c
275 #define RXDP 0x30
276 #define RXDP_HI 0x34
277 #define RXCFG 0x38
278 #define PQCR 0x3c
279 #define WCSR 0x40
280 #define PCR 0x44
281 #define RFCR 0x48
282 #define RFDR 0x4c
283
284 #define SRR 0x58
285
286 #define VRCR 0xbc
287 #define VTCR 0xc0
288 #define VDR 0xc4
289 #define CCSR 0xcc
290
291 #define TBICR 0xe0
292 #define TBISR 0xe4
293 #define TANAR 0xe8
294 #define TANLPAR 0xec
295 #define TANER 0xf0
296 #define TESR 0xf4
297
298 #define TBICR_MR_AN_ENABLE 0x00001000
299 #define TBICR_MR_RESTART_AN 0x00000200
300
301 #define TBISR_MR_LINK_STATUS 0x00000020
302 #define TBISR_MR_AN_COMPLETE 0x00000004
303
304 #define TANAR_PS2 0x00000100
305 #define TANAR_PS1 0x00000080
306 #define TANAR_HALF_DUP 0x00000040
307 #define TANAR_FULL_DUP 0x00000020
308
309 #define GPIOR_GP5_OE 0x00000200
310 #define GPIOR_GP4_OE 0x00000100
311 #define GPIOR_GP3_OE 0x00000080
312 #define GPIOR_GP2_OE 0x00000040
313 #define GPIOR_GP1_OE 0x00000020
314 #define GPIOR_GP3_OUT 0x00000004
315 #define GPIOR_GP1_OUT 0x00000001
316
317 #define LINK_AUTONEGOTIATE 0x01
318 #define LINK_DOWN 0x02
319 #define LINK_UP 0x04
320
321
322 #define __kick_rx() writel(CR_RXE, ns->base + CR)
323
324 #define kick_rx() do { \
325 dprintf(("kick_rx: maybe kicking\n")); \
326 writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \
327 if (ns->next_rx == ns->next_empty) \
328 printf("uh-oh: next_rx == next_empty???\n"); \
329 __kick_rx(); \
330 } while(0)
331
332
333 #ifdef USE_64BIT_ADDR
334 #define HW_ADDR_LEN 8
335 #else
336 #define HW_ADDR_LEN 4
337 #endif
338
339 #define CMDSTS_OWN 0x80000000
340 #define CMDSTS_MORE 0x40000000
341 #define CMDSTS_INTR 0x20000000
342 #define CMDSTS_ERR 0x10000000
343 #define CMDSTS_OK 0x08000000
344 #define CMDSTS_LEN_MASK 0x0000ffff
345
346 #define CMDSTS_DEST_MASK 0x01800000
347 #define CMDSTS_DEST_SELF 0x00800000
348 #define CMDSTS_DEST_MULTI 0x01000000
349
350 #define DESC_SIZE 8 /* Should be cache line sized */
351
352 #ifdef USE_64BIT_ADDR
353 struct ring_desc {
354 uint64_t link;
355 uint64_t bufptr;
356 u32 cmdsts;
357 u32 extsts; /* Extended status field */
358 };
359 #else
360 struct ring_desc {
361 u32 link;
362 u32 bufptr;
363 u32 cmdsts;
364 u32 extsts; /* Extended status field */
365 };
366 #endif
367
368 /* Private Storage for the NIC */
369 static struct ns83820_private {
370 u8 *base;
371 int up;
372 long idle;
373 u32 *next_rx_desc;
374 u16 next_rx, next_empty;
375 u32 cur_rx;
376 u32 *descs;
377 unsigned ihr;
378 u32 CFG_cache;
379 u32 MEAR_cache;
380 u32 IMR_cache;
381 int linkstate;
382 u16 tx_done_idx;
383 u16 tx_idx;
384 u16 tx_intr_idx;
385 u32 phy_descs;
386 u32 *tx_descs;
387
388 } nsx;
389 static struct ns83820_private *ns;
390
391 /* Define the TX and RX Descriptor and Buffers */
392 struct {
393 struct ring_desc tx_ring[NR_TX_DESC] __attribute__ ((aligned(8)));
394 unsigned char txb[NR_TX_DESC * REAL_RX_BUF_SIZE];
395 struct ring_desc rx_ring[NR_RX_DESC] __attribute__ ((aligned(8)));
396 unsigned char rxb[NR_RX_DESC * REAL_RX_BUF_SIZE]
397 __attribute__ ((aligned(8)));
398 } ns83820_bufs __shared;
399 #define tx_ring ns83820_bufs.tx_ring
400 #define rx_ring ns83820_bufs.rx_ring
401 #define txb ns83820_bufs.txb
402 #define rxb ns83820_bufs.rxb
403
phy_intr(struct nic * nic __unused)404 static void phy_intr(struct nic *nic __unused)
405 {
406 static char *speeds[] =
407 { "10", "100", "1000", "1000(?)", "1000F" };
408 u32 cfg, new_cfg;
409 u32 tbisr, tanar, tanlpar;
410 int speed, fullduplex, newlinkstate;
411
412 cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY;
413 if (ns->CFG_cache & CFG_TBI_EN) {
414 /* we have an optical transceiver */
415 tbisr = readl(ns->base + TBISR);
416 tanar = readl(ns->base + TANAR);
417 tanlpar = readl(ns->base + TANLPAR);
418 dprintf(("phy_intr: tbisr=%hX, tanar=%hX, tanlpar=%hX\n",
419 tbisr, tanar, tanlpar));
420
421 if ((fullduplex = (tanlpar & TANAR_FULL_DUP)
422 && (tanar & TANAR_FULL_DUP))) {
423
424 /* both of us are full duplex */
425 writel(readl(ns->base + TXCFG)
426 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
427 ns->base + TXCFG);
428 writel(readl(ns->base + RXCFG) | RXCFG_RX_FD,
429 ns->base + RXCFG);
430 /* Light up full duplex LED */
431 writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT,
432 ns->base + GPIOR);
433
434 } else if (((tanlpar & TANAR_HALF_DUP)
435 && (tanar & TANAR_HALF_DUP))
436 || ((tanlpar & TANAR_FULL_DUP)
437 && (tanar & TANAR_HALF_DUP))
438 || ((tanlpar & TANAR_HALF_DUP)
439 && (tanar & TANAR_FULL_DUP))) {
440
441 /* one or both of us are half duplex */
442 writel((readl(ns->base + TXCFG)
443 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
444 ns->base + TXCFG);
445 writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD,
446 ns->base + RXCFG);
447 /* Turn off full duplex LED */
448 writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT,
449 ns->base + GPIOR);
450 }
451
452 speed = 4; /* 1000F */
453
454 } else {
455 /* we have a copper transceiver */
456 new_cfg =
457 ns->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
458
459 if (cfg & CFG_SPDSTS1)
460 new_cfg |= CFG_MODE_1000;
461 else
462 new_cfg &= ~CFG_MODE_1000;
463
464 speed = ((cfg / CFG_SPDSTS0) & 3);
465 fullduplex = (cfg & CFG_DUPSTS);
466
467 if (fullduplex)
468 new_cfg |= CFG_SB;
469
470 if ((cfg & CFG_LNKSTS) &&
471 ((new_cfg ^ ns->CFG_cache) & CFG_MODE_1000)) {
472 writel(new_cfg, ns->base + CFG);
473 ns->CFG_cache = new_cfg;
474 }
475
476 ns->CFG_cache &= ~CFG_SPDSTS;
477 ns->CFG_cache |= cfg & CFG_SPDSTS;
478 }
479
480 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
481
482 if (newlinkstate & LINK_UP && ns->linkstate != newlinkstate) {
483 printf("link now %s mbps, %s duplex and up.\n",
484 speeds[speed], fullduplex ? "full" : "half");
485 } else if (newlinkstate & LINK_DOWN
486 && ns->linkstate != newlinkstate) {
487 printf("link now down.\n");
488 }
489 ns->linkstate = newlinkstate;
490 }
491 static void ns83820_set_multicast(struct nic *nic __unused);
ns83820_setup_rx(struct nic * nic)492 static void ns83820_setup_rx(struct nic *nic)
493 {
494 unsigned i;
495 ns->idle = 1;
496 ns->next_rx = 0;
497 ns->next_rx_desc = ns->descs;
498 ns->next_empty = 0;
499 ns->cur_rx = 0;
500
501
502 for (i = 0; i < NR_RX_DESC; i++) {
503 rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
504 rx_ring[i].bufptr =
505 virt_to_le32desc(&rxb[i * REAL_RX_BUF_SIZE]);
506 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
507 rx_ring[i].extsts = cpu_to_le32(0);
508 }
509 // No need to wrap the ring
510 // rx_ring[i].link = virt_to_le32desc(&rx_ring[0]);
511 writel(0, ns->base + RXDP_HI);
512 writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP);
513
514 dprintf(("starting receiver\n"));
515
516 writel(0x0001, ns->base + CCSR);
517 writel(0, ns->base + RFCR);
518 writel(0x7fc00000, ns->base + RFCR);
519 writel(0xffc00000, ns->base + RFCR);
520
521 ns->up = 1;
522
523 phy_intr(nic);
524
525 /* Okay, let it rip */
526 ns->IMR_cache |= ISR_PHY;
527 ns->IMR_cache |= ISR_RXRCMP;
528 //dev->IMR_cache |= ISR_RXERR;
529 //dev->IMR_cache |= ISR_RXOK;
530 ns->IMR_cache |= ISR_RXORN;
531 ns->IMR_cache |= ISR_RXSOVR;
532 ns->IMR_cache |= ISR_RXDESC;
533 ns->IMR_cache |= ISR_RXIDLE;
534 ns->IMR_cache |= ISR_TXDESC;
535 ns->IMR_cache |= ISR_TXIDLE;
536
537 // No reason to enable interupts...
538 // writel(ns->IMR_cache, ns->base + IMR);
539 // writel(1, ns->base + IER);
540 ns83820_set_multicast(nic);
541 kick_rx();
542 }
543
544
ns83820_do_reset(struct nic * nic __unused,u32 which)545 static void ns83820_do_reset(struct nic *nic __unused, u32 which)
546 {
547 dprintf(("resetting chip...\n"));
548 writel(which, ns->base + CR);
549 do {
550
551 } while (readl(ns->base + CR) & which);
552 dprintf(("okay!\n"));
553 }
554
ns83820_reset(struct nic * nic)555 static void ns83820_reset(struct nic *nic)
556 {
557 unsigned i;
558 dprintf(("ns83820_reset\n"));
559
560 writel(0, ns->base + PQCR);
561
562 ns83820_setup_rx(nic);
563
564 for (i = 0; i < NR_TX_DESC; i++) {
565 tx_ring[i].link = 0;
566 tx_ring[i].bufptr = 0;
567 tx_ring[i].cmdsts = cpu_to_le32(0);
568 tx_ring[i].extsts = cpu_to_le32(0);
569 }
570
571 ns->tx_idx = 0;
572 ns->tx_done_idx = 0;
573 writel(0, ns->base + TXDP_HI);
574 return;
575 }
ns83820_getmac(struct nic * nic __unused,u8 * mac)576 static void ns83820_getmac(struct nic *nic __unused, u8 * mac)
577 {
578 unsigned i;
579 for (i = 0; i < 3; i++) {
580 u32 data;
581 /* Read from the perfect match memory: this is loaded by
582 * the chip from the EEPROM via the EELOAD self test.
583 */
584 writel(i * 2, ns->base + RFCR);
585 data = readl(ns->base + RFDR);
586 *mac++ = data;
587 *mac++ = data >> 8;
588 }
589 }
590
ns83820_set_multicast(struct nic * nic __unused)591 static void ns83820_set_multicast(struct nic *nic __unused)
592 {
593 u8 *rfcr = ns->base + RFCR;
594 u32 and_mask = 0xffffffff;
595 u32 or_mask = 0;
596 u32 val;
597
598 /* Support Multicast */
599 and_mask &= ~(RFCR_AAU | RFCR_AAM);
600 or_mask |= RFCR_AAM;
601 val = (readl(rfcr) & and_mask) | or_mask;
602 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
603 writel(val & ~RFCR_RFEN, rfcr);
604 writel(val, rfcr);
605
606 }
ns83820_run_bist(struct nic * nic __unused,const char * name,u32 enable,u32 done,u32 fail)607 static void ns83820_run_bist(struct nic *nic __unused, const char *name,
608 u32 enable, u32 done, u32 fail)
609 {
610 int timed_out = 0;
611 long start;
612 u32 status;
613 int loops = 0;
614
615 dprintf(("start %s\n", name))
616
617 start = currticks();
618
619 writel(enable, ns->base + PTSCR);
620 for (;;) {
621 loops++;
622 status = readl(ns->base + PTSCR);
623 if (!(status & enable))
624 break;
625 if (status & done)
626 break;
627 if (status & fail)
628 break;
629 if ((currticks() - start) >= HZ) {
630 timed_out = 1;
631 break;
632 }
633 }
634
635 if (status & fail)
636 printf("%s failed! (0x%hX & 0x%hX)\n", name, (unsigned int) status,
637 (unsigned int) fail);
638 else if (timed_out)
639 printf("run_bist %s timed out! (%hX)\n", name, (unsigned int) status);
640 dprintf(("done %s in %d loops\n", name, loops));
641 }
642
643 /*************************************
644 Check Link
645 *************************************/
ns83820_check_intr(struct nic * nic)646 static void ns83820_check_intr(struct nic *nic) {
647 int i;
648 u32 isr = readl(ns->base + ISR);
649 if(ISR_PHY & isr)
650 phy_intr(nic);
651 if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr)
652 kick_rx();
653 for (i = 0; i < NR_RX_DESC; i++) {
654 if (rx_ring[i].cmdsts == CMDSTS_OWN) {
655 // rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
656 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
657 }
658 }
659 }
660 /**************************************************************************
661 POLL - Wait for a frame
662 ***************************************************************************/
ns83820_poll(struct nic * nic,int retrieve)663 static int ns83820_poll(struct nic *nic, int retrieve)
664 {
665 /* return true if there's an ethernet packet ready to read */
666 /* nic->packet should contain data on return */
667 /* nic->packetlen should contain length of data */
668 u32 cmdsts;
669 int entry = ns->cur_rx;
670
671 ns83820_check_intr(nic);
672
673 cmdsts = le32_to_cpu(rx_ring[entry].cmdsts);
674
675 if ( ! ( (CMDSTS_OWN & (cmdsts)) && (cmdsts != (CMDSTS_OWN)) ) )
676 return 0;
677
678 if ( ! retrieve ) return 1;
679
680 if (! (CMDSTS_OK & cmdsts) )
681 return 0;
682
683 nic->packetlen = cmdsts & 0xffff;
684 memcpy(nic->packet,
685 rxb + (entry * REAL_RX_BUF_SIZE),
686 nic->packetlen);
687 // rx_ring[entry].link = 0;
688 rx_ring[entry].cmdsts = cpu_to_le32(CMDSTS_OWN);
689
690 ns->cur_rx = ++ns->cur_rx % NR_RX_DESC;
691
692 if (ns->cur_rx == 0) /* We have wrapped the ring */
693 kick_rx();
694
695 return 1;
696 }
697
kick_tx(struct nic * nic __unused)698 static inline void kick_tx(struct nic *nic __unused)
699 {
700 dprintf(("kick_tx\n"));
701 writel(CR_TXE, ns->base + CR);
702 }
703
704 /**************************************************************************
705 TRANSMIT - Transmit a frame
706 ***************************************************************************/
ns83820_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)707 static void ns83820_transmit(struct nic *nic, const char *d, /* Destination */
708 unsigned int t, /* Type */
709 unsigned int s, /* size */
710 const char *p)
711 { /* Packet */
712 /* send the packet to destination */
713
714 u16 nstype;
715 u32 cmdsts, extsts;
716 int cur_tx = 0;
717 u32 isr = readl(ns->base + ISR);
718 if (ISR_TXIDLE & isr)
719 kick_tx(nic);
720 /* point to the current txb incase multiple tx_rings are used */
721 memcpy(txb, d, ETH_ALEN);
722 memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
723 nstype = htons((u16) t);
724 memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
725 memcpy(txb + ETH_HLEN, p, s);
726 s += ETH_HLEN;
727 s &= 0x0FFF;
728 while (s < ETH_ZLEN)
729 txb[s++] = '\0';
730
731 /* Setup the transmit descriptor */
732 extsts = 0;
733 extsts |= EXTSTS_UDPPKT;
734
735 tx_ring[cur_tx].bufptr = virt_to_le32desc(&txb);
736 tx_ring[cur_tx].extsts = cpu_to_le32(extsts);
737
738 cmdsts = cpu_to_le32(0);
739 cmdsts |= cpu_to_le32(CMDSTS_OWN | s);
740 tx_ring[cur_tx].cmdsts = cpu_to_le32(cmdsts);
741
742 writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP);
743 kick_tx(nic);
744 }
745
746 /**************************************************************************
747 DISABLE - Turn off ethernet interface
748 ***************************************************************************/
ns83820_disable(struct nic * nic)749 static void ns83820_disable ( struct nic *nic ) {
750
751 /* put the card in its initial state */
752 /* This function serves 3 purposes.
753 * This disables DMA and interrupts so we don't receive
754 * unexpected packets or interrupts from the card after
755 * etherboot has finished.
756 * This frees resources so etherboot may use
757 * this driver on another interface
758 * This allows etherboot to reinitialize the interface
759 * if something is something goes wrong.
760 */
761 /* disable interrupts */
762 writel(0, ns->base + IMR);
763 writel(0, ns->base + IER);
764 readl(ns->base + IER);
765
766 ns->up = 0;
767
768 ns83820_do_reset(nic, CR_RST);
769
770 ns->IMR_cache &=
771 ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY |
772 ISR_RXIDLE);
773 writel(ns->IMR_cache, ns->base + IMR);
774
775 /* touch the pci bus... */
776 readl(ns->base + IMR);
777
778 /* assumes the transmitter is already disabled and reset */
779 writel(0, ns->base + RXDP_HI);
780 writel(0, ns->base + RXDP);
781 }
782
783 /**************************************************************************
784 IRQ - Enable, Disable, or Force interrupts
785 ***************************************************************************/
ns83820_irq(struct nic * nic __unused,irq_action_t action __unused)786 static void ns83820_irq(struct nic *nic __unused, irq_action_t action __unused)
787 {
788 switch ( action ) {
789 case DISABLE :
790 break;
791 case ENABLE :
792 break;
793 case FORCE :
794 break;
795 }
796 }
797
798 static struct nic_operations ns83820_operations = {
799 .connect = dummy_connect,
800 .poll = ns83820_poll,
801 .transmit = ns83820_transmit,
802 .irq = ns83820_irq,
803
804 };
805
806 static struct pci_device_id ns83820_nics[] = {
807 PCI_ROM(0x100b, 0x0022, "ns83820", "National Semiconductor 83820", 0),
808 };
809
810 PCI_DRIVER ( ns83820_driver, ns83820_nics, PCI_NO_CLASS );
811
812 /**************************************************************************
813 PROBE - Look for an adapter, this routine's visible to the outside
814 ***************************************************************************/
815
816 #define board_found 1
817 #define valid_link 0
ns83820_probe(struct nic * nic,struct pci_device * pci)818 static int ns83820_probe ( struct nic *nic, struct pci_device *pci ) {
819
820 long addr;
821 int using_dac = 0;
822
823 if (pci->ioaddr == 0)
824 return 0;
825
826 printf("ns83820.c: Found %s, vendor=0x%hX, device=0x%hX\n",
827 pci->driver_name, pci->vendor, pci->device);
828
829 /* point to private storage */
830 ns = &nsx;
831
832 adjust_pci_device(pci);
833
834 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_1);
835
836 ns->base = ioremap(addr, (1UL << 12));
837
838 if (!ns->base)
839 return 0;
840
841 nic->irqno = 0;
842 nic->ioaddr = pci->ioaddr & ~3;
843
844 /* disable interrupts */
845 writel(0, ns->base + IMR);
846 writel(0, ns->base + IER);
847 readl(ns->base + IER);
848
849 ns->IMR_cache = 0;
850
851 ns83820_do_reset(nic, CR_RST);
852
853 /* Must reset the ram bist before running it */
854 writel(PTSCR_RBIST_RST, ns->base + PTSCR);
855 ns83820_run_bist(nic, "sram bist", PTSCR_RBIST_EN,
856 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
857 ns83820_run_bist(nic, "eeprom bist", PTSCR_EEBIST_EN, 0,
858 PTSCR_EEBIST_FAIL);
859 ns83820_run_bist(nic, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
860
861 /* I love config registers */
862 ns->CFG_cache = readl(ns->base + CFG);
863
864 if ((ns->CFG_cache & CFG_PCI64_DET)) {
865 printf("%s: detected 64 bit PCI data bus.\n", pci->driver_name);
866 /*dev->CFG_cache |= CFG_DATA64_EN; */
867 if (!(ns->CFG_cache & CFG_DATA64_EN))
868 printf
869 ("%s: EEPROM did not enable 64 bit bus. Disabled.\n",
870 pci->driver_name);
871 } else
872 ns->CFG_cache &= ~(CFG_DATA64_EN);
873
874 ns->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
875 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
876 CFG_M64ADDR);
877 ns->CFG_cache |=
878 CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
879 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
880 ns->CFG_cache |= CFG_REQALG;
881 ns->CFG_cache |= CFG_POW;
882 ns->CFG_cache |= CFG_TMRTEST;
883
884 /* When compiled with 64 bit addressing, we must always enable
885 * the 64 bit descriptor format.
886 */
887 #ifdef USE_64BIT_ADDR
888 ns->CFG_cache |= CFG_M64ADDR;
889 #endif
890
891 //FIXME: Enable section on dac or remove this
892 if (using_dac)
893 ns->CFG_cache |= CFG_T64ADDR;
894
895 /* Big endian mode does not seem to do what the docs suggest */
896 ns->CFG_cache &= ~CFG_BEM;
897
898 /* setup optical transceiver if we have one */
899 if (ns->CFG_cache & CFG_TBI_EN) {
900 dprintf(("%s: enabling optical transceiver\n", pci->driver_name));
901 writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR);
902
903 /* setup auto negotiation feature advertisement */
904 writel(readl(ns->base + TANAR)
905 | TANAR_HALF_DUP | TANAR_FULL_DUP,
906 ns->base + TANAR);
907
908 /* start auto negotiation */
909 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
910 ns->base + TBICR);
911 writel(TBICR_MR_AN_ENABLE, ns->base + TBICR);
912 ns->linkstate = LINK_AUTONEGOTIATE;
913
914 ns->CFG_cache |= CFG_MODE_1000;
915 }
916 writel(ns->CFG_cache, ns->base + CFG);
917 dprintf(("CFG: %hX\n", ns->CFG_cache));
918
919 /* FIXME: reset_phy is defaulted to 0, should we reset anyway? */
920 if (reset_phy) {
921 dprintf(("%s: resetting phy\n", pci->driver_name));
922 writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG);
923 writel(ns->CFG_cache, ns->base + CFG);
924 }
925 #if 0 /* Huh? This sets the PCI latency register. Should be done via
926 * the PCI layer. FIXME.
927 */
928 if (readl(dev->base + SRR))
929 writel(readl(dev->base + 0x20c) | 0xfe00,
930 dev->base + 0x20c);
931 #endif
932
933 /* Note! The DMA burst size interacts with packet
934 * transmission, such that the largest packet that
935 * can be transmitted is 8192 - FLTH - burst size.
936 * If only the transmit fifo was larger...
937 */
938 /* Ramit : 1024 DMA is not a good idea, it ends up banging
939 * some DELL and COMPAQ SMP systems */
940 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
941 | ((1600 / 32) * 0x100), ns->base + TXCFG);
942
943 /* Set Rx to full duplex, don't accept runt, errored, long or length
944 * range errored packets. Use 512 byte DMA.
945 */
946 /* Ramit : 1024 DMA is not a good idea, it ends up banging
947 * some DELL and COMPAQ SMP systems
948 * Turn on ALP, only we are accpeting Jumbo Packets */
949 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
950 | RXCFG_STRIPCRC
951 //| RXCFG_ALP
952 | (RXCFG_MXDMA512) | 0, ns->base + RXCFG);
953
954 /* Disable priority queueing */
955 writel(0, ns->base + PQCR);
956
957 /* Enable IP checksum validation and detetion of VLAN headers.
958 * Note: do not set the reject options as at least the 0x102
959 * revision of the chip does not properly accept IP fragments
960 * at least for UDP.
961 */
962 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
963 * the MAC it calculates the packetsize AFTER stripping the VLAN
964 * header, and if a VLAN Tagged packet of 64 bytes is received (like
965 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
966 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
967 * it discrards it!. These guys......
968 */
969 writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR);
970
971 /* Enable per-packet TCP/UDP/IP checksumming */
972 writel(VTCR_PPCHK, ns->base + VTCR);
973
974 /* Ramit : Enable async and sync pause frames */
975 // writel(0, ns->base + PCR);
976 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
977 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
978 ns->base + PCR);
979
980 /* Disable Wake On Lan */
981 writel(0, ns->base + WCSR);
982
983 ns83820_getmac(nic, nic->node_addr);
984
985 if (using_dac) {
986 dprintf(("%s: using 64 bit addressing.\n", pci->driver_name));
987 }
988
989 dprintf(("%s: DP83820 %d.%d: %! io=0x%hX\n",
990 pci->driver_name,
991 (unsigned) readl(ns->base + SRR) >> 8,
992 (unsigned) readl(ns->base + SRR) & 0xff,
993 nic->node_addr, pci->ioaddr));
994
995 #ifdef PHY_CODE_IS_FINISHED
996 ns83820_probe_phy(dev);
997 #endif
998
999 ns83820_reset(nic);
1000 /* point to NIC specific routines */
1001 nic->nic_op = &ns83820_operations;
1002 return 1;
1003 }
1004
1005 DRIVER ( "NS83820/PCI", nic_driver, pci_driver, ns83820_driver,
1006 ns83820_probe, ns83820_disable );
1007
1008 /*
1009 * Local variables:
1010 * c-basic-offset: 8
1011 * c-indent-level: 8
1012 * tab-width: 8
1013 * End:
1014 */
1015