1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29
30 #include "r300_context.h"
31 #include "r300_cb.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
r300_emit_blend_state(struct r300_context * r300,unsigned size,void * state)39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 struct pipe_surface *cb;
46 CS_LOCALS(r300);
47
48 cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL;
49
50 if (cb) {
51 if (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
52 WRITE_CS_TABLE(blend->cb_noclamp, size);
53 } else if (cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT) {
54 WRITE_CS_TABLE(blend->cb_noclamp_noalpha, size);
55 } else {
56 unsigned swz = r300_surface(cb)->colormask_swizzle;
57 WRITE_CS_TABLE(blend->cb_clamp[swz], size);
58 }
59 } else {
60 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
61 }
62 }
63
r300_emit_blend_color_state(struct r300_context * r300,unsigned size,void * state)64 void r300_emit_blend_color_state(struct r300_context* r300,
65 unsigned size, void* state)
66 {
67 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
68 CS_LOCALS(r300);
69
70 WRITE_CS_TABLE(bc->cb, size);
71 }
72
r300_emit_clip_state(struct r300_context * r300,unsigned size,void * state)73 void r300_emit_clip_state(struct r300_context* r300,
74 unsigned size, void* state)
75 {
76 struct r300_clip_state* clip = (struct r300_clip_state*)state;
77 CS_LOCALS(r300);
78
79 WRITE_CS_TABLE(clip->cb, size);
80 }
81
r300_emit_dsa_state(struct r300_context * r300,unsigned size,void * state)82 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
83 {
84 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
85 struct pipe_framebuffer_state* fb =
86 (struct pipe_framebuffer_state*)r300->fb_state.state;
87 boolean is_r500 = r300->screen->caps.is_r500;
88 CS_LOCALS(r300);
89 uint32_t alpha_func = dsa->alpha_function;
90
91 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
92 * 16-bit (FG_ALPHA_VALUE). */
93 if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) {
94 struct pipe_surface *cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL;
95
96 if (cb &&
97 (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
98 cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT)) {
99 alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE;
100 } else {
101 alpha_func |= R500_FG_ALPHA_FUNC_8BIT;
102 }
103 }
104
105 /* Setup alpha-to-coverage. */
106 if (r300->alpha_to_coverage && r300->msaa_enable) {
107 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
108 alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE |
109 R300_FG_ALPHA_FUNC_CFG_3_OF_6;
110 }
111
112 BEGIN_CS(size);
113 OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func);
114 OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2);
115 END_CS;
116 }
117
get_rc_constant_state(float vec[4],struct r300_context * r300,struct rc_constant * constant)118 static void get_rc_constant_state(
119 float vec[4],
120 struct r300_context * r300,
121 struct rc_constant * constant)
122 {
123 struct r300_textures_state* texstate = r300->textures_state.state;
124 struct r300_resource *tex;
125
126 assert(constant->Type == RC_CONSTANT_STATE);
127
128 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
129 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
130 * state factors. */
131
132 switch (constant->u.State[0]) {
133 /* Factor for converting rectangle coords to
134 * normalized coords. Should only show up on non-r500. */
135 case RC_STATE_R300_TEXRECT_FACTOR:
136 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
137 vec[0] = 1.0 / tex->tex.width0;
138 vec[1] = 1.0 / tex->tex.height0;
139 vec[2] = 0;
140 vec[3] = 1;
141 break;
142
143 case RC_STATE_R300_TEXSCALE_FACTOR:
144 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
145 /* Add a small number to the texture size to work around rounding errors in hw. */
146 vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f);
147 vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f);
148 vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f);
149 vec[3] = 1;
150 break;
151
152 case RC_STATE_R300_VIEWPORT_SCALE:
153 vec[0] = r300->viewport.scale[0];
154 vec[1] = r300->viewport.scale[1];
155 vec[2] = r300->viewport.scale[2];
156 vec[3] = 1;
157 break;
158
159 case RC_STATE_R300_VIEWPORT_OFFSET:
160 vec[0] = r300->viewport.translate[0];
161 vec[1] = r300->viewport.translate[1];
162 vec[2] = r300->viewport.translate[2];
163 vec[3] = 1;
164 break;
165
166 default:
167 fprintf(stderr, "r300: Implementation error: "
168 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
169 vec[0] = 0;
170 vec[1] = 0;
171 vec[2] = 0;
172 vec[3] = 1;
173 }
174 }
175
176 /* Convert a normal single-precision float into the 7.16 format
177 * used by the R300 fragment shader.
178 */
pack_float24(float f)179 uint32_t pack_float24(float f)
180 {
181 union {
182 float fl;
183 uint32_t u;
184 } u;
185 float mantissa;
186 int exponent;
187 uint32_t float24 = 0;
188
189 if (f == 0.0)
190 return 0;
191
192 u.fl = f;
193
194 mantissa = frexpf(f, &exponent);
195
196 /* Handle -ve */
197 if (mantissa < 0) {
198 float24 |= (1 << 23);
199 mantissa = mantissa * -1.0;
200 }
201 /* Handle exponent, bias of 63 */
202 exponent += 62;
203 float24 |= (exponent << 16);
204 /* Kill 7 LSB of mantissa */
205 float24 |= (u.u & 0x7FFFFF) >> 7;
206
207 return float24;
208 }
209
r300_emit_fs(struct r300_context * r300,unsigned size,void * state)210 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
211 {
212 struct r300_fragment_shader *fs = r300_fs(r300);
213 CS_LOCALS(r300);
214
215 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
216 }
217
r300_emit_fs_constants(struct r300_context * r300,unsigned size,void * state)218 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
219 {
220 struct r300_fragment_shader *fs = r300_fs(r300);
221 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
222 unsigned count = fs->shader->externals_count;
223 unsigned i, j;
224 CS_LOCALS(r300);
225
226 if (count == 0)
227 return;
228
229 BEGIN_CS(size);
230 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
231 if (buf->remap_table){
232 for (i = 0; i < count; i++) {
233 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
234 for (j = 0; j < 4; j++)
235 OUT_CS(pack_float24(data[j]));
236 }
237 } else {
238 for (i = 0; i < count; i++)
239 for (j = 0; j < 4; j++)
240 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
241 }
242
243 END_CS;
244 }
245
r300_emit_fs_rc_constant_state(struct r300_context * r300,unsigned size,void * state)246 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
247 {
248 struct r300_fragment_shader *fs = r300_fs(r300);
249 struct rc_constant_list *constants = &fs->shader->code.constants;
250 unsigned i;
251 unsigned count = fs->shader->rc_state_count;
252 unsigned first = fs->shader->externals_count;
253 unsigned end = constants->Count;
254 unsigned j;
255 CS_LOCALS(r300);
256
257 if (count == 0)
258 return;
259
260 BEGIN_CS(size);
261 for(i = first; i < end; ++i) {
262 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
263 float data[4];
264
265 get_rc_constant_state(data, r300, &constants->Constants[i]);
266
267 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
268 for (j = 0; j < 4; j++)
269 OUT_CS(pack_float24(data[j]));
270 }
271 }
272 END_CS;
273 }
274
r500_emit_fs(struct r300_context * r300,unsigned size,void * state)275 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
276 {
277 struct r300_fragment_shader *fs = r300_fs(r300);
278 CS_LOCALS(r300);
279
280 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
281 }
282
r500_emit_fs_constants(struct r300_context * r300,unsigned size,void * state)283 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
284 {
285 struct r300_fragment_shader *fs = r300_fs(r300);
286 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
287 unsigned count = fs->shader->externals_count;
288 CS_LOCALS(r300);
289
290 if (count == 0)
291 return;
292
293 BEGIN_CS(size);
294 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
295 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
296 if (buf->remap_table){
297 for (unsigned i = 0; i < count; i++) {
298 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
299 OUT_CS_TABLE(data, 4);
300 }
301 } else {
302 OUT_CS_TABLE(buf->ptr, count * 4);
303 }
304 END_CS;
305 }
306
r500_emit_fs_rc_constant_state(struct r300_context * r300,unsigned size,void * state)307 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
308 {
309 struct r300_fragment_shader *fs = r300_fs(r300);
310 struct rc_constant_list *constants = &fs->shader->code.constants;
311 unsigned i;
312 unsigned count = fs->shader->rc_state_count;
313 unsigned first = fs->shader->externals_count;
314 unsigned end = constants->Count;
315 CS_LOCALS(r300);
316
317 if (count == 0)
318 return;
319
320 BEGIN_CS(size);
321 for(i = first; i < end; ++i) {
322 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
323 float data[4];
324
325 get_rc_constant_state(data, r300, &constants->Constants[i]);
326
327 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
328 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
329 (i & R500_GA_US_VECTOR_INDEX_MASK));
330 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
331 OUT_CS_TABLE(data, 4);
332 }
333 }
334 END_CS;
335 }
336
r300_emit_gpu_flush(struct r300_context * r300,unsigned size,void * state)337 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
338 {
339 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
340 struct pipe_framebuffer_state* fb =
341 (struct pipe_framebuffer_state*)r300->fb_state.state;
342 uint32_t height = fb->height;
343 uint32_t width = fb->width;
344 CS_LOCALS(r300);
345
346 if (r300->cbzb_clear) {
347 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
348
349 height = surf->cbzb_height;
350 width = surf->cbzb_width;
351 }
352
353 DBG(r300, DBG_SCISSOR,
354 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
355 width, height, r300->cbzb_clear ? "YES" : "NO");
356
357 BEGIN_CS(size);
358
359 /* Set up scissors.
360 * By writing to the SC registers, SC & US assert idle. */
361 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
362 if (r300->screen->caps.is_r500) {
363 OUT_CS(0);
364 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
365 ((height - 1) << R300_SCISSORS_Y_SHIFT));
366 } else {
367 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
368 (1440 << R300_SCISSORS_Y_SHIFT));
369 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
370 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
371 }
372
373 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
374 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
375 END_CS;
376 }
377
r300_emit_aa_state(struct r300_context * r300,unsigned size,void * state)378 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
379 {
380 struct r300_aa_state *aa = (struct r300_aa_state*)state;
381 CS_LOCALS(r300);
382
383 BEGIN_CS(size);
384 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
385
386 if (aa->dest) {
387 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3);
388 OUT_CS(aa->dest->offset);
389 OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK);
390 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE |
391 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE);
392 OUT_CS_RELOC(aa->dest);
393 } else {
394 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0);
395 }
396
397 END_CS;
398 }
399
r300_emit_fb_state(struct r300_context * r300,unsigned size,void * state)400 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
401 {
402 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
403 struct r300_surface* surf;
404 unsigned i;
405 uint32_t rb3d_cctl = 0;
406
407 CS_LOCALS(r300);
408
409 BEGIN_CS(size);
410
411 if (r300->screen->caps.is_r500) {
412 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
413 }
414 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */
415 if (fb->nr_cbufs && r300->fb_multiwrite) {
416 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
417 }
418 if (r300->cmask_in_use) {
419 rb3d_cctl |= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE |
420 R300_RB3D_CCTL_CMASK_ENABLE;
421 }
422
423 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
424
425 /* Set up colorbuffers. */
426 for (i = 0; i < fb->nr_cbufs; i++) {
427 surf = r300_surface(r300_get_nonnull_cb(fb, i));
428
429 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
430 OUT_CS_RELOC(surf);
431
432 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
433 OUT_CS_RELOC(surf);
434
435 if (r300->cmask_in_use && i == 0) {
436 OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0);
437 OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask);
438 OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value);
439 if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) {
440 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
441 OUT_CS(r300->color_clear_value_ar);
442 OUT_CS(r300->color_clear_value_gb);
443 }
444 }
445 }
446
447 /* Set up the ZB part of the CBZB clear. */
448 if (r300->cbzb_clear) {
449 surf = r300_surface(fb->cbufs[0]);
450
451 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
452
453 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
454 OUT_CS_RELOC(surf);
455
456 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
457 OUT_CS_RELOC(surf);
458
459 DBG(r300, DBG_CBZB,
460 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
461 surf->cbzb_pitch);
462 }
463 /* Set up a zbuffer. */
464 else if (fb->zsbuf) {
465 surf = r300_surface(fb->zsbuf);
466
467 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
468
469 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
470 OUT_CS_RELOC(surf);
471
472 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
473 OUT_CS_RELOC(surf);
474
475 if (r300->hyperz_enabled) {
476 /* HiZ RAM. */
477 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
478 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
479 /* Z Mask RAM. (compressed zbuffer) */
480 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
481 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
482 }
483 }
484
485 END_CS;
486 }
487
r300_emit_hyperz_state(struct r300_context * r300,unsigned size,void * state)488 void r300_emit_hyperz_state(struct r300_context *r300,
489 unsigned size, void *state)
490 {
491 struct r300_hyperz_state *z = state;
492 CS_LOCALS(r300);
493
494 if (z->flush)
495 WRITE_CS_TABLE(&z->cb_flush_begin, size);
496 else
497 WRITE_CS_TABLE(&z->cb_begin, size - 2);
498 }
499
r300_emit_hyperz_end(struct r300_context * r300)500 void r300_emit_hyperz_end(struct r300_context *r300)
501 {
502 struct r300_hyperz_state z =
503 *(struct r300_hyperz_state*)r300->hyperz_state.state;
504
505 z.flush = 1;
506 z.zb_bw_cntl = 0;
507 z.zb_depthclearvalue = 0;
508 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
509 z.gb_z_peq_config = 0;
510
511 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
512 }
513
514 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \
515 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \
516 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \
517 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \
518 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
519
r300_get_mspos(int index,unsigned * p)520 static unsigned r300_get_mspos(int index, unsigned *p)
521 {
522 unsigned reg, i, distx, disty, dist;
523
524 if (index == 0) {
525 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
526 * followed by a (Y,X) pair containing the minimum distance from the pixel
527 * edge:
528 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
529 *
530 * There is a quirk when setting D0_X. The value represents the distance
531 * from the left edge of the pixel quad to the first sample in subpixels.
532 * All values less than eight should use the actual value, but „7‟ should
533 * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
534 */
535 distx = 11;
536 for (i = 0; i < 12; i += 2) {
537 if (p[i] < distx)
538 distx = p[i];
539 }
540
541 disty = 11;
542 for (i = 1; i < 12; i += 2) {
543 if (p[i] < disty)
544 disty = p[i];
545 }
546
547 if (distx == 8)
548 distx = 7;
549
550 reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx);
551 } else {
552 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
553 * followed by the minimum distance from the pixel edge (not sure if X or Y):
554 * X3, Y3, X4, Y4, X5, Y5, D1
555 */
556 dist = 11;
557 for (i = 0; i < 12; i++) {
558 if (p[i] < dist)
559 dist = p[i];
560 }
561
562 reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0);
563 }
564 return reg;
565 }
566
r300_emit_fb_state_pipelined(struct r300_context * r300,unsigned size,void * state)567 void r300_emit_fb_state_pipelined(struct r300_context *r300,
568 unsigned size, void *state)
569 {
570 /* The sample coordinates are in the range [0,11], because
571 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
572 *
573 * Some sample coordinates reach to neighboring pixels and should not be used.
574 * (e.g. Y=11)
575 *
576 * The unused samples must be set to the positions of other valid samples. */
577 static unsigned sample_locs_1x[12] = {
578 6,6, 6,6, 6,6, 6,6, 6,6, 6,6
579 };
580 static unsigned sample_locs_2x[12] = {
581 3,9, 9,3, 9,3, 9,3, 9,3, 9,3
582 };
583 static unsigned sample_locs_4x[12] = {
584 4,4, 8,8, 2,10, 10,2, 10,2, 10,2
585 };
586 static unsigned sample_locs_6x[12] = {
587 3,1, 7,3, 11,5, 1,7, 5,9, 9,10
588 };
589
590 struct pipe_framebuffer_state* fb =
591 (struct pipe_framebuffer_state*)r300->fb_state.state;
592 unsigned i, num_cbufs = fb->nr_cbufs;
593 unsigned mspos0, mspos1;
594 CS_LOCALS(r300);
595
596 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
597 * marked as UNUSED in the US block. */
598 if (r300->fb_multiwrite) {
599 num_cbufs = MIN2(num_cbufs, 1);
600 }
601
602 BEGIN_CS(size);
603
604 /* Colorbuffer format in the US block.
605 * (must be written after unpipelined regs) */
606 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
607 for (i = 0; i < num_cbufs; i++) {
608 OUT_CS(r300_surface(r300_get_nonnull_cb(fb, i))->format);
609 }
610 for (; i < 1; i++) {
611 OUT_CS(R300_US_OUT_FMT_C4_8 |
612 R300_C0_SEL_B | R300_C1_SEL_G |
613 R300_C2_SEL_R | R300_C3_SEL_A);
614 }
615 for (; i < 4; i++) {
616 OUT_CS(R300_US_OUT_FMT_UNUSED);
617 }
618
619 /* Set sample positions. It depends on the framebuffer sample count.
620 * These are pipelined regs and as such cannot be moved to the AA state.
621 */
622 switch (r300->num_samples) {
623 default:
624 mspos0 = r300_get_mspos(0, sample_locs_1x);
625 mspos1 = r300_get_mspos(1, sample_locs_1x);
626 break;
627 case 2:
628 mspos0 = r300_get_mspos(0, sample_locs_2x);
629 mspos1 = r300_get_mspos(1, sample_locs_2x);
630 break;
631 case 4:
632 mspos0 = r300_get_mspos(0, sample_locs_4x);
633 mspos1 = r300_get_mspos(1, sample_locs_4x);
634 break;
635 case 6:
636 mspos0 = r300_get_mspos(0, sample_locs_6x);
637 mspos1 = r300_get_mspos(1, sample_locs_6x);
638 break;
639 }
640
641 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
642 OUT_CS(mspos0);
643 OUT_CS(mspos1);
644 END_CS;
645 }
646
r300_emit_query_start(struct r300_context * r300,unsigned size,void * state)647 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
648 {
649 struct r300_query *query = r300->query_current;
650 CS_LOCALS(r300);
651
652 if (!query)
653 return;
654
655 BEGIN_CS(size);
656 if (r300->screen->caps.family == CHIP_RV530) {
657 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
658 } else {
659 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
660 }
661 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
662 END_CS;
663 query->begin_emitted = TRUE;
664 }
665
r300_emit_query_end_frag_pipes(struct r300_context * r300,struct r300_query * query)666 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
667 struct r300_query *query)
668 {
669 struct r300_capabilities* caps = &r300->screen->caps;
670 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes;
671 CS_LOCALS(r300);
672
673 assert(gb_pipes);
674
675 BEGIN_CS(6 * gb_pipes + 2);
676 /* I'm not so sure I like this switch, but it's hard to be elegant
677 * when there's so many special cases...
678 *
679 * So here's the basic idea. For each pipe, enable writes to it only,
680 * then put out the relocation for ZPASS_ADDR, taking into account a
681 * 4-byte offset for each pipe. RV380 and older are special; they have
682 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
683 * so there's a chipset cap for that. */
684 switch (gb_pipes) {
685 case 4:
686 /* pipe 3 only */
687 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
688 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
689 OUT_CS_RELOC(r300->query_current);
690 case 3:
691 /* pipe 2 only */
692 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
693 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
694 OUT_CS_RELOC(r300->query_current);
695 case 2:
696 /* pipe 1 only */
697 /* As mentioned above, accommodate RV380 and older. */
698 OUT_CS_REG(R300_SU_REG_DEST,
699 1 << (caps->high_second_pipe ? 3 : 1));
700 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
701 OUT_CS_RELOC(r300->query_current);
702 case 1:
703 /* pipe 0 only */
704 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
705 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
706 OUT_CS_RELOC(r300->query_current);
707 break;
708 default:
709 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
710 " pixel pipes!\n", gb_pipes);
711 abort();
712 }
713
714 /* And, finally, reset it to normal... */
715 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
716 END_CS;
717 }
718
rv530_emit_query_end_single_z(struct r300_context * r300,struct r300_query * query)719 static void rv530_emit_query_end_single_z(struct r300_context *r300,
720 struct r300_query *query)
721 {
722 CS_LOCALS(r300);
723
724 BEGIN_CS(8);
725 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
726 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
727 OUT_CS_RELOC(r300->query_current);
728 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
729 END_CS;
730 }
731
rv530_emit_query_end_double_z(struct r300_context * r300,struct r300_query * query)732 static void rv530_emit_query_end_double_z(struct r300_context *r300,
733 struct r300_query *query)
734 {
735 CS_LOCALS(r300);
736
737 BEGIN_CS(14);
738 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
739 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
740 OUT_CS_RELOC(r300->query_current);
741 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
742 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
743 OUT_CS_RELOC(r300->query_current);
744 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
745 END_CS;
746 }
747
r300_emit_query_end(struct r300_context * r300)748 void r300_emit_query_end(struct r300_context* r300)
749 {
750 struct r300_capabilities *caps = &r300->screen->caps;
751 struct r300_query *query = r300->query_current;
752
753 if (!query)
754 return;
755
756 if (query->begin_emitted == FALSE)
757 return;
758
759 if (caps->family == CHIP_RV530) {
760 if (r300->screen->info.r300_num_z_pipes == 2)
761 rv530_emit_query_end_double_z(r300, query);
762 else
763 rv530_emit_query_end_single_z(r300, query);
764 } else
765 r300_emit_query_end_frag_pipes(r300, query);
766
767 query->begin_emitted = FALSE;
768 query->num_results += query->num_pipes;
769
770 /* XXX grab all the results and reset the counter. */
771 if (query->num_results >= query->buf->size / 4 - 4) {
772 query->num_results = (query->buf->size / 4) / 2;
773 fprintf(stderr, "r300: Rewinding OQBO...\n");
774 }
775 }
776
r300_emit_invariant_state(struct r300_context * r300,unsigned size,void * state)777 void r300_emit_invariant_state(struct r300_context *r300,
778 unsigned size, void *state)
779 {
780 CS_LOCALS(r300);
781 WRITE_CS_TABLE(state, size);
782 }
783
r300_emit_rs_state(struct r300_context * r300,unsigned size,void * state)784 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
785 {
786 struct r300_rs_state* rs = state;
787 CS_LOCALS(r300);
788
789 BEGIN_CS(size);
790 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
791 if (rs->polygon_offset_enable) {
792 if (r300->zbuffer_bpp == 16) {
793 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
794 } else {
795 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
796 }
797 }
798 END_CS;
799 }
800
r300_emit_rs_block_state(struct r300_context * r300,unsigned size,void * state)801 void r300_emit_rs_block_state(struct r300_context* r300,
802 unsigned size, void* state)
803 {
804 struct r300_rs_block* rs = (struct r300_rs_block*)state;
805 unsigned i;
806 /* It's the same for both INST and IP tables */
807 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
808 CS_LOCALS(r300);
809
810 if (DBG_ON(r300, DBG_RS_BLOCK)) {
811 r500_dump_rs_block(rs);
812
813 fprintf(stderr, "r300: RS emit:\n");
814
815 for (i = 0; i < count; i++)
816 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
817
818 for (i = 0; i < count; i++)
819 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
820
821 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
822 rs->count, rs->inst_count);
823 }
824
825 BEGIN_CS(size);
826 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
827 OUT_CS(rs->vap_vtx_state_cntl);
828 OUT_CS(rs->vap_vsm_vtx_assm);
829 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
830 OUT_CS(rs->vap_out_vtx_fmt[0]);
831 OUT_CS(rs->vap_out_vtx_fmt[1]);
832 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
833 OUT_CS(rs->gb_enable);
834
835 if (r300->screen->caps.is_r500) {
836 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
837 } else {
838 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
839 }
840 OUT_CS_TABLE(rs->ip, count);
841
842 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
843 OUT_CS(rs->count);
844 OUT_CS(rs->inst_count);
845
846 if (r300->screen->caps.is_r500) {
847 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
848 } else {
849 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
850 }
851 OUT_CS_TABLE(rs->inst, count);
852 END_CS;
853 }
854
r300_emit_sample_mask(struct r300_context * r300,unsigned size,void * state)855 void r300_emit_sample_mask(struct r300_context *r300,
856 unsigned size, void *state)
857 {
858 unsigned mask = (*(unsigned*)state) & ((1 << 6)-1);
859 CS_LOCALS(r300);
860
861 BEGIN_CS(size);
862 OUT_CS_REG(R300_SC_SCREENDOOR,
863 mask | (mask << 6) | (mask << 12) | (mask << 18));
864 END_CS;
865 }
866
r300_emit_scissor_state(struct r300_context * r300,unsigned size,void * state)867 void r300_emit_scissor_state(struct r300_context* r300,
868 unsigned size, void* state)
869 {
870 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
871 CS_LOCALS(r300);
872
873 BEGIN_CS(size);
874 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
875 if (r300->screen->caps.is_r500) {
876 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
877 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
878 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
879 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
880 } else {
881 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
882 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
883 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
884 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
885 }
886 END_CS;
887 }
888
r300_emit_textures_state(struct r300_context * r300,unsigned size,void * state)889 void r300_emit_textures_state(struct r300_context *r300,
890 unsigned size, void *state)
891 {
892 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
893 struct r300_texture_sampler_state *texstate;
894 struct r300_resource *tex;
895 unsigned i;
896 boolean has_us_format = r300->screen->caps.has_us_format;
897 CS_LOCALS(r300);
898
899 BEGIN_CS(size);
900 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
901
902 for (i = 0; i < allstate->count; i++) {
903 if ((1 << i) & allstate->tx_enable) {
904 texstate = &allstate->regs[i];
905 tex = r300_resource(allstate->sampler_views[i]->base.texture);
906
907 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
908 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
909 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
910 texstate->border_color);
911
912 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
913 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
914 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
915
916 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
917 OUT_CS_RELOC(tex);
918
919 if (has_us_format) {
920 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
921 texstate->format.us_format0);
922 }
923 }
924 }
925 END_CS;
926 }
927
r300_emit_vertex_arrays(struct r300_context * r300,int offset,boolean indexed,int instance_id)928 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
929 boolean indexed, int instance_id)
930 {
931 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
932 struct pipe_vertex_element *velem = r300->velems->velem;
933 struct r300_resource *buf;
934 int i;
935 unsigned vertex_array_count = r300->velems->count;
936 unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
937 struct pipe_vertex_buffer *vb1, *vb2;
938 unsigned *hw_format_size = r300->velems->format_size;
939 unsigned size1, size2, offset1, offset2, stride1, stride2;
940 CS_LOCALS(r300);
941
942 BEGIN_CS(2 + packet_size + vertex_array_count * 2);
943 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
944 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
945
946 if (instance_id == -1) {
947 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
948 for (i = 0; i < vertex_array_count - 1; i += 2) {
949 vb1 = &vbuf[velem[i].vertex_buffer_index];
950 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
951 size1 = hw_format_size[i];
952 size2 = hw_format_size[i+1];
953
954 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
955 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
956 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
957 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
958 }
959
960 if (vertex_array_count & 1) {
961 vb1 = &vbuf[velem[i].vertex_buffer_index];
962 size1 = hw_format_size[i];
963
964 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
965 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
966 }
967
968 for (i = 0; i < vertex_array_count; i++) {
969 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
970 OUT_CS_RELOC(buf);
971 }
972 } else {
973 /* Instanced arrays. */
974 for (i = 0; i < vertex_array_count - 1; i += 2) {
975 vb1 = &vbuf[velem[i].vertex_buffer_index];
976 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
977 size1 = hw_format_size[i];
978 size2 = hw_format_size[i+1];
979
980 if (velem[i].instance_divisor) {
981 stride1 = 0;
982 offset1 = vb1->buffer_offset + velem[i].src_offset +
983 (instance_id / velem[i].instance_divisor) * vb1->stride;
984 } else {
985 stride1 = vb1->stride;
986 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
987 }
988 if (velem[i+1].instance_divisor) {
989 stride2 = 0;
990 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
991 (instance_id / velem[i+1].instance_divisor) * vb2->stride;
992 } else {
993 stride2 = vb2->stride;
994 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
995 }
996
997 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
998 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
999 OUT_CS(offset1);
1000 OUT_CS(offset2);
1001 }
1002
1003 if (vertex_array_count & 1) {
1004 vb1 = &vbuf[velem[i].vertex_buffer_index];
1005 size1 = hw_format_size[i];
1006
1007 if (velem[i].instance_divisor) {
1008 stride1 = 0;
1009 offset1 = vb1->buffer_offset + velem[i].src_offset +
1010 (instance_id / velem[i].instance_divisor) * vb1->stride;
1011 } else {
1012 stride1 = vb1->stride;
1013 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
1014 }
1015
1016 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
1017 OUT_CS(offset1);
1018 }
1019
1020 for (i = 0; i < vertex_array_count; i++) {
1021 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
1022 OUT_CS_RELOC(buf);
1023 }
1024 }
1025 END_CS;
1026 }
1027
r300_emit_vertex_arrays_swtcl(struct r300_context * r300,boolean indexed)1028 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
1029 {
1030 CS_LOCALS(r300);
1031
1032 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
1033 "vertex size %d\n", r300->vbo,
1034 r300->vertex_info.size);
1035 /* Set the pointer to our vertex buffer. The emitted values are this:
1036 * PACKET3 [3D_LOAD_VBPNTR]
1037 * COUNT [1]
1038 * FORMAT [size | stride << 8]
1039 * OFFSET [offset into BO]
1040 * VBPNTR [relocated BO]
1041 */
1042 BEGIN_CS(7);
1043 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
1044 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
1045 OUT_CS(r300->vertex_info.size |
1046 (r300->vertex_info.size << 8));
1047 OUT_CS(r300->draw_vbo_offset);
1048 OUT_CS(0);
1049
1050 assert(r300->vbo);
1051 OUT_CS(0xc0001000); /* PKT3_NOP */
1052 OUT_CS(r300->rws->cs_lookup_buffer(r300->cs, r300->vbo) * 4);
1053 END_CS;
1054 }
1055
r300_emit_vertex_stream_state(struct r300_context * r300,unsigned size,void * state)1056 void r300_emit_vertex_stream_state(struct r300_context* r300,
1057 unsigned size, void* state)
1058 {
1059 struct r300_vertex_stream_state *streams =
1060 (struct r300_vertex_stream_state*)state;
1061 unsigned i;
1062 CS_LOCALS(r300);
1063
1064 if (DBG_ON(r300, DBG_PSC)) {
1065 fprintf(stderr, "r300: PSC emit:\n");
1066
1067 for (i = 0; i < streams->count; i++) {
1068 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
1069 streams->vap_prog_stream_cntl[i]);
1070 }
1071
1072 for (i = 0; i < streams->count; i++) {
1073 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
1074 streams->vap_prog_stream_cntl_ext[i]);
1075 }
1076 }
1077
1078 BEGIN_CS(size);
1079 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
1080 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
1081 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
1082 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
1083 END_CS;
1084 }
1085
r300_emit_pvs_flush(struct r300_context * r300,unsigned size,void * state)1086 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
1087 {
1088 CS_LOCALS(r300);
1089
1090 BEGIN_CS(size);
1091 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1092 END_CS;
1093 }
1094
r300_emit_vap_invariant_state(struct r300_context * r300,unsigned size,void * state)1095 void r300_emit_vap_invariant_state(struct r300_context *r300,
1096 unsigned size, void *state)
1097 {
1098 CS_LOCALS(r300);
1099 WRITE_CS_TABLE(state, size);
1100 }
1101
r300_emit_vs_state(struct r300_context * r300,unsigned size,void * state)1102 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
1103 {
1104 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
1105 struct r300_vertex_program_code* code = &vs->code;
1106 struct r300_screen* r300screen = r300->screen;
1107 unsigned instruction_count = code->length / 4;
1108
1109 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1110 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1111 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1112 unsigned temp_count = MAX2(code->num_temporaries, 1);
1113
1114 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1115 vtx_mem_size / output_count, 10);
1116 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1117
1118 CS_LOCALS(r300);
1119
1120 BEGIN_CS(size);
1121
1122 /* R300_VAP_PVS_CODE_CNTL_0
1123 * R300_VAP_PVS_CONST_CNTL
1124 * R300_VAP_PVS_CODE_CNTL_1
1125 * See the r5xx docs for instructions on how to use these. */
1126 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1127 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1128 R300_PVS_LAST_INST(instruction_count - 1));
1129 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1130
1131 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1132 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1133 OUT_CS_TABLE(code->body.d, code->length);
1134
1135 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1136 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1137 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1138 R300_PVS_VF_MAX_VTX_NUM(12) |
1139 (r300->clip_halfz ? R300_DX_CLIP_SPACE_DEF : 0) |
1140 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1141
1142 /* Emit flow control instructions. Even if there are no fc instructions,
1143 * we still need to write the registers to make sure they are cleared. */
1144 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1145 if (r300screen->caps.is_r500) {
1146 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
1147 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
1148 } else {
1149 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
1150 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
1151 }
1152 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
1153 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
1154
1155 END_CS;
1156 }
1157
r300_emit_vs_constants(struct r300_context * r300,unsigned size,void * state)1158 void r300_emit_vs_constants(struct r300_context* r300,
1159 unsigned size, void *state)
1160 {
1161 unsigned count =
1162 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1163 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1164 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1165 unsigned i;
1166 int imm_first = vs->externals_count;
1167 int imm_end = vs->code.constants.Count;
1168 int imm_count = vs->immediates_count;
1169 CS_LOCALS(r300);
1170
1171 BEGIN_CS(size);
1172 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1173 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1174 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1175 if (vs->externals_count) {
1176 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1177 (r300->screen->caps.is_r500 ?
1178 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1179 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1180 if (buf->remap_table){
1181 for (i = 0; i < count; i++) {
1182 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1183 OUT_CS_TABLE(data, 4);
1184 }
1185 } else {
1186 OUT_CS_TABLE(buf->ptr, count * 4);
1187 }
1188 }
1189
1190 /* Emit immediates. */
1191 if (imm_count) {
1192 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1193 (r300->screen->caps.is_r500 ?
1194 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1195 buf->buffer_base + imm_first);
1196 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1197 for (i = imm_first; i < imm_end; i++) {
1198 const float *data = vs->code.constants.Constants[i].u.Immediate;
1199 OUT_CS_TABLE(data, 4);
1200 }
1201 }
1202 END_CS;
1203 }
1204
r300_emit_viewport_state(struct r300_context * r300,unsigned size,void * state)1205 void r300_emit_viewport_state(struct r300_context* r300,
1206 unsigned size, void* state)
1207 {
1208 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1209 CS_LOCALS(r300);
1210
1211 BEGIN_CS(size);
1212 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1213 OUT_CS_TABLE(&viewport->xscale, 6);
1214 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1215 END_CS;
1216 }
1217
r300_emit_hiz_clear(struct r300_context * r300,unsigned size,void * state)1218 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1219 {
1220 struct pipe_framebuffer_state *fb =
1221 (struct pipe_framebuffer_state*)r300->fb_state.state;
1222 struct r300_resource* tex;
1223 CS_LOCALS(r300);
1224
1225 tex = r300_resource(fb->zsbuf->texture);
1226
1227 BEGIN_CS(size);
1228 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1229 OUT_CS(0);
1230 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1231 OUT_CS(r300->hiz_clear_value);
1232 END_CS;
1233
1234 /* Mark the current zbuffer's hiz ram as in use. */
1235 r300->hiz_in_use = TRUE;
1236 r300->hiz_func = HIZ_FUNC_NONE;
1237 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1238 }
1239
r300_emit_zmask_clear(struct r300_context * r300,unsigned size,void * state)1240 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1241 {
1242 struct pipe_framebuffer_state *fb =
1243 (struct pipe_framebuffer_state*)r300->fb_state.state;
1244 struct r300_resource *tex;
1245 CS_LOCALS(r300);
1246
1247 tex = r300_resource(fb->zsbuf->texture);
1248
1249 BEGIN_CS(size);
1250 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1251 OUT_CS(0);
1252 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1253 OUT_CS(0);
1254 END_CS;
1255
1256 /* Mark the current zbuffer's zmask as in use. */
1257 r300->zmask_in_use = TRUE;
1258 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1259 }
1260
r300_emit_cmask_clear(struct r300_context * r300,unsigned size,void * state)1261 void r300_emit_cmask_clear(struct r300_context *r300, unsigned size, void *state)
1262 {
1263 struct pipe_framebuffer_state *fb =
1264 (struct pipe_framebuffer_state*)r300->fb_state.state;
1265 struct r300_resource *tex;
1266 CS_LOCALS(r300);
1267
1268 tex = r300_resource(fb->cbufs[0]->texture);
1269
1270 BEGIN_CS(size);
1271 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK, 2);
1272 OUT_CS(0);
1273 OUT_CS(tex->tex.cmask_dwords);
1274 OUT_CS(0);
1275 END_CS;
1276
1277 /* Mark the current zbuffer's zmask as in use. */
1278 r300->cmask_in_use = TRUE;
1279 r300_mark_fb_state_dirty(r300, R300_CHANGED_CMASK_ENABLE);
1280 }
1281
r300_emit_ztop_state(struct r300_context * r300,unsigned size,void * state)1282 void r300_emit_ztop_state(struct r300_context* r300,
1283 unsigned size, void* state)
1284 {
1285 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1286 CS_LOCALS(r300);
1287
1288 BEGIN_CS(size);
1289 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1290 END_CS;
1291 }
1292
r300_emit_texture_cache_inval(struct r300_context * r300,unsigned size,void * state)1293 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1294 {
1295 CS_LOCALS(r300);
1296
1297 BEGIN_CS(size);
1298 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1299 END_CS;
1300 }
1301
r300_emit_buffer_validate(struct r300_context * r300,boolean do_validate_vertex_buffers,struct pipe_resource * index_buffer)1302 boolean r300_emit_buffer_validate(struct r300_context *r300,
1303 boolean do_validate_vertex_buffers,
1304 struct pipe_resource *index_buffer)
1305 {
1306 struct pipe_framebuffer_state *fb =
1307 (struct pipe_framebuffer_state*)r300->fb_state.state;
1308 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
1309 struct r300_textures_state *texstate =
1310 (struct r300_textures_state*)r300->textures_state.state;
1311 struct r300_resource *tex;
1312 unsigned i;
1313 boolean flushed = FALSE;
1314
1315 validate:
1316 if (r300->fb_state.dirty) {
1317 /* Color buffers... */
1318 for (i = 0; i < fb->nr_cbufs; i++) {
1319 if (!fb->cbufs[i])
1320 continue;
1321 tex = r300_resource(fb->cbufs[i]->texture);
1322 assert(tex && tex->buf && "cbuf is marked, but NULL!");
1323 r300->rws->cs_add_buffer(r300->cs, tex->buf,
1324 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
1325 r300_surface(fb->cbufs[i])->domain,
1326 tex->b.b.nr_samples > 1 ?
1327 RADEON_PRIO_COLOR_BUFFER_MSAA :
1328 RADEON_PRIO_COLOR_BUFFER);
1329 }
1330 /* ...depth buffer... */
1331 if (fb->zsbuf) {
1332 tex = r300_resource(fb->zsbuf->texture);
1333 assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1334 r300->rws->cs_add_buffer(r300->cs, tex->buf,
1335 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
1336 r300_surface(fb->zsbuf)->domain,
1337 tex->b.b.nr_samples > 1 ?
1338 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1339 RADEON_PRIO_DEPTH_BUFFER);
1340 }
1341 }
1342 /* The AA resolve buffer. */
1343 if (r300->aa_state.dirty) {
1344 if (aa->dest) {
1345 r300->rws->cs_add_buffer(r300->cs, aa->dest->buf,
1346 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED,
1347 aa->dest->domain,
1348 RADEON_PRIO_COLOR_BUFFER);
1349 }
1350 }
1351 if (r300->textures_state.dirty) {
1352 /* ...textures... */
1353 for (i = 0; i < texstate->count; i++) {
1354 if (!(texstate->tx_enable & (1 << i))) {
1355 continue;
1356 }
1357
1358 tex = r300_resource(texstate->sampler_views[i]->base.texture);
1359 r300->rws->cs_add_buffer(r300->cs, tex->buf,
1360 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
1361 tex->domain, RADEON_PRIO_SAMPLER_TEXTURE);
1362 }
1363 }
1364 /* ...occlusion query buffer... */
1365 if (r300->query_current)
1366 r300->rws->cs_add_buffer(r300->cs, r300->query_current->buf,
1367 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED,
1368 RADEON_DOMAIN_GTT,
1369 RADEON_PRIO_QUERY);
1370 /* ...vertex buffer for SWTCL path... */
1371 if (r300->vbo)
1372 r300->rws->cs_add_buffer(r300->cs, r300->vbo,
1373 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
1374 RADEON_DOMAIN_GTT,
1375 RADEON_PRIO_VERTEX_BUFFER);
1376 /* ...vertex buffers for HWTCL path... */
1377 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1378 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1379 struct pipe_vertex_buffer *last = r300->vertex_buffer +
1380 r300->nr_vertex_buffers;
1381 struct pipe_resource *buf;
1382
1383 for (; vbuf != last; vbuf++) {
1384 buf = vbuf->buffer;
1385 if (!buf)
1386 continue;
1387
1388 r300->rws->cs_add_buffer(r300->cs, r300_resource(buf)->buf,
1389 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
1390 r300_resource(buf)->domain,
1391 RADEON_PRIO_SAMPLER_BUFFER);
1392 }
1393 }
1394 /* ...and index buffer for HWTCL path. */
1395 if (index_buffer)
1396 r300->rws->cs_add_buffer(r300->cs, r300_resource(index_buffer)->buf,
1397 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
1398 r300_resource(index_buffer)->domain,
1399 RADEON_PRIO_INDEX_BUFFER);
1400
1401 /* Now do the validation (flush is called inside cs_validate on failure). */
1402 if (!r300->rws->cs_validate(r300->cs)) {
1403 /* Ooops, an infinite loop, give up. */
1404 if (flushed)
1405 return FALSE;
1406
1407 flushed = TRUE;
1408 goto validate;
1409 }
1410
1411 return TRUE;
1412 }
1413
r300_get_num_dirty_dwords(struct r300_context * r300)1414 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1415 {
1416 struct r300_atom* atom;
1417 unsigned dwords = 0;
1418
1419 foreach_dirty_atom(r300, atom) {
1420 if (atom->dirty) {
1421 dwords += atom->size;
1422 }
1423 }
1424
1425 /* let's reserve some more, just in case */
1426 dwords += 32;
1427
1428 return dwords;
1429 }
1430
r300_get_num_cs_end_dwords(struct r300_context * r300)1431 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1432 {
1433 unsigned dwords = 0;
1434
1435 /* Emitted in flush. */
1436 dwords += 26; /* emit_query_end */
1437 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1438 if (r300->screen->caps.is_r500)
1439 dwords += 2; /* emit_index_bias */
1440 dwords += 3; /* MSPOS */
1441
1442 return dwords;
1443 }
1444
1445 /* Emit all dirty state. */
r300_emit_dirty_state(struct r300_context * r300)1446 void r300_emit_dirty_state(struct r300_context* r300)
1447 {
1448 struct r300_atom *atom;
1449
1450 foreach_dirty_atom(r300, atom) {
1451 if (atom->dirty) {
1452 atom->emit(r300, atom->size, atom->state);
1453 atom->dirty = FALSE;
1454 }
1455 }
1456
1457 r300->first_dirty = NULL;
1458 r300->last_dirty = NULL;
1459 r300->dirty_hw++;
1460 }
1461