| /external/compiler-rt/lib/builtins/arm/ |
| D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
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| D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
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| D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
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| D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
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| D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
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| D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
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| D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
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| D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
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| D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
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| D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
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| D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 2396 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12()
2415 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_shifted_reg()
2485 IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8, in mk_EA_reg_plusminus_imm8()
2502 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_reg()
8393 UInt rN = INSN(19,16); in dis_neon_load_or_store() local
10983 UInt rD = 99, rN = 99, rM = 99, rA = 99; in decode_V6MEDIA_instruction() local
12398 UInt rD = 99, rN = 99, rM = 99, rA = 99; in decode_V6MEDIA_instruction() local
12455 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; in decode_V6MEDIA_instruction() local
12544 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; in decode_V6MEDIA_instruction() local
14054 UInt rN, /* base reg */ in mk_ldm_stm()
[all …]
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| D | host_arm64_defs.c | 1025 ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStH()
1035 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStS()
1045 ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStD()
1055 ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { in ARM64Instr_VLdStQ()
3299 UInt rN = iregEnc(i->ARM64in.Arith.argL); in emit_ARM64Instr() local
3325 UInt rN = iregEnc(i->ARM64in.Cmp.argL); in emit_ARM64Instr() local
3352 UInt rN = iregEnc(i->ARM64in.Logic.argL); in emit_ARM64Instr() local
3392 UInt rN = iregEnc(i->ARM64in.Test.argL); in emit_ARM64Instr() local
3411 UInt rN = iregEnc(i->ARM64in.Shift.argL); in emit_ARM64Instr() local
3897 UInt rN = iregEnc(i->ARM64in.VLdStH.rN); in emit_ARM64Instr() local
[all …]
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| D | host_arm_defs.c | 365 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { in mkARMAModeN_RR()
373 ARMAModeN *mkARMAModeN_R ( HReg rN ) { in mkARMAModeN_R()
1534 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { in ARMInstr_Add32()
2953 UInt rN = 0; in imm32_to_ireg() local
3087 UInt rN = iregEnc(i->ARMin.Alu.argL); in emit_ARMInstr() local
3231 HReg rN = am->ARMam2.RI.reg; in emit_ARMInstr() local
3278 HReg rN = am->ARMam2.RI.reg; in emit_ARMInstr() local
3619 UInt rN = iregEnc(i->ARMin.VLdStD.amode->reg); in emit_ARMInstr() local
3635 UInt rN = iregEnc(i->ARMin.VLdStS.amode->reg); in emit_ARMInstr() local
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| D | host_arm64_isel.c | 2217 HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); in iselV128Expr_wrk() local
3064 HReg rN = get_baseblock_register(); in iselDblExpr_wrk() local
3251 HReg rN = get_baseblock_register(); in iselFltExpr_wrk() local
3398 HReg rN = get_baseblock_register(); in iselF16Expr_wrk() local
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| D | host_arm64_defs.h | 712 HReg rN; member
719 HReg rN; member
726 HReg rN; member
733 HReg rN; // address member
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| D | host_arm_defs.h | 215 HReg rN; member
219 HReg rN; member
970 HReg rN; member
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| D | guest_arm64_toIR.c | 2819 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2861 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2927 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
4891 UInt rN = INSN(9,5); in dis_ARM64_load_store() local
5009 UInt rN = INSN(9,5); in dis_ARM64_load_store() local
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| /external/lzma/Asm/x86/ |
| D | XzCrc64Opt.asm | 11 rN equ r10 define
101 rN equ r7 define
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| D | 7zCrcOpt.asm | 9 rN equ r7 define
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| D | AesOpt.asm | 19 rN equ r0 define
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| /external/valgrind/none/tests/arm/ |
| D | vfp.c | 605 #define TESTINSN_VLDR(instruction, dD, rN, rNval, offset) \ argument
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| /external/v8/tools/profviz/ |
| D | gnuplot-4.6.3-emscripten.js | 4496 …0,A=0,B=0,C=0,D=0,E=0,F=0,G=0,H=0,I=0,J=0,K=0,L=0,M=0,N=0,O=0,Q=0,R=0,S=0,T=0,U=0,V=0,W=0,X=0,Y=0,…
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