1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
si_write_harvested_raster_configs(struct radv_physical_device * physical_device,struct radeon_winsys_cs * cs,unsigned raster_config,unsigned raster_config_1)39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 void
si_init_compute(struct radv_physical_device * physical_device,struct radv_cmd_buffer * cmd_buffer)174 si_init_compute(struct radv_physical_device *physical_device,
175 struct radv_cmd_buffer *cmd_buffer)
176 {
177 struct radeon_winsys_cs *cs = cmd_buffer->cs;
178 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182
183 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
184 radeon_emit(cs, 0);
185 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
186 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188
189 if (physical_device->rad_info.chip_class >= CIK) {
190 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
191 radeon_set_sh_reg_seq(cs,
192 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
193 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
194 S_00B864_SH1_CU_EN(0xffff));
195 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
196 S_00B868_SH1_CU_EN(0xffff));
197 }
198
199 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
200 * and is now per pipe, so it should be handled in the
201 * kernel if we want to use something other than the default value,
202 * which is now 0x22f.
203 */
204 if (physical_device->rad_info.chip_class <= SI) {
205 /* XXX: This should be:
206 * (number of compute units) * 4 * (waves per simd) - 1 */
207
208 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
209 0x190 /* Default value */);
210 }
211 }
212
213
si_init_config(struct radv_physical_device * physical_device,struct radv_cmd_buffer * cmd_buffer)214 void si_init_config(struct radv_physical_device *physical_device,
215 struct radv_cmd_buffer *cmd_buffer)
216 {
217 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
218 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
219 unsigned raster_config, raster_config_1;
220 int i;
221 struct radeon_winsys_cs *cs = cmd_buffer->cs;
222 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
223 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
224 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
225
226 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
227 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
228
229 /* FIXME calculate these values somehow ??? */
230 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
231 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
232 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
233
234 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
235 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
236
237 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
238 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
239 if (physical_device->rad_info.chip_class < CIK)
240 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
241 S_008A14_CLIP_VTX_REORDER_ENA(1));
242
243 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
244 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
245
246 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
247
248 for (i = 0; i < 16; i++) {
249 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
250 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
251 }
252
253 switch (physical_device->rad_info.family) {
254 case CHIP_TAHITI:
255 case CHIP_PITCAIRN:
256 raster_config = 0x2a00126a;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_VERDE:
260 raster_config = 0x0000124a;
261 raster_config_1 = 0x00000000;
262 break;
263 case CHIP_OLAND:
264 raster_config = 0x00000082;
265 raster_config_1 = 0x00000000;
266 break;
267 case CHIP_HAINAN:
268 raster_config = 0x00000000;
269 raster_config_1 = 0x00000000;
270 break;
271 case CHIP_BONAIRE:
272 raster_config = 0x16000012;
273 raster_config_1 = 0x00000000;
274 break;
275 case CHIP_HAWAII:
276 raster_config = 0x3a00161a;
277 raster_config_1 = 0x0000002e;
278 break;
279 case CHIP_FIJI:
280 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
281 /* old kernels with old tiling config */
282 raster_config = 0x16000012;
283 raster_config_1 = 0x0000002a;
284 } else {
285 raster_config = 0x3a00161a;
286 raster_config_1 = 0x0000002e;
287 }
288 break;
289 case CHIP_POLARIS10:
290 raster_config = 0x16000012;
291 raster_config_1 = 0x0000002a;
292 break;
293 case CHIP_POLARIS11:
294 raster_config = 0x16000012;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_TONGA:
298 raster_config = 0x16000012;
299 raster_config_1 = 0x0000002a;
300 break;
301 case CHIP_ICELAND:
302 if (num_rb == 1)
303 raster_config = 0x00000000;
304 else
305 raster_config = 0x00000002;
306 raster_config_1 = 0x00000000;
307 break;
308 case CHIP_CARRIZO:
309 raster_config = 0x00000002;
310 raster_config_1 = 0x00000000;
311 break;
312 case CHIP_KAVERI:
313 /* KV should be 0x00000002, but that causes problems with radeon */
314 raster_config = 0x00000000; /* 0x00000002 */
315 raster_config_1 = 0x00000000;
316 break;
317 case CHIP_KABINI:
318 case CHIP_MULLINS:
319 case CHIP_STONEY:
320 raster_config = 0x00000000;
321 raster_config_1 = 0x00000000;
322 break;
323 default:
324 fprintf(stderr,
325 "radeonsi: Unknown GPU, using 0 for raster_config\n");
326 raster_config = 0x00000000;
327 raster_config_1 = 0x00000000;
328 break;
329 }
330
331 /* Always use the default config when all backends are enabled
332 * (or when we failed to determine the enabled backends).
333 */
334 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
335 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
336 raster_config);
337 if (physical_device->rad_info.chip_class >= CIK)
338 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
339 raster_config_1);
340 } else {
341 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
342 }
343
344 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
345 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
346 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
347 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
348 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
349 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
350 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
351
352 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
353 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
354 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
355 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
356 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
357
358 radeon_set_context_reg(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
359 radeon_set_context_reg(cs, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
360 radeon_set_context_reg(cs, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
361 radeon_set_context_reg(cs, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
362
363 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
364 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
365 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
366 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
367 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
368 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
369
370 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
371 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
372 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
373
374 if (physical_device->rad_info.chip_class >= CIK) {
375 /* If this is 0, Bonaire can hang even if GS isn't being used.
376 * Other chips are unaffected. These are suboptimal values,
377 * but we don't use on-chip GS.
378 */
379 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
380 S_028A44_ES_VERTS_PER_SUBGRP(64) |
381 S_028A44_GS_PRIMS_PER_SUBGRP(4));
382
383 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
384 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
385 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
386 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
387
388 if (physical_device->rad_info.num_good_compute_units /
389 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
390 /* Too few available compute units per SH. Disallowing
391 * VS to run on CU0 could hurt us more than late VS
392 * allocation would help.
393 *
394 * LATE_ALLOC_VS = 2 is the highest safe number.
395 */
396 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
397 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
398 } else {
399 /* Set LATE_ALLOC_VS == 31. It should be less than
400 * the number of scratch waves. Limitations:
401 * - VS can't execute on CU0.
402 * - If HS writes outputs to LDS, LS can't execute on CU0.
403 */
404 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
405 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
406 }
407
408 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
409 }
410
411 if (physical_device->rad_info.chip_class >= VI) {
412 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
413 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
414 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
415 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
416 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
417 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
418 S_028B50_ACCUM_ISOLINE(32) |
419 S_028B50_ACCUM_TRI(11) |
420 S_028B50_ACCUM_QUAD(11) |
421 S_028B50_DONUT_SPLIT(16));
422 } else {
423 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
424 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
425 }
426
427 if (physical_device->rad_info.family == CHIP_STONEY)
428 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
429
430 si_init_compute(physical_device, cmd_buffer);
431 }
432
433 static void
get_viewport_xform(const VkViewport * viewport,float scale[3],float translate[3])434 get_viewport_xform(const VkViewport *viewport,
435 float scale[3], float translate[3])
436 {
437 float x = viewport->x;
438 float y = viewport->y;
439 float half_width = 0.5f * viewport->width;
440 float half_height = 0.5f * viewport->height;
441 double n = viewport->minDepth;
442 double f = viewport->maxDepth;
443
444 scale[0] = half_width;
445 translate[0] = half_width + x;
446 scale[1] = half_height;
447 translate[1] = half_height + y;
448
449 scale[2] = (f - n);
450 translate[2] = n;
451 }
452
453 void
si_write_viewport(struct radeon_winsys_cs * cs,int first_vp,int count,const VkViewport * viewports)454 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
455 int count, const VkViewport *viewports)
456 {
457 int i;
458
459 if (count == 0) {
460 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
461 radeon_emit(cs, fui(1.0));
462 radeon_emit(cs, fui(0.0));
463 radeon_emit(cs, fui(1.0));
464 radeon_emit(cs, fui(0.0));
465 radeon_emit(cs, fui(1.0));
466 radeon_emit(cs, fui(0.0));
467
468 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
469 radeon_emit(cs, fui(0.0));
470 radeon_emit(cs, fui(1.0));
471
472 return;
473 }
474 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
475 first_vp * 4 * 6, count * 6);
476
477 for (i = 0; i < count; i++) {
478 float scale[3], translate[3];
479
480
481 get_viewport_xform(&viewports[i], scale, translate);
482 radeon_emit(cs, fui(scale[0]));
483 radeon_emit(cs, fui(translate[0]));
484 radeon_emit(cs, fui(scale[1]));
485 radeon_emit(cs, fui(translate[1]));
486 radeon_emit(cs, fui(scale[2]));
487 radeon_emit(cs, fui(translate[2]));
488 }
489
490 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
491 first_vp * 4 * 2, count * 2);
492 for (i = 0; i < count; i++) {
493 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
494 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
495 radeon_emit(cs, fui(zmin));
496 radeon_emit(cs, fui(zmax));
497 }
498 }
499
500 void
si_write_scissors(struct radeon_winsys_cs * cs,int first,int count,const VkRect2D * scissors)501 si_write_scissors(struct radeon_winsys_cs *cs, int first,
502 int count, const VkRect2D *scissors)
503 {
504 int i;
505 if (count == 0)
506 return;
507
508 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
509 for (i = 0; i < count; i++) {
510 radeon_emit(cs, S_028250_TL_X(scissors[i].offset.x) |
511 S_028250_TL_Y(scissors[i].offset.y) |
512 S_028250_WINDOW_OFFSET_DISABLE(1));
513 radeon_emit(cs, S_028254_BR_X(scissors[i].offset.x + scissors[i].extent.width) |
514 S_028254_BR_Y(scissors[i].offset.y + scissors[i].extent.height));
515 }
516 }
517
518 uint32_t
si_get_ia_multi_vgt_param(struct radv_cmd_buffer * cmd_buffer)519 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer)
520 {
521 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
522 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
523 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
524 unsigned primgroup_size = 128; /* recommended without a GS */
525 unsigned max_primgroup_in_wave = 2;
526 /* SWITCH_ON_EOP(0) is always preferable. */
527 bool wd_switch_on_eop = false;
528 bool ia_switch_on_eop = false;
529 bool ia_switch_on_eoi = false;
530 bool partial_vs_wave = false;
531 bool partial_es_wave = false;
532
533 /* TODO GS */
534
535 /* TODO TES */
536
537 /* TODO linestipple */
538
539 if (chip_class >= CIK) {
540 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
541 * 4 shader engines. Set 1 to pass the assertion below.
542 * The other cases are hardware requirements. */
543 if (info->max_se < 4 ||
544 prim == V_008958_DI_PT_POLYGON ||
545 prim == V_008958_DI_PT_LINELOOP ||
546 prim == V_008958_DI_PT_TRIFAN ||
547 prim == V_008958_DI_PT_TRISTRIP_ADJ)
548 // info->primitive_restart ||
549 // info->count_from_stream_output)
550 wd_switch_on_eop = true;
551
552 /* TODO HAWAII */
553
554 /* Required on CIK and later. */
555 if (info->max_se > 2 && !wd_switch_on_eop)
556 ia_switch_on_eoi = true;
557
558 /* Required by Hawaii and, for some special cases, by VI. */
559 #if 0
560 if (ia_switch_on_eoi &&
561 (sctx->b.family == CHIP_HAWAII ||
562 (sctx->b.chip_class == VI &&
563 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
564 partial_vs_wave = true;
565 #endif
566
567 #if 0
568 /* Instancing bug on Bonaire. */
569 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
570 (info->indirect || info->instance_count > 1))
571 partial_vs_wave = true;
572 #endif
573 /* If the WD switch is false, the IA switch must be false too. */
574 assert(wd_switch_on_eop || !ia_switch_on_eop);
575 }
576 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
577 if (ia_switch_on_eoi)
578 partial_es_wave = true;
579
580 /* GS requirement. */
581 #if 0
582 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
583 partial_es_wave = true;
584 #endif
585
586 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
587 * on multi-SE chips. */
588 #if 0
589 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
590 (info->indirect ||
591 (info->instance_count > 1 &&
592 si_num_prims_for_vertices(info) <= 1)))
593 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
594 #endif
595 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
596 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
597 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
598 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
599 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
600 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
601 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
602 max_primgroup_in_wave : 0);
603
604 }
605
606 void
si_emit_cache_flush(struct radv_cmd_buffer * cmd_buffer)607 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
608 {
609 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
610 unsigned cp_coher_cntl = 0;
611 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
612
613 if (is_compute)
614 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
615 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
616 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
617 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
618 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
619 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
620 RADV_CMD_FLAG_VGT_FLUSH);
621
622 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
623
624 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_ICACHE)
625 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
626 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
627 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
628 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
629 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
630 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
631 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
632 if (chip_class >= VI)
633 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
634 }
635
636 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
637 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
638 S_0085F0_CB0_DEST_BASE_ENA(1) |
639 S_0085F0_CB1_DEST_BASE_ENA(1) |
640 S_0085F0_CB2_DEST_BASE_ENA(1) |
641 S_0085F0_CB3_DEST_BASE_ENA(1) |
642 S_0085F0_CB4_DEST_BASE_ENA(1) |
643 S_0085F0_CB5_DEST_BASE_ENA(1) |
644 S_0085F0_CB6_DEST_BASE_ENA(1) |
645 S_0085F0_CB7_DEST_BASE_ENA(1);
646
647 /* Necessary for DCC */
648 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
649 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
650 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
651 EVENT_INDEX(5));
652 radeon_emit(cmd_buffer->cs, 0);
653 radeon_emit(cmd_buffer->cs, 0);
654 radeon_emit(cmd_buffer->cs, 0);
655 radeon_emit(cmd_buffer->cs, 0);
656 }
657 }
658
659 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
660 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
661 S_0085F0_DB_DEST_BASE_ENA(1);
662 }
663
664 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
665 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
666 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
667 }
668
669 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
670 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
671 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
672 }
673
674 if (!(cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
675 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
676 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
677 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
678 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
679 } else if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
680 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
681 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
682 }
683 }
684
685 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
686 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
687 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
688 }
689
690 /* VGT state sync */
691 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
692 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
693 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
694 }
695
696 /* Make sure ME is idle (it executes most packets) before continuing.
697 * This prevents read-after-write hazards between PFP and ME.
698 */
699 if ((cp_coher_cntl || (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
700 !radv_cmd_buffer_uses_mec(cmd_buffer)) {
701 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
702 radeon_emit(cmd_buffer->cs, 0);
703 }
704
705 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
706 * Therefore, it should be last. Done in PFP.
707 */
708 if (cp_coher_cntl) {
709 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
710 radeon_emit(cmd_buffer->cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
711 PKT3_SHADER_TYPE_S(1));
712 radeon_emit(cmd_buffer->cs, cp_coher_cntl); /* CP_COHER_CNTL */
713 radeon_emit(cmd_buffer->cs, 0xffffffff); /* CP_COHER_SIZE */
714 radeon_emit(cmd_buffer->cs, 0xff); /* CP_COHER_SIZE_HI */
715 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE */
716 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE_HI */
717 radeon_emit(cmd_buffer->cs, 0x0000000A); /* POLL_INTERVAL */
718 } else {
719 /* ACQUIRE_MEM is only required on a compute ring. */
720 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
721 radeon_emit(cmd_buffer->cs, cp_coher_cntl); /* CP_COHER_CNTL */
722 radeon_emit(cmd_buffer->cs, 0xffffffff); /* CP_COHER_SIZE */
723 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE */
724 radeon_emit(cmd_buffer->cs, 0x0000000A); /* POLL_INTERVAL */
725 }
726 }
727
728 if (cmd_buffer->state.flush_bits)
729 radv_cmd_buffer_trace_emit(cmd_buffer);
730 cmd_buffer->state.flush_bits = 0;
731 }
732
733
734 /* Set this if you want the 3D engine to wait until CP DMA is done.
735 * It should be set on the last CP DMA packet. */
736 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
737
738 /* Set this if the source data was used as a destination in a previous CP DMA
739 * packet. It's for preventing a read-after-write (RAW) hazard between two
740 * CP DMA packets. */
741 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
742 #define CIK_CP_DMA_USE_L2 (1 << 2)
743
744 /* Alignment for optimal performance. */
745 #define CP_DMA_ALIGNMENT 32
746 /* The max number of bytes to copy per packet. */
747 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
748
si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer * cmd_buffer,uint64_t dst_va,uint64_t src_va,unsigned size,unsigned flags)749 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
750 uint64_t dst_va, uint64_t src_va,
751 unsigned size, unsigned flags)
752 {
753 struct radeon_winsys_cs *cs = cmd_buffer->cs;
754 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
755 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
756 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
757 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
758 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
759 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
760
761 assert(size);
762 assert((size & ((1<<21)-1)) == size);
763
764 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
765
766 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
767 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
768 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
769 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
770 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
771 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
772 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
773 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
774 } else {
775 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
776 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
777 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
778 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
779 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
780 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
781 }
782
783 /* CP DMA is executed in ME, but index buffers are read by PFP.
784 * This ensures that ME (CP DMA) is idle before PFP starts fetching
785 * indices. If we wanted to execute CP DMA in PFP, this packet
786 * should precede it.
787 */
788 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
789 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
790 radeon_emit(cs, 0);
791 }
792
793 radv_cmd_buffer_trace_emit(cmd_buffer);
794 }
795
796 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer * cmd_buffer,uint64_t dst_va,unsigned size,uint32_t clear_value,unsigned flags)797 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
798 uint64_t dst_va, unsigned size,
799 uint32_t clear_value, unsigned flags)
800 {
801 struct radeon_winsys_cs *cs = cmd_buffer->cs;
802 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
803 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
804 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
805 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
806
807 assert(size);
808 assert((size & ((1<<21)-1)) == size);
809
810 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
811
812 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
813 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
814 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
815 radeon_emit(cs, clear_value); /* DATA [31:0] */
816 radeon_emit(cs, 0);
817 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
818 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
819 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
820 } else {
821 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
822 radeon_emit(cs, clear_value); /* DATA [31:0] */
823 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
824 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
825 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
826 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
827 }
828
829 /* See "copy_buffer" for explanation. */
830 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
831 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
832 radeon_emit(cs, 0);
833 }
834 radv_cmd_buffer_trace_emit(cmd_buffer);
835 }
836
si_cp_dma_prepare(struct radv_cmd_buffer * cmd_buffer,uint64_t byte_count,uint64_t remaining_size,unsigned * flags)837 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
838 uint64_t remaining_size, unsigned *flags)
839 {
840
841 /* Flush the caches for the first copy only.
842 * Also wait for the previous CP DMA operations.
843 */
844 if (cmd_buffer->state.flush_bits) {
845 si_emit_cache_flush(cmd_buffer);
846 *flags |= SI_CP_DMA_RAW_WAIT;
847 }
848
849 /* Do the synchronization after the last dma, so that all data
850 * is written to memory.
851 */
852 if (byte_count == remaining_size)
853 *flags |= R600_CP_DMA_SYNC;
854 }
855
si_cp_dma_realign_engine(struct radv_cmd_buffer * cmd_buffer,unsigned size)856 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
857 {
858 uint64_t va;
859 uint32_t offset;
860 unsigned dma_flags = 0;
861 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
862 void *ptr;
863
864 assert(size < CP_DMA_ALIGNMENT);
865
866 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
867
868 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
869 va += offset;
870
871 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
872
873 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
874 dma_flags);
875 }
876
si_cp_dma_buffer_copy(struct radv_cmd_buffer * cmd_buffer,uint64_t src_va,uint64_t dest_va,uint64_t size)877 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
878 uint64_t src_va, uint64_t dest_va,
879 uint64_t size)
880 {
881 uint64_t main_src_va, main_dest_va;
882 uint64_t skipped_size = 0, realign_size = 0;
883
884
885 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
886 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
887 /* If the size is not aligned, we must add a dummy copy at the end
888 * just to align the internal counter. Otherwise, the DMA engine
889 * would slow down by an order of magnitude for following copies.
890 */
891 if (size % CP_DMA_ALIGNMENT)
892 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
893
894 /* If the copy begins unaligned, we must start copying from the next
895 * aligned block and the skipped part should be copied after everything
896 * else has been copied. Only the src alignment matters, not dst.
897 */
898 if (src_va % CP_DMA_ALIGNMENT) {
899 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
900 /* The main part will be skipped if the size is too small. */
901 skipped_size = MIN2(skipped_size, size);
902 size -= skipped_size;
903 }
904 }
905 main_src_va = src_va + skipped_size;
906 main_dest_va = dest_va + skipped_size;
907
908 while (size) {
909 unsigned dma_flags = 0;
910 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
911
912 si_cp_dma_prepare(cmd_buffer, byte_count,
913 size + skipped_size + realign_size,
914 &dma_flags);
915
916 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
917 byte_count, dma_flags);
918
919 size -= byte_count;
920 main_src_va += byte_count;
921 main_dest_va += byte_count;
922 }
923
924 if (skipped_size) {
925 unsigned dma_flags = 0;
926
927 si_cp_dma_prepare(cmd_buffer, skipped_size,
928 size + skipped_size + realign_size,
929 &dma_flags);
930
931 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
932 skipped_size, dma_flags);
933 }
934 if (realign_size)
935 si_cp_dma_realign_engine(cmd_buffer, realign_size);
936 }
937
si_cp_dma_clear_buffer(struct radv_cmd_buffer * cmd_buffer,uint64_t va,uint64_t size,unsigned value)938 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
939 uint64_t size, unsigned value)
940 {
941
942 if (!size)
943 return;
944
945 assert(va % 4 == 0 && size % 4 == 0);
946
947 while (size) {
948 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
949 unsigned dma_flags = 0;
950
951 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
952
953 /* Emit the clear packet. */
954 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
955 dma_flags);
956
957 size -= byte_count;
958 va += byte_count;
959 }
960 }
961
962 /* For MSAA sample positions. */
963 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
964 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
965 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
966 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
967 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
968
969
970 /* 2xMSAA
971 * There are two locations (4, 4), (-4, -4). */
972 const uint32_t eg_sample_locs_2x[4] = {
973 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
974 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
975 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
976 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
977 };
978 const unsigned eg_max_dist_2x = 4;
979 /* 4xMSAA
980 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
981 const uint32_t eg_sample_locs_4x[4] = {
982 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
983 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
984 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
985 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
986 };
987 const unsigned eg_max_dist_4x = 6;
988
989 /* Cayman 8xMSAA */
990 static const uint32_t cm_sample_locs_8x[] = {
991 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
992 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
993 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
994 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
995 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
996 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
997 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
998 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
999 };
1000 static const unsigned cm_max_dist_8x = 8;
1001 /* Cayman 16xMSAA */
1002 static const uint32_t cm_sample_locs_16x[] = {
1003 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1004 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1005 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1006 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1007 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1008 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1009 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1010 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1011 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1012 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1013 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1014 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1015 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1016 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1017 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1018 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1019 };
1020 static const unsigned cm_max_dist_16x = 8;
1021
radv_cayman_get_maxdist(int log_samples)1022 unsigned radv_cayman_get_maxdist(int log_samples)
1023 {
1024 unsigned max_dist[] = {
1025 0,
1026 eg_max_dist_2x,
1027 eg_max_dist_4x,
1028 cm_max_dist_8x,
1029 cm_max_dist_16x
1030 };
1031 return max_dist[log_samples];
1032 }
1033
radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs * cs,int nr_samples)1034 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1035 {
1036 switch (nr_samples) {
1037 default:
1038 case 1:
1039 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1040 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1041 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1042 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1043 break;
1044 case 2:
1045 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1046 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1047 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1048 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1049 break;
1050 case 4:
1051 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1052 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1053 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1054 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1055 break;
1056 case 8:
1057 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1058 radeon_emit(cs, cm_sample_locs_8x[0]);
1059 radeon_emit(cs, cm_sample_locs_8x[4]);
1060 radeon_emit(cs, 0);
1061 radeon_emit(cs, 0);
1062 radeon_emit(cs, cm_sample_locs_8x[1]);
1063 radeon_emit(cs, cm_sample_locs_8x[5]);
1064 radeon_emit(cs, 0);
1065 radeon_emit(cs, 0);
1066 radeon_emit(cs, cm_sample_locs_8x[2]);
1067 radeon_emit(cs, cm_sample_locs_8x[6]);
1068 radeon_emit(cs, 0);
1069 radeon_emit(cs, 0);
1070 radeon_emit(cs, cm_sample_locs_8x[3]);
1071 radeon_emit(cs, cm_sample_locs_8x[7]);
1072 break;
1073 case 16:
1074 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1075 radeon_emit(cs, cm_sample_locs_16x[0]);
1076 radeon_emit(cs, cm_sample_locs_16x[4]);
1077 radeon_emit(cs, cm_sample_locs_16x[8]);
1078 radeon_emit(cs, cm_sample_locs_16x[12]);
1079 radeon_emit(cs, cm_sample_locs_16x[1]);
1080 radeon_emit(cs, cm_sample_locs_16x[5]);
1081 radeon_emit(cs, cm_sample_locs_16x[9]);
1082 radeon_emit(cs, cm_sample_locs_16x[13]);
1083 radeon_emit(cs, cm_sample_locs_16x[2]);
1084 radeon_emit(cs, cm_sample_locs_16x[6]);
1085 radeon_emit(cs, cm_sample_locs_16x[10]);
1086 radeon_emit(cs, cm_sample_locs_16x[14]);
1087 radeon_emit(cs, cm_sample_locs_16x[3]);
1088 radeon_emit(cs, cm_sample_locs_16x[7]);
1089 radeon_emit(cs, cm_sample_locs_16x[11]);
1090 radeon_emit(cs, cm_sample_locs_16x[15]);
1091 break;
1092 }
1093 }
1094
radv_cayman_get_sample_position(struct radv_device * device,unsigned sample_count,unsigned sample_index,float * out_value)1095 static void radv_cayman_get_sample_position(struct radv_device *device,
1096 unsigned sample_count,
1097 unsigned sample_index, float *out_value)
1098 {
1099 int offset, index;
1100 struct {
1101 int idx:4;
1102 } val;
1103 switch (sample_count) {
1104 case 1:
1105 default:
1106 out_value[0] = out_value[1] = 0.5;
1107 break;
1108 case 2:
1109 offset = 4 * (sample_index * 2);
1110 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1111 out_value[0] = (float)(val.idx + 8) / 16.0f;
1112 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1113 out_value[1] = (float)(val.idx + 8) / 16.0f;
1114 break;
1115 case 4:
1116 offset = 4 * (sample_index * 2);
1117 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1118 out_value[0] = (float)(val.idx + 8) / 16.0f;
1119 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1120 out_value[1] = (float)(val.idx + 8) / 16.0f;
1121 break;
1122 case 8:
1123 offset = 4 * (sample_index % 4 * 2);
1124 index = (sample_index / 4) * 4;
1125 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1126 out_value[0] = (float)(val.idx + 8) / 16.0f;
1127 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1128 out_value[1] = (float)(val.idx + 8) / 16.0f;
1129 break;
1130 case 16:
1131 offset = 4 * (sample_index % 4 * 2);
1132 index = (sample_index / 4) * 4;
1133 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1134 out_value[0] = (float)(val.idx + 8) / 16.0f;
1135 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1136 out_value[1] = (float)(val.idx + 8) / 16.0f;
1137 break;
1138 }
1139 }
1140
radv_device_init_msaa(struct radv_device * device)1141 void radv_device_init_msaa(struct radv_device *device)
1142 {
1143 int i;
1144 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1145
1146 for (i = 0; i < 2; i++)
1147 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1148 for (i = 0; i < 4; i++)
1149 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1150 for (i = 0; i < 8; i++)
1151 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1152 for (i = 0; i < 16; i++)
1153 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1154 }
1155