/external/libvpx/libvpx/vpx_dsp/mips/ |
D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local 128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local 354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local 434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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D | txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
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D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local 110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
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/external/v8/src/interpreter/ |
D | bytecode-register.cc | 107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
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/external/libyuv/files/source/ |
D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local 570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local 610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local 1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local 1159 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local 1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local 1305 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local 1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local [all …]
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D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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D | scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local 296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
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/external/llvm/lib/Target/AArch64/ |
D | AArch64PBQPRegAlloc.cpp | 150 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity()
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/external/vixl/src/aarch64/ |
D | macro-assembler-aarch64.cc | 2721 void UseScratchRegisterScope::Include(const Register& reg1, in Include() 2735 void UseScratchRegisterScope::Include(const FPRegister& reg1, in Include() 2755 void UseScratchRegisterScope::Exclude(const Register& reg1, in Exclude() 2765 void UseScratchRegisterScope::Exclude(const FPRegister& reg1, in Exclude() 2775 void UseScratchRegisterScope::Exclude(const CPURegister& reg1, in Exclude()
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/external/mesa3d/src/gallium/drivers/ilo/shader/ |
D | toy_legalize_ra.c | 82 const int *reg1 = elem1; in linear_scan_compare_regs() local
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/external/v8/src/x87/ |
D | assembler-x87.h | 689 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } in cmp() 774 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } in test()
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/external/syslinux/gpxe/src/drivers/net/ |
D | sky2.c | 596 u32 reg1; in sky2_phy_power_up() local 617 u32 reg1; in sky2_phy_power_down() local
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/external/vixl/test/aarch64/ |
D | test-utils-aarch64.cc | 197 const Register& reg1) { in Equal64()
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/external/aac/libFDK/src/ |
D | fixpoint_math.cpp | 430 FIXP_DBL reg1, reg2, regtmp ; in invSqrtNorm2() local
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/external/mesa3d/src/util/ |
D | register_allocate.c | 234 struct ra_reg *reg1 = ®s->regs[r1]; in ra_add_conflict_list() local
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/external/v8/src/arm/ |
D | macro-assembler-arm.cc | 215 void MacroAssembler::Swap(Register reg1, in Swap() 2840 void MacroAssembler::JumpIfNotBothSmi(Register reg1, in JumpIfNotBothSmi() 2857 void MacroAssembler::JumpIfEitherSmi(Register reg1, in JumpIfEitherSmi() 3709 Register GetRegisterThatIsNotOneOf(Register reg1, in GetRegisterThatIsNotOneOf() 3735 bool AreAliased(Register reg1, in AreAliased()
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/external/vixl/src/aarch32/ |
D | instructions-aarch32.h | 550 VRegisterList(VRegister reg1, VRegister reg2) in VRegisterList() 552 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList() 555 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
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/external/libvpx/libvpx/third_party/libyuv/include/libyuv/ |
D | row.h | 519 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \ argument 547 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \ argument
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/external/pcre/dist2/src/sljit/ |
D | sljitNativeARM_T2_32.c | 63 #define IS_2_LO_REGS(reg1, reg2) \ argument 65 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
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/external/v8/src/compiler/mips64/ |
D | code-generator-mips64.cc | 1040 Register reg1 = kScratchReg; in AssembleArchInstruction() local 1060 Register reg1 = kScratchReg; in AssembleArchInstruction() local 1080 Register reg1 = kScratchReg; in AssembleArchInstruction() local 1124 Register reg1 = kScratchReg; in AssembleArchInstruction() local
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/external/v8/src/full-codegen/arm64/ |
D | full-codegen-arm64.cc | 66 void EmitJumpIfEitherNotSmi(Register reg1, Register reg2, Label* target) { in EmitJumpIfEitherNotSmi() 2691 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands() 2696 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 2702 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | RenderMachineFunction.cpp | 173 unsigned reg1, reg2; in processIntervalRange() local
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/external/v8/src/full-codegen/mips/ |
D | full-codegen-mips.cc | 1522 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands() 1527 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1533 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1539 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
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/external/v8/src/full-codegen/mips64/ |
D | full-codegen-mips64.cc | 1524 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands() 1529 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1535 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1541 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
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/external/v8/src/full-codegen/s390/ |
D | full-codegen-s390.cc | 1448 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands() 1453 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1459 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands() 1465 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
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