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Searched defs:reg1 (Results 1 – 25 of 45) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
Dtxfm_macros_msa.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
/external/v8/src/interpreter/
Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
/external/libyuv/files/source/
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1159 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1305 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
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Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc2721 void UseScratchRegisterScope::Include(const Register& reg1, in Include()
2735 void UseScratchRegisterScope::Include(const FPRegister& reg1, in Include()
2755 void UseScratchRegisterScope::Exclude(const Register& reg1, in Exclude()
2765 void UseScratchRegisterScope::Exclude(const FPRegister& reg1, in Exclude()
2775 void UseScratchRegisterScope::Exclude(const CPURegister& reg1, in Exclude()
/external/mesa3d/src/gallium/drivers/ilo/shader/
Dtoy_legalize_ra.c82 const int *reg1 = elem1; in linear_scan_compare_regs() local
/external/v8/src/x87/
Dassembler-x87.h689 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } in cmp()
774 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } in test()
/external/syslinux/gpxe/src/drivers/net/
Dsky2.c596 u32 reg1; in sky2_phy_power_up() local
617 u32 reg1; in sky2_phy_power_down() local
/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc197 const Register& reg1) { in Equal64()
/external/aac/libFDK/src/
Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; in invSqrtNorm2() local
/external/mesa3d/src/util/
Dregister_allocate.c234 struct ra_reg *reg1 = &regs->regs[r1]; in ra_add_conflict_list() local
/external/v8/src/arm/
Dmacro-assembler-arm.cc215 void MacroAssembler::Swap(Register reg1, in Swap()
2840 void MacroAssembler::JumpIfNotBothSmi(Register reg1, in JumpIfNotBothSmi()
2857 void MacroAssembler::JumpIfEitherSmi(Register reg1, in JumpIfEitherSmi()
3709 Register GetRegisterThatIsNotOneOf(Register reg1, in GetRegisterThatIsNotOneOf()
3735 bool AreAliased(Register reg1, in AreAliased()
/external/vixl/src/aarch32/
Dinstructions-aarch32.h550 VRegisterList(VRegister reg1, VRegister reg2) in VRegisterList()
552 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList()
555 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
/external/libvpx/libvpx/third_party/libyuv/include/libyuv/
Drow.h519 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \ argument
547 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \ argument
/external/pcre/dist2/src/sljit/
DsljitNativeARM_T2_32.c63 #define IS_2_LO_REGS(reg1, reg2) \ argument
65 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
/external/v8/src/compiler/mips64/
Dcode-generator-mips64.cc1040 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1060 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1080 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1124 Register reg1 = kScratchReg; in AssembleArchInstruction() local
/external/v8/src/full-codegen/arm64/
Dfull-codegen-arm64.cc66 void EmitJumpIfEitherNotSmi(Register reg1, Register reg2, Label* target) { in EmitJumpIfEitherNotSmi()
2691 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands()
2696 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
2702 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRenderMachineFunction.cpp173 unsigned reg1, reg2; in processIntervalRange() local
/external/v8/src/full-codegen/mips/
Dfull-codegen-mips.cc1522 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands()
1527 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1533 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1539 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
/external/v8/src/full-codegen/mips64/
Dfull-codegen-mips64.cc1524 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands()
1529 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1535 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1541 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()
/external/v8/src/full-codegen/s390/
Dfull-codegen-s390.cc1448 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { in PushOperands()
1453 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1459 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, in PushOperands()
1465 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { in PopOperands()

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