• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCAsmInfo.h"
18 #include "MipsMCNaCl.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCELFStreamer.h"
22 #include "llvm/MC/MCInstrAnalysis.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/Support/TargetRegistry.h"
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_MC_DESC
35 #include "MipsGenInstrInfo.inc"
36 
37 #define GET_SUBTARGETINFO_MC_DESC
38 #include "MipsGenSubtargetInfo.inc"
39 
40 #define GET_REGINFO_MC_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 /// Select the Mips CPU for the given triple and cpu name.
44 /// FIXME: Merge with the copy in MipsSubtarget.cpp
selectMipsCPU(const Triple & TT,StringRef CPU)45 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
46   if (CPU.empty() || CPU == "generic") {
47     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
48       CPU = "mips32";
49     else
50       CPU = "mips64";
51   }
52   return CPU;
53 }
54 
createMipsMCInstrInfo()55 static MCInstrInfo *createMipsMCInstrInfo() {
56   MCInstrInfo *X = new MCInstrInfo();
57   InitMipsMCInstrInfo(X);
58   return X;
59 }
60 
createMipsMCRegisterInfo(const Triple & TT)61 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
62   MCRegisterInfo *X = new MCRegisterInfo();
63   InitMipsMCRegisterInfo(X, Mips::RA);
64   return X;
65 }
66 
createMipsMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)67 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
68                                                   StringRef CPU, StringRef FS) {
69   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
70   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
71 }
72 
createMipsMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT)73 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
74                                       const Triple &TT) {
75   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
76 
77   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
78   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
79   MAI->addInitialFrameState(Inst);
80 
81   return MAI;
82 }
83 
createMipsMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)84 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
85                                               unsigned SyntaxVariant,
86                                               const MCAsmInfo &MAI,
87                                               const MCInstrInfo &MII,
88                                               const MCRegisterInfo &MRI) {
89   return new MipsInstPrinter(MAI, MII, MRI);
90 }
91 
createMCStreamer(const Triple & T,MCContext & Context,MCAsmBackend & MAB,raw_pwrite_stream & OS,MCCodeEmitter * Emitter,bool RelaxAll)92 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
93                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
94                                     MCCodeEmitter *Emitter, bool RelaxAll) {
95   MCStreamer *S;
96   if (!T.isOSNaCl())
97     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
98   else
99     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
100   return S;
101 }
102 
createMipsAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint,bool isVerboseAsm)103 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
104                                                      formatted_raw_ostream &OS,
105                                                      MCInstPrinter *InstPrint,
106                                                      bool isVerboseAsm) {
107   return new MipsTargetAsmStreamer(S, OS);
108 }
109 
createMipsNullTargetStreamer(MCStreamer & S)110 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
111   return new MipsTargetStreamer(S);
112 }
113 
114 static MCTargetStreamer *
createMipsObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)115 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
116   return new MipsTargetELFStreamer(S, STI);
117 }
118 
119 namespace {
120 
121 class MipsMCInstrAnalysis : public MCInstrAnalysis {
122 public:
MipsMCInstrAnalysis(const MCInstrInfo * Info)123   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
124 
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const125   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
126                       uint64_t &Target) const override {
127     unsigned NumOps = Inst.getNumOperands();
128     if (NumOps == 0)
129       return false;
130     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
131     case MCOI::OPERAND_UNKNOWN:
132     case MCOI::OPERAND_IMMEDIATE:
133       // jal, bal ...
134       Target = Inst.getOperand(NumOps - 1).getImm();
135       return true;
136     case MCOI::OPERAND_PCREL:
137       // b, j, beq ...
138       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
139       return true;
140     default:
141       return false;
142     }
143   }
144 };
145 }
146 
createMipsMCInstrAnalysis(const MCInstrInfo * Info)147 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
148   return new MipsMCInstrAnalysis(Info);
149 }
150 
LLVMInitializeMipsTargetMC()151 extern "C" void LLVMInitializeMipsTargetMC() {
152   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
153                     &TheMips64elTarget}) {
154     // Register the MC asm info.
155     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
156 
157     // Register the MC instruction info.
158     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
159 
160     // Register the MC register info.
161     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
162 
163     // Register the elf streamer.
164     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
165 
166     // Register the asm target streamer.
167     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
168 
169     TargetRegistry::RegisterNullTargetStreamer(*T,
170                                                createMipsNullTargetStreamer);
171 
172     // Register the MC subtarget info.
173     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
174 
175     // Register the MC instruction analyzer.
176     TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
177 
178     // Register the MCInstPrinter.
179     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
180 
181     TargetRegistry::RegisterObjectTargetStreamer(
182         *T, createMipsObjectTargetStreamer);
183   }
184 
185   // Register the MC Code Emitter
186   for (Target *T : {&TheMipsTarget, &TheMips64Target})
187     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
188 
189   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
190     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
191 
192   // Register the asm backend.
193   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
194                                        createMipsAsmBackendEB32);
195   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
196                                        createMipsAsmBackendEL32);
197   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
198                                        createMipsAsmBackendEB64);
199   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
200                                        createMipsAsmBackendEL64);
201 
202 }
203